1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_ABI_USER_H 34 #define MLX5_ABI_USER_H 35 36 #include <linux/types.h> 37 38 enum { 39 MLX5_QP_FLAG_SIGNATURE = 1 << 0, 40 MLX5_QP_FLAG_SCATTER_CQE = 1 << 1, 41 }; 42 43 enum { 44 MLX5_SRQ_FLAG_SIGNATURE = 1 << 0, 45 }; 46 47 enum { 48 MLX5_WQ_FLAG_SIGNATURE = 1 << 0, 49 }; 50 51 /* Increment this value if any changes that break userspace ABI 52 * compatibility are made. 53 */ 54 #define MLX5_IB_UVERBS_ABI_VERSION 1 55 56 /* Make sure that all structs defined in this file remain laid out so 57 * that they pack the same way on 32-bit and 64-bit architectures (to 58 * avoid incompatibility between 32-bit userspace and 64-bit kernels). 59 * In particular do not use pointer types -- pass pointers in __u64 60 * instead. 61 */ 62 63 struct mlx5_ib_alloc_ucontext_req { 64 __u32 total_num_bfregs; 65 __u32 num_low_latency_bfregs; 66 }; 67 68 enum mlx5_lib_caps { 69 MLX5_LIB_CAP_4K_UAR = (u64)1 << 0, 70 }; 71 72 struct mlx5_ib_alloc_ucontext_req_v2 { 73 __u32 total_num_bfregs; 74 __u32 num_low_latency_bfregs; 75 __u32 flags; 76 __u32 comp_mask; 77 __u8 max_cqe_version; 78 __u8 reserved0; 79 __u16 reserved1; 80 __u32 reserved2; 81 __u64 lib_caps; 82 }; 83 84 enum mlx5_ib_alloc_ucontext_resp_mask { 85 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0, 86 }; 87 88 enum mlx5_user_cmds_supp_uhw { 89 MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0, 90 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH = 1 << 1, 91 }; 92 93 /* The eth_min_inline response value is set to off-by-one vs the FW 94 * returned value to allow user-space to deal with older kernels. 95 */ 96 enum mlx5_user_inline_mode { 97 MLX5_USER_INLINE_MODE_NA, 98 MLX5_USER_INLINE_MODE_NONE, 99 MLX5_USER_INLINE_MODE_L2, 100 MLX5_USER_INLINE_MODE_IP, 101 MLX5_USER_INLINE_MODE_TCP_UDP, 102 }; 103 104 struct mlx5_ib_alloc_ucontext_resp { 105 __u32 qp_tab_size; 106 __u32 bf_reg_size; 107 __u32 tot_bfregs; 108 __u32 cache_line_size; 109 __u16 max_sq_desc_sz; 110 __u16 max_rq_desc_sz; 111 __u32 max_send_wqebb; 112 __u32 max_recv_wr; 113 __u32 max_srq_recv_wr; 114 __u16 num_ports; 115 __u16 reserved1; 116 __u32 comp_mask; 117 __u32 response_length; 118 __u8 cqe_version; 119 __u8 cmds_supp_uhw; 120 __u8 eth_min_inline; 121 __u8 reserved2; 122 __u64 hca_core_clock_offset; 123 __u32 log_uar_size; 124 __u32 num_uars_per_page; 125 }; 126 127 struct mlx5_ib_alloc_pd_resp { 128 __u32 pdn; 129 }; 130 131 struct mlx5_ib_tso_caps { 132 __u32 max_tso; /* Maximum tso payload size in bytes */ 133 134 /* Corresponding bit will be set if qp type from 135 * 'enum ib_qp_type' is supported, e.g. 136 * supported_qpts |= 1 << IB_QPT_UD 137 */ 138 __u32 supported_qpts; 139 }; 140 141 struct mlx5_ib_rss_caps { 142 __u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */ 143 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */ 144 __u8 reserved[7]; 145 }; 146 147 enum mlx5_ib_cqe_comp_res_format { 148 MLX5_IB_CQE_RES_FORMAT_HASH = 1 << 0, 149 MLX5_IB_CQE_RES_FORMAT_CSUM = 1 << 1, 150 MLX5_IB_CQE_RES_RESERVED = 1 << 2, 151 }; 152 153 struct mlx5_ib_cqe_comp_caps { 154 __u32 max_num; 155 __u32 supported_format; /* enum mlx5_ib_cqe_comp_res_format */ 156 }; 157 158 struct mlx5_packet_pacing_caps { 159 __u32 qp_rate_limit_min; 160 __u32 qp_rate_limit_max; /* In kpbs */ 161 162 /* Corresponding bit will be set if qp type from 163 * 'enum ib_qp_type' is supported, e.g. 164 * supported_qpts |= 1 << IB_QPT_RAW_PACKET 165 */ 166 __u32 supported_qpts; 167 __u32 reserved; 168 }; 169 170 struct mlx5_ib_query_device_resp { 171 __u32 comp_mask; 172 __u32 response_length; 173 struct mlx5_ib_tso_caps tso_caps; 174 struct mlx5_ib_rss_caps rss_caps; 175 struct mlx5_ib_cqe_comp_caps cqe_comp_caps; 176 struct mlx5_packet_pacing_caps packet_pacing_caps; 177 __u32 mlx5_ib_support_multi_pkt_send_wqes; 178 __u32 reserved; 179 }; 180 181 struct mlx5_ib_create_cq { 182 __u64 buf_addr; 183 __u64 db_addr; 184 __u32 cqe_size; 185 __u8 cqe_comp_en; 186 __u8 cqe_comp_res_format; 187 __u16 reserved; /* explicit padding (optional on i386) */ 188 }; 189 190 struct mlx5_ib_create_cq_resp { 191 __u32 cqn; 192 __u32 reserved; 193 }; 194 195 struct mlx5_ib_resize_cq { 196 __u64 buf_addr; 197 __u16 cqe_size; 198 __u16 reserved0; 199 __u32 reserved1; 200 }; 201 202 struct mlx5_ib_create_srq { 203 __u64 buf_addr; 204 __u64 db_addr; 205 __u32 flags; 206 __u32 reserved0; /* explicit padding (optional on i386) */ 207 __u32 uidx; 208 __u32 reserved1; 209 }; 210 211 struct mlx5_ib_create_srq_resp { 212 __u32 srqn; 213 __u32 reserved; 214 }; 215 216 struct mlx5_ib_create_qp { 217 __u64 buf_addr; 218 __u64 db_addr; 219 __u32 sq_wqe_count; 220 __u32 rq_wqe_count; 221 __u32 rq_wqe_shift; 222 __u32 flags; 223 __u32 uidx; 224 __u32 reserved0; 225 __u64 sq_buf_addr; 226 }; 227 228 /* RX Hash function flags */ 229 enum mlx5_rx_hash_function_flags { 230 MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0, 231 }; 232 233 /* 234 * RX Hash flags, these flags allows to set which incoming packet's field should 235 * participates in RX Hash. Each flag represent certain packet's field, 236 * when the flag is set the field that is represented by the flag will 237 * participate in RX Hash calculation. 238 * Note: *IPV4 and *IPV6 flags can't be enabled together on the same QP 239 * and *TCP and *UDP flags can't be enabled together on the same QP. 240 */ 241 enum mlx5_rx_hash_fields { 242 MLX5_RX_HASH_SRC_IPV4 = 1 << 0, 243 MLX5_RX_HASH_DST_IPV4 = 1 << 1, 244 MLX5_RX_HASH_SRC_IPV6 = 1 << 2, 245 MLX5_RX_HASH_DST_IPV6 = 1 << 3, 246 MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4, 247 MLX5_RX_HASH_DST_PORT_TCP = 1 << 5, 248 MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6, 249 MLX5_RX_HASH_DST_PORT_UDP = 1 << 7 250 }; 251 252 struct mlx5_ib_create_qp_rss { 253 __u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */ 254 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */ 255 __u8 rx_key_len; /* valid only for Toeplitz */ 256 __u8 reserved[6]; 257 __u8 rx_hash_key[128]; /* valid only for Toeplitz */ 258 __u32 comp_mask; 259 __u32 reserved1; 260 }; 261 262 struct mlx5_ib_create_qp_resp { 263 __u32 bfreg_index; 264 }; 265 266 struct mlx5_ib_alloc_mw { 267 __u32 comp_mask; 268 __u8 num_klms; 269 __u8 reserved1; 270 __u16 reserved2; 271 }; 272 273 struct mlx5_ib_create_wq { 274 __u64 buf_addr; 275 __u64 db_addr; 276 __u32 rq_wqe_count; 277 __u32 rq_wqe_shift; 278 __u32 user_index; 279 __u32 flags; 280 __u32 comp_mask; 281 __u32 reserved; 282 }; 283 284 struct mlx5_ib_create_ah_resp { 285 __u32 response_length; 286 __u8 dmac[ETH_ALEN]; 287 __u8 reserved[6]; 288 }; 289 290 struct mlx5_ib_create_wq_resp { 291 __u32 response_length; 292 __u32 reserved; 293 }; 294 295 struct mlx5_ib_create_rwq_ind_tbl_resp { 296 __u32 response_length; 297 __u32 reserved; 298 }; 299 300 struct mlx5_ib_modify_wq { 301 __u32 comp_mask; 302 __u32 reserved; 303 }; 304 #endif /* MLX5_ABI_USER_H */ 305