1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) */ 2 /* 3 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #ifndef MLX5_ABI_USER_H 35 #define MLX5_ABI_USER_H 36 37 #include <linux/types.h> 38 #include <linux/if_ether.h> /* For ETH_ALEN. */ 39 40 enum { 41 MLX5_QP_FLAG_SIGNATURE = 1 << 0, 42 MLX5_QP_FLAG_SCATTER_CQE = 1 << 1, 43 MLX5_QP_FLAG_TUNNEL_OFFLOADS = 1 << 2, 44 MLX5_QP_FLAG_BFREG_INDEX = 1 << 3, 45 MLX5_QP_FLAG_TYPE_DCT = 1 << 4, 46 MLX5_QP_FLAG_TYPE_DCI = 1 << 5, 47 }; 48 49 enum { 50 MLX5_SRQ_FLAG_SIGNATURE = 1 << 0, 51 }; 52 53 enum { 54 MLX5_WQ_FLAG_SIGNATURE = 1 << 0, 55 }; 56 57 /* Increment this value if any changes that break userspace ABI 58 * compatibility are made. 59 */ 60 #define MLX5_IB_UVERBS_ABI_VERSION 1 61 62 /* Make sure that all structs defined in this file remain laid out so 63 * that they pack the same way on 32-bit and 64-bit architectures (to 64 * avoid incompatibility between 32-bit userspace and 64-bit kernels). 65 * In particular do not use pointer types -- pass pointers in __u64 66 * instead. 67 */ 68 69 struct mlx5_ib_alloc_ucontext_req { 70 __u32 total_num_bfregs; 71 __u32 num_low_latency_bfregs; 72 }; 73 74 enum mlx5_lib_caps { 75 MLX5_LIB_CAP_4K_UAR = (__u64)1 << 0, 76 }; 77 78 struct mlx5_ib_alloc_ucontext_req_v2 { 79 __u32 total_num_bfregs; 80 __u32 num_low_latency_bfregs; 81 __u32 flags; 82 __u32 comp_mask; 83 __u8 max_cqe_version; 84 __u8 reserved0; 85 __u16 reserved1; 86 __u32 reserved2; 87 __u64 lib_caps; 88 }; 89 90 enum mlx5_ib_alloc_ucontext_resp_mask { 91 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0, 92 }; 93 94 enum mlx5_user_cmds_supp_uhw { 95 MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0, 96 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH = 1 << 1, 97 }; 98 99 /* The eth_min_inline response value is set to off-by-one vs the FW 100 * returned value to allow user-space to deal with older kernels. 101 */ 102 enum mlx5_user_inline_mode { 103 MLX5_USER_INLINE_MODE_NA, 104 MLX5_USER_INLINE_MODE_NONE, 105 MLX5_USER_INLINE_MODE_L2, 106 MLX5_USER_INLINE_MODE_IP, 107 MLX5_USER_INLINE_MODE_TCP_UDP, 108 }; 109 110 struct mlx5_ib_alloc_ucontext_resp { 111 __u32 qp_tab_size; 112 __u32 bf_reg_size; 113 __u32 tot_bfregs; 114 __u32 cache_line_size; 115 __u16 max_sq_desc_sz; 116 __u16 max_rq_desc_sz; 117 __u32 max_send_wqebb; 118 __u32 max_recv_wr; 119 __u32 max_srq_recv_wr; 120 __u16 num_ports; 121 __u16 reserved1; 122 __u32 comp_mask; 123 __u32 response_length; 124 __u8 cqe_version; 125 __u8 cmds_supp_uhw; 126 __u8 eth_min_inline; 127 __u8 clock_info_versions; 128 __u64 hca_core_clock_offset; 129 __u32 log_uar_size; 130 __u32 num_uars_per_page; 131 __u32 num_dyn_bfregs; 132 __u32 reserved3; 133 }; 134 135 struct mlx5_ib_alloc_pd_resp { 136 __u32 pdn; 137 }; 138 139 struct mlx5_ib_tso_caps { 140 __u32 max_tso; /* Maximum tso payload size in bytes */ 141 142 /* Corresponding bit will be set if qp type from 143 * 'enum ib_qp_type' is supported, e.g. 144 * supported_qpts |= 1 << IB_QPT_UD 145 */ 146 __u32 supported_qpts; 147 }; 148 149 struct mlx5_ib_rss_caps { 150 __u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */ 151 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */ 152 __u8 reserved[7]; 153 }; 154 155 enum mlx5_ib_cqe_comp_res_format { 156 MLX5_IB_CQE_RES_FORMAT_HASH = 1 << 0, 157 MLX5_IB_CQE_RES_FORMAT_CSUM = 1 << 1, 158 MLX5_IB_CQE_RES_RESERVED = 1 << 2, 159 }; 160 161 struct mlx5_ib_cqe_comp_caps { 162 __u32 max_num; 163 __u32 supported_format; /* enum mlx5_ib_cqe_comp_res_format */ 164 }; 165 166 struct mlx5_packet_pacing_caps { 167 __u32 qp_rate_limit_min; 168 __u32 qp_rate_limit_max; /* In kpbs */ 169 170 /* Corresponding bit will be set if qp type from 171 * 'enum ib_qp_type' is supported, e.g. 172 * supported_qpts |= 1 << IB_QPT_RAW_PACKET 173 */ 174 __u32 supported_qpts; 175 __u32 reserved; 176 }; 177 178 enum mlx5_ib_mpw_caps { 179 MPW_RESERVED = 1 << 0, 180 MLX5_IB_ALLOW_MPW = 1 << 1, 181 MLX5_IB_SUPPORT_EMPW = 1 << 2, 182 }; 183 184 enum mlx5_ib_sw_parsing_offloads { 185 MLX5_IB_SW_PARSING = 1 << 0, 186 MLX5_IB_SW_PARSING_CSUM = 1 << 1, 187 MLX5_IB_SW_PARSING_LSO = 1 << 2, 188 }; 189 190 struct mlx5_ib_sw_parsing_caps { 191 __u32 sw_parsing_offloads; /* enum mlx5_ib_sw_parsing_offloads */ 192 193 /* Corresponding bit will be set if qp type from 194 * 'enum ib_qp_type' is supported, e.g. 195 * supported_qpts |= 1 << IB_QPT_RAW_PACKET 196 */ 197 __u32 supported_qpts; 198 }; 199 200 struct mlx5_ib_striding_rq_caps { 201 __u32 min_single_stride_log_num_of_bytes; 202 __u32 max_single_stride_log_num_of_bytes; 203 __u32 min_single_wqe_log_num_of_strides; 204 __u32 max_single_wqe_log_num_of_strides; 205 206 /* Corresponding bit will be set if qp type from 207 * 'enum ib_qp_type' is supported, e.g. 208 * supported_qpts |= 1 << IB_QPT_RAW_PACKET 209 */ 210 __u32 supported_qpts; 211 __u32 reserved; 212 }; 213 214 enum mlx5_ib_query_dev_resp_flags { 215 /* Support 128B CQE compression */ 216 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP = 1 << 0, 217 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD = 1 << 1, 218 }; 219 220 enum mlx5_ib_tunnel_offloads { 221 MLX5_IB_TUNNELED_OFFLOADS_VXLAN = 1 << 0, 222 MLX5_IB_TUNNELED_OFFLOADS_GRE = 1 << 1, 223 MLX5_IB_TUNNELED_OFFLOADS_GENEVE = 1 << 2 224 }; 225 226 struct mlx5_ib_query_device_resp { 227 __u32 comp_mask; 228 __u32 response_length; 229 struct mlx5_ib_tso_caps tso_caps; 230 struct mlx5_ib_rss_caps rss_caps; 231 struct mlx5_ib_cqe_comp_caps cqe_comp_caps; 232 struct mlx5_packet_pacing_caps packet_pacing_caps; 233 __u32 mlx5_ib_support_multi_pkt_send_wqes; 234 __u32 flags; /* Use enum mlx5_ib_query_dev_resp_flags */ 235 struct mlx5_ib_sw_parsing_caps sw_parsing_caps; 236 struct mlx5_ib_striding_rq_caps striding_rq_caps; 237 __u32 tunnel_offloads_caps; /* enum mlx5_ib_tunnel_offloads */ 238 __u32 reserved; 239 }; 240 241 enum mlx5_ib_create_cq_flags { 242 MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD = 1 << 0, 243 }; 244 245 struct mlx5_ib_create_cq { 246 __u64 buf_addr; 247 __u64 db_addr; 248 __u32 cqe_size; 249 __u8 cqe_comp_en; 250 __u8 cqe_comp_res_format; 251 __u16 flags; 252 }; 253 254 struct mlx5_ib_create_cq_resp { 255 __u32 cqn; 256 __u32 reserved; 257 }; 258 259 struct mlx5_ib_resize_cq { 260 __u64 buf_addr; 261 __u16 cqe_size; 262 __u16 reserved0; 263 __u32 reserved1; 264 }; 265 266 struct mlx5_ib_create_srq { 267 __u64 buf_addr; 268 __u64 db_addr; 269 __u32 flags; 270 __u32 reserved0; /* explicit padding (optional on i386) */ 271 __u32 uidx; 272 __u32 reserved1; 273 }; 274 275 struct mlx5_ib_create_srq_resp { 276 __u32 srqn; 277 __u32 reserved; 278 }; 279 280 struct mlx5_ib_create_qp { 281 __u64 buf_addr; 282 __u64 db_addr; 283 __u32 sq_wqe_count; 284 __u32 rq_wqe_count; 285 __u32 rq_wqe_shift; 286 __u32 flags; 287 __u32 uidx; 288 __u32 bfreg_index; 289 union { 290 __u64 sq_buf_addr; 291 __u64 access_key; 292 }; 293 }; 294 295 /* RX Hash function flags */ 296 enum mlx5_rx_hash_function_flags { 297 MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0, 298 }; 299 300 /* 301 * RX Hash flags, these flags allows to set which incoming packet's field should 302 * participates in RX Hash. Each flag represent certain packet's field, 303 * when the flag is set the field that is represented by the flag will 304 * participate in RX Hash calculation. 305 * Note: *IPV4 and *IPV6 flags can't be enabled together on the same QP 306 * and *TCP and *UDP flags can't be enabled together on the same QP. 307 */ 308 enum mlx5_rx_hash_fields { 309 MLX5_RX_HASH_SRC_IPV4 = 1 << 0, 310 MLX5_RX_HASH_DST_IPV4 = 1 << 1, 311 MLX5_RX_HASH_SRC_IPV6 = 1 << 2, 312 MLX5_RX_HASH_DST_IPV6 = 1 << 3, 313 MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4, 314 MLX5_RX_HASH_DST_PORT_TCP = 1 << 5, 315 MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6, 316 MLX5_RX_HASH_DST_PORT_UDP = 1 << 7, 317 /* Save bits for future fields */ 318 MLX5_RX_HASH_INNER = (1UL << 31), 319 }; 320 321 struct mlx5_ib_create_qp_rss { 322 __u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */ 323 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */ 324 __u8 rx_key_len; /* valid only for Toeplitz */ 325 __u8 reserved[6]; 326 __u8 rx_hash_key[128]; /* valid only for Toeplitz */ 327 __u32 comp_mask; 328 __u32 flags; 329 }; 330 331 struct mlx5_ib_create_qp_resp { 332 __u32 bfreg_index; 333 }; 334 335 struct mlx5_ib_alloc_mw { 336 __u32 comp_mask; 337 __u8 num_klms; 338 __u8 reserved1; 339 __u16 reserved2; 340 }; 341 342 enum mlx5_ib_create_wq_mask { 343 MLX5_IB_CREATE_WQ_STRIDING_RQ = (1 << 0), 344 }; 345 346 struct mlx5_ib_create_wq { 347 __u64 buf_addr; 348 __u64 db_addr; 349 __u32 rq_wqe_count; 350 __u32 rq_wqe_shift; 351 __u32 user_index; 352 __u32 flags; 353 __u32 comp_mask; 354 __u32 single_stride_log_num_of_bytes; 355 __u32 single_wqe_log_num_of_strides; 356 __u32 two_byte_shift_en; 357 }; 358 359 struct mlx5_ib_create_ah_resp { 360 __u32 response_length; 361 __u8 dmac[ETH_ALEN]; 362 __u8 reserved[6]; 363 }; 364 365 struct mlx5_ib_modify_qp_resp { 366 __u32 response_length; 367 __u32 dctn; 368 }; 369 370 struct mlx5_ib_create_wq_resp { 371 __u32 response_length; 372 __u32 reserved; 373 }; 374 375 struct mlx5_ib_create_rwq_ind_tbl_resp { 376 __u32 response_length; 377 __u32 reserved; 378 }; 379 380 struct mlx5_ib_modify_wq { 381 __u32 comp_mask; 382 __u32 reserved; 383 }; 384 385 struct mlx5_ib_clock_info { 386 __u32 sign; 387 __u32 resv; 388 __u64 nsec; 389 __u64 cycles; 390 __u64 frac; 391 __u32 mult; 392 __u32 shift; 393 __u64 mask; 394 __u64 overflow_period; 395 }; 396 397 enum mlx5_ib_mmap_cmd { 398 MLX5_IB_MMAP_REGULAR_PAGE = 0, 399 MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1, 400 MLX5_IB_MMAP_WC_PAGE = 2, 401 MLX5_IB_MMAP_NC_PAGE = 3, 402 /* 5 is chosen in order to be compatible with old versions of libmlx5 */ 403 MLX5_IB_MMAP_CORE_CLOCK = 5, 404 MLX5_IB_MMAP_ALLOC_WC = 6, 405 MLX5_IB_MMAP_CLOCK_INFO = 7, 406 }; 407 408 enum { 409 MLX5_IB_CLOCK_INFO_KERNEL_UPDATING = 1, 410 }; 411 412 /* Bit indexes for the mlx5_alloc_ucontext_resp.clock_info_versions bitmap */ 413 enum { 414 MLX5_IB_CLOCK_INFO_V1 = 0, 415 }; 416 #endif /* MLX5_ABI_USER_H */ 417