1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) */ 2 /* 3 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #ifndef MLX5_ABI_USER_H 35 #define MLX5_ABI_USER_H 36 37 #include <linux/types.h> 38 #include <linux/if_ether.h> /* For ETH_ALEN. */ 39 #include <rdma/ib_user_ioctl_verbs.h> 40 41 enum { 42 MLX5_QP_FLAG_SIGNATURE = 1 << 0, 43 MLX5_QP_FLAG_SCATTER_CQE = 1 << 1, 44 MLX5_QP_FLAG_TUNNEL_OFFLOADS = 1 << 2, 45 MLX5_QP_FLAG_BFREG_INDEX = 1 << 3, 46 MLX5_QP_FLAG_TYPE_DCT = 1 << 4, 47 MLX5_QP_FLAG_TYPE_DCI = 1 << 5, 48 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC = 1 << 6, 49 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC = 1 << 7, 50 MLX5_QP_FLAG_ALLOW_SCATTER_CQE = 1 << 8, 51 MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE = 1 << 9, 52 MLX5_QP_FLAG_UAR_PAGE_INDEX = 1 << 10, 53 MLX5_QP_FLAG_DCI_STREAM = 1 << 11, 54 }; 55 56 enum { 57 MLX5_SRQ_FLAG_SIGNATURE = 1 << 0, 58 }; 59 60 enum { 61 MLX5_WQ_FLAG_SIGNATURE = 1 << 0, 62 }; 63 64 /* Increment this value if any changes that break userspace ABI 65 * compatibility are made. 66 */ 67 #define MLX5_IB_UVERBS_ABI_VERSION 1 68 69 /* Make sure that all structs defined in this file remain laid out so 70 * that they pack the same way on 32-bit and 64-bit architectures (to 71 * avoid incompatibility between 32-bit userspace and 64-bit kernels). 72 * In particular do not use pointer types -- pass pointers in __u64 73 * instead. 74 */ 75 76 struct mlx5_ib_alloc_ucontext_req { 77 __u32 total_num_bfregs; 78 __u32 num_low_latency_bfregs; 79 }; 80 81 enum mlx5_lib_caps { 82 MLX5_LIB_CAP_4K_UAR = (__u64)1 << 0, 83 MLX5_LIB_CAP_DYN_UAR = (__u64)1 << 1, 84 }; 85 86 enum mlx5_ib_alloc_uctx_v2_flags { 87 MLX5_IB_ALLOC_UCTX_DEVX = 1 << 0, 88 }; 89 struct mlx5_ib_alloc_ucontext_req_v2 { 90 __u32 total_num_bfregs; 91 __u32 num_low_latency_bfregs; 92 __u32 flags; 93 __u32 comp_mask; 94 __u8 max_cqe_version; 95 __u8 reserved0; 96 __u16 reserved1; 97 __u32 reserved2; 98 __aligned_u64 lib_caps; 99 }; 100 101 enum mlx5_ib_alloc_ucontext_resp_mask { 102 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0, 103 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY = 1UL << 1, 104 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE = 1UL << 2, 105 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS = 1UL << 3, 106 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_TIME_TS = 1UL << 4, 107 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_MKEY_UPDATE_TAG = 1UL << 5, 108 }; 109 110 enum mlx5_user_cmds_supp_uhw { 111 MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0, 112 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH = 1 << 1, 113 }; 114 115 /* The eth_min_inline response value is set to off-by-one vs the FW 116 * returned value to allow user-space to deal with older kernels. 117 */ 118 enum mlx5_user_inline_mode { 119 MLX5_USER_INLINE_MODE_NA, 120 MLX5_USER_INLINE_MODE_NONE, 121 MLX5_USER_INLINE_MODE_L2, 122 MLX5_USER_INLINE_MODE_IP, 123 MLX5_USER_INLINE_MODE_TCP_UDP, 124 }; 125 126 enum { 127 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM = 1 << 0, 128 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA = 1 << 1, 129 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING = 1 << 2, 130 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD = 1 << 3, 131 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN = 1 << 4, 132 }; 133 134 struct mlx5_ib_alloc_ucontext_resp { 135 __u32 qp_tab_size; 136 __u32 bf_reg_size; 137 __u32 tot_bfregs; 138 __u32 cache_line_size; 139 __u16 max_sq_desc_sz; 140 __u16 max_rq_desc_sz; 141 __u32 max_send_wqebb; 142 __u32 max_recv_wr; 143 __u32 max_srq_recv_wr; 144 __u16 num_ports; 145 __u16 flow_action_flags; 146 __u32 comp_mask; 147 __u32 response_length; 148 __u8 cqe_version; 149 __u8 cmds_supp_uhw; 150 __u8 eth_min_inline; 151 __u8 clock_info_versions; 152 __aligned_u64 hca_core_clock_offset; 153 __u32 log_uar_size; 154 __u32 num_uars_per_page; 155 __u32 num_dyn_bfregs; 156 __u32 dump_fill_mkey; 157 }; 158 159 struct mlx5_ib_alloc_pd_resp { 160 __u32 pdn; 161 }; 162 163 struct mlx5_ib_tso_caps { 164 __u32 max_tso; /* Maximum tso payload size in bytes */ 165 166 /* Corresponding bit will be set if qp type from 167 * 'enum ib_qp_type' is supported, e.g. 168 * supported_qpts |= 1 << IB_QPT_UD 169 */ 170 __u32 supported_qpts; 171 }; 172 173 struct mlx5_ib_rss_caps { 174 __aligned_u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */ 175 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */ 176 __u8 reserved[7]; 177 }; 178 179 enum mlx5_ib_cqe_comp_res_format { 180 MLX5_IB_CQE_RES_FORMAT_HASH = 1 << 0, 181 MLX5_IB_CQE_RES_FORMAT_CSUM = 1 << 1, 182 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX = 1 << 2, 183 }; 184 185 struct mlx5_ib_cqe_comp_caps { 186 __u32 max_num; 187 __u32 supported_format; /* enum mlx5_ib_cqe_comp_res_format */ 188 }; 189 190 enum mlx5_ib_packet_pacing_cap_flags { 191 MLX5_IB_PP_SUPPORT_BURST = 1 << 0, 192 }; 193 194 struct mlx5_packet_pacing_caps { 195 __u32 qp_rate_limit_min; 196 __u32 qp_rate_limit_max; /* In kpbs */ 197 198 /* Corresponding bit will be set if qp type from 199 * 'enum ib_qp_type' is supported, e.g. 200 * supported_qpts |= 1 << IB_QPT_RAW_PACKET 201 */ 202 __u32 supported_qpts; 203 __u8 cap_flags; /* enum mlx5_ib_packet_pacing_cap_flags */ 204 __u8 reserved[3]; 205 }; 206 207 enum mlx5_ib_mpw_caps { 208 MPW_RESERVED = 1 << 0, 209 MLX5_IB_ALLOW_MPW = 1 << 1, 210 MLX5_IB_SUPPORT_EMPW = 1 << 2, 211 }; 212 213 enum mlx5_ib_sw_parsing_offloads { 214 MLX5_IB_SW_PARSING = 1 << 0, 215 MLX5_IB_SW_PARSING_CSUM = 1 << 1, 216 MLX5_IB_SW_PARSING_LSO = 1 << 2, 217 }; 218 219 struct mlx5_ib_sw_parsing_caps { 220 __u32 sw_parsing_offloads; /* enum mlx5_ib_sw_parsing_offloads */ 221 222 /* Corresponding bit will be set if qp type from 223 * 'enum ib_qp_type' is supported, e.g. 224 * supported_qpts |= 1 << IB_QPT_RAW_PACKET 225 */ 226 __u32 supported_qpts; 227 }; 228 229 struct mlx5_ib_striding_rq_caps { 230 __u32 min_single_stride_log_num_of_bytes; 231 __u32 max_single_stride_log_num_of_bytes; 232 __u32 min_single_wqe_log_num_of_strides; 233 __u32 max_single_wqe_log_num_of_strides; 234 235 /* Corresponding bit will be set if qp type from 236 * 'enum ib_qp_type' is supported, e.g. 237 * supported_qpts |= 1 << IB_QPT_RAW_PACKET 238 */ 239 __u32 supported_qpts; 240 __u32 reserved; 241 }; 242 243 struct mlx5_ib_dci_streams_caps { 244 __u8 max_log_num_concurent; 245 __u8 max_log_num_errored; 246 }; 247 248 enum mlx5_ib_query_dev_resp_flags { 249 /* Support 128B CQE compression */ 250 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP = 1 << 0, 251 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD = 1 << 1, 252 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE = 1 << 2, 253 MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT = 1 << 3, 254 }; 255 256 enum mlx5_ib_tunnel_offloads { 257 MLX5_IB_TUNNELED_OFFLOADS_VXLAN = 1 << 0, 258 MLX5_IB_TUNNELED_OFFLOADS_GRE = 1 << 1, 259 MLX5_IB_TUNNELED_OFFLOADS_GENEVE = 1 << 2, 260 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE = 1 << 3, 261 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP = 1 << 4, 262 }; 263 264 struct mlx5_ib_query_device_resp { 265 __u32 comp_mask; 266 __u32 response_length; 267 struct mlx5_ib_tso_caps tso_caps; 268 struct mlx5_ib_rss_caps rss_caps; 269 struct mlx5_ib_cqe_comp_caps cqe_comp_caps; 270 struct mlx5_packet_pacing_caps packet_pacing_caps; 271 __u32 mlx5_ib_support_multi_pkt_send_wqes; 272 __u32 flags; /* Use enum mlx5_ib_query_dev_resp_flags */ 273 struct mlx5_ib_sw_parsing_caps sw_parsing_caps; 274 struct mlx5_ib_striding_rq_caps striding_rq_caps; 275 __u32 tunnel_offloads_caps; /* enum mlx5_ib_tunnel_offloads */ 276 struct mlx5_ib_dci_streams_caps dci_streams_caps; 277 __u16 reserved; 278 }; 279 280 enum mlx5_ib_create_cq_flags { 281 MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD = 1 << 0, 282 MLX5_IB_CREATE_CQ_FLAGS_UAR_PAGE_INDEX = 1 << 1, 283 MLX5_IB_CREATE_CQ_FLAGS_REAL_TIME_TS = 1 << 2, 284 }; 285 286 struct mlx5_ib_create_cq { 287 __aligned_u64 buf_addr; 288 __aligned_u64 db_addr; 289 __u32 cqe_size; 290 __u8 cqe_comp_en; 291 __u8 cqe_comp_res_format; 292 __u16 flags; 293 __u16 uar_page_index; 294 __u16 reserved0; 295 __u32 reserved1; 296 }; 297 298 struct mlx5_ib_create_cq_resp { 299 __u32 cqn; 300 __u32 reserved; 301 }; 302 303 struct mlx5_ib_resize_cq { 304 __aligned_u64 buf_addr; 305 __u16 cqe_size; 306 __u16 reserved0; 307 __u32 reserved1; 308 }; 309 310 struct mlx5_ib_create_srq { 311 __aligned_u64 buf_addr; 312 __aligned_u64 db_addr; 313 __u32 flags; 314 __u32 reserved0; /* explicit padding (optional on i386) */ 315 __u32 uidx; 316 __u32 reserved1; 317 }; 318 319 struct mlx5_ib_create_srq_resp { 320 __u32 srqn; 321 __u32 reserved; 322 }; 323 324 struct mlx5_ib_create_qp_dci_streams { 325 __u8 log_num_concurent; 326 __u8 log_num_errored; 327 }; 328 329 struct mlx5_ib_create_qp { 330 __aligned_u64 buf_addr; 331 __aligned_u64 db_addr; 332 __u32 sq_wqe_count; 333 __u32 rq_wqe_count; 334 __u32 rq_wqe_shift; 335 __u32 flags; 336 __u32 uidx; 337 __u32 bfreg_index; 338 union { 339 __aligned_u64 sq_buf_addr; 340 __aligned_u64 access_key; 341 }; 342 __u32 ece_options; 343 struct mlx5_ib_create_qp_dci_streams dci_streams; 344 __u16 reserved; 345 }; 346 347 /* RX Hash function flags */ 348 enum mlx5_rx_hash_function_flags { 349 MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0, 350 }; 351 352 /* 353 * RX Hash flags, these flags allows to set which incoming packet's field should 354 * participates in RX Hash. Each flag represent certain packet's field, 355 * when the flag is set the field that is represented by the flag will 356 * participate in RX Hash calculation. 357 * Note: *IPV4 and *IPV6 flags can't be enabled together on the same QP 358 * and *TCP and *UDP flags can't be enabled together on the same QP. 359 */ 360 enum mlx5_rx_hash_fields { 361 MLX5_RX_HASH_SRC_IPV4 = 1 << 0, 362 MLX5_RX_HASH_DST_IPV4 = 1 << 1, 363 MLX5_RX_HASH_SRC_IPV6 = 1 << 2, 364 MLX5_RX_HASH_DST_IPV6 = 1 << 3, 365 MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4, 366 MLX5_RX_HASH_DST_PORT_TCP = 1 << 5, 367 MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6, 368 MLX5_RX_HASH_DST_PORT_UDP = 1 << 7, 369 MLX5_RX_HASH_IPSEC_SPI = 1 << 8, 370 /* Save bits for future fields */ 371 MLX5_RX_HASH_INNER = (1UL << 31), 372 }; 373 374 struct mlx5_ib_create_qp_rss { 375 __aligned_u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */ 376 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */ 377 __u8 rx_key_len; /* valid only for Toeplitz */ 378 __u8 reserved[6]; 379 __u8 rx_hash_key[128]; /* valid only for Toeplitz */ 380 __u32 comp_mask; 381 __u32 flags; 382 }; 383 384 enum mlx5_ib_create_qp_resp_mask { 385 MLX5_IB_CREATE_QP_RESP_MASK_TIRN = 1UL << 0, 386 MLX5_IB_CREATE_QP_RESP_MASK_TISN = 1UL << 1, 387 MLX5_IB_CREATE_QP_RESP_MASK_RQN = 1UL << 2, 388 MLX5_IB_CREATE_QP_RESP_MASK_SQN = 1UL << 3, 389 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR = 1UL << 4, 390 }; 391 392 struct mlx5_ib_create_qp_resp { 393 __u32 bfreg_index; 394 __u32 ece_options; 395 __u32 comp_mask; 396 __u32 tirn; 397 __u32 tisn; 398 __u32 rqn; 399 __u32 sqn; 400 __u32 reserved1; 401 __u64 tir_icm_addr; 402 }; 403 404 struct mlx5_ib_alloc_mw { 405 __u32 comp_mask; 406 __u8 num_klms; 407 __u8 reserved1; 408 __u16 reserved2; 409 }; 410 411 enum mlx5_ib_create_wq_mask { 412 MLX5_IB_CREATE_WQ_STRIDING_RQ = (1 << 0), 413 }; 414 415 struct mlx5_ib_create_wq { 416 __aligned_u64 buf_addr; 417 __aligned_u64 db_addr; 418 __u32 rq_wqe_count; 419 __u32 rq_wqe_shift; 420 __u32 user_index; 421 __u32 flags; 422 __u32 comp_mask; 423 __u32 single_stride_log_num_of_bytes; 424 __u32 single_wqe_log_num_of_strides; 425 __u32 two_byte_shift_en; 426 }; 427 428 struct mlx5_ib_create_ah_resp { 429 __u32 response_length; 430 __u8 dmac[ETH_ALEN]; 431 __u8 reserved[6]; 432 }; 433 434 struct mlx5_ib_burst_info { 435 __u32 max_burst_sz; 436 __u16 typical_pkt_sz; 437 __u16 reserved; 438 }; 439 440 struct mlx5_ib_modify_qp { 441 __u32 comp_mask; 442 struct mlx5_ib_burst_info burst_info; 443 __u32 ece_options; 444 }; 445 446 struct mlx5_ib_modify_qp_resp { 447 __u32 response_length; 448 __u32 dctn; 449 __u32 ece_options; 450 __u32 reserved; 451 }; 452 453 struct mlx5_ib_create_wq_resp { 454 __u32 response_length; 455 __u32 reserved; 456 }; 457 458 struct mlx5_ib_create_rwq_ind_tbl_resp { 459 __u32 response_length; 460 __u32 reserved; 461 }; 462 463 struct mlx5_ib_modify_wq { 464 __u32 comp_mask; 465 __u32 reserved; 466 }; 467 468 struct mlx5_ib_clock_info { 469 __u32 sign; 470 __u32 resv; 471 __aligned_u64 nsec; 472 __aligned_u64 cycles; 473 __aligned_u64 frac; 474 __u32 mult; 475 __u32 shift; 476 __aligned_u64 mask; 477 __aligned_u64 overflow_period; 478 }; 479 480 enum mlx5_ib_mmap_cmd { 481 MLX5_IB_MMAP_REGULAR_PAGE = 0, 482 MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1, 483 MLX5_IB_MMAP_WC_PAGE = 2, 484 MLX5_IB_MMAP_NC_PAGE = 3, 485 /* 5 is chosen in order to be compatible with old versions of libmlx5 */ 486 MLX5_IB_MMAP_CORE_CLOCK = 5, 487 MLX5_IB_MMAP_ALLOC_WC = 6, 488 MLX5_IB_MMAP_CLOCK_INFO = 7, 489 MLX5_IB_MMAP_DEVICE_MEM = 8, 490 }; 491 492 enum { 493 MLX5_IB_CLOCK_INFO_KERNEL_UPDATING = 1, 494 }; 495 496 /* Bit indexes for the mlx5_alloc_ucontext_resp.clock_info_versions bitmap */ 497 enum { 498 MLX5_IB_CLOCK_INFO_V1 = 0, 499 }; 500 501 struct mlx5_ib_flow_counters_desc { 502 __u32 description; 503 __u32 index; 504 }; 505 506 struct mlx5_ib_flow_counters_data { 507 RDMA_UAPI_PTR(struct mlx5_ib_flow_counters_desc *, counters_data); 508 __u32 ncounters; 509 __u32 reserved; 510 }; 511 512 struct mlx5_ib_create_flow { 513 __u32 ncounters_data; 514 __u32 reserved; 515 /* 516 * Following are counters data based on ncounters_data, each 517 * entry in the data[] should match a corresponding counter object 518 * that was pointed by a counters spec upon the flow creation 519 */ 520 struct mlx5_ib_flow_counters_data data[]; 521 }; 522 523 #endif /* MLX5_ABI_USER_H */ 524