1 /* 2 * Copyright 2013 Red Hat 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 #ifndef VIRTGPU_DRM_H 25 #define VIRTGPU_DRM_H 26 27 #include "drm.h" 28 29 /* Please note that modifications to all structs defined here are 30 * subject to backwards-compatibility constraints. 31 * 32 * Do not use pointers, use __u64 instead for 32 bit / 64 bit user/kernel 33 * compatibility Keep fields aligned to their size 34 */ 35 36 #define DRM_VIRTGPU_MAP 0x01 37 #define DRM_VIRTGPU_EXECBUFFER 0x02 38 #define DRM_VIRTGPU_GETPARAM 0x03 39 #define DRM_VIRTGPU_RESOURCE_CREATE 0x04 40 #define DRM_VIRTGPU_RESOURCE_INFO 0x05 41 #define DRM_VIRTGPU_TRANSFER_FROM_HOST 0x06 42 #define DRM_VIRTGPU_TRANSFER_TO_HOST 0x07 43 #define DRM_VIRTGPU_WAIT 0x08 44 #define DRM_VIRTGPU_GET_CAPS 0x09 45 46 struct drm_virtgpu_map { 47 __u64 offset; /* use for mmap system call */ 48 __u32 handle; 49 __u32 pad; 50 }; 51 52 struct drm_virtgpu_execbuffer { 53 __u32 flags; /* for future use */ 54 __u32 size; 55 __u64 command; /* void* */ 56 __u64 bo_handles; 57 __u32 num_bo_handles; 58 __u32 pad; 59 }; 60 61 #define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */ 62 63 struct drm_virtgpu_getparam { 64 __u64 param; 65 __u64 value; 66 }; 67 68 /* NO_BO flags? NO resource flag? */ 69 /* resource flag for y_0_top */ 70 struct drm_virtgpu_resource_create { 71 __u32 target; 72 __u32 format; 73 __u32 bind; 74 __u32 width; 75 __u32 height; 76 __u32 depth; 77 __u32 array_size; 78 __u32 last_level; 79 __u32 nr_samples; 80 __u32 flags; 81 __u32 bo_handle; /* if this is set - recreate a new resource attached to this bo ? */ 82 __u32 res_handle; /* returned by kernel */ 83 __u32 size; /* validate transfer in the host */ 84 __u32 stride; /* validate transfer in the host */ 85 }; 86 87 struct drm_virtgpu_resource_info { 88 __u32 bo_handle; 89 __u32 res_handle; 90 __u32 size; 91 __u32 stride; 92 }; 93 94 struct drm_virtgpu_3d_box { 95 __u32 x; 96 __u32 y; 97 __u32 z; 98 __u32 w; 99 __u32 h; 100 __u32 d; 101 }; 102 103 struct drm_virtgpu_3d_transfer_to_host { 104 __u32 bo_handle; 105 struct drm_virtgpu_3d_box box; 106 __u32 level; 107 __u32 offset; 108 }; 109 110 struct drm_virtgpu_3d_transfer_from_host { 111 __u32 bo_handle; 112 struct drm_virtgpu_3d_box box; 113 __u32 level; 114 __u32 offset; 115 }; 116 117 #define VIRTGPU_WAIT_NOWAIT 1 /* like it */ 118 struct drm_virtgpu_3d_wait { 119 __u32 handle; /* 0 is an invalid handle */ 120 __u32 flags; 121 }; 122 123 struct drm_virtgpu_get_caps { 124 __u32 cap_set_id; 125 __u32 cap_set_ver; 126 __u64 addr; 127 __u32 size; 128 __u32 pad; 129 }; 130 131 #define DRM_IOCTL_VIRTGPU_MAP \ 132 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map) 133 134 #define DRM_IOCTL_VIRTGPU_EXECBUFFER \ 135 DRM_IOW(DRM_COMMAND_BASE + DRM_VIRTGPU_EXECBUFFER,\ 136 struct drm_virtgpu_execbuffer) 137 138 #define DRM_IOCTL_VIRTGPU_GETPARAM \ 139 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GETPARAM,\ 140 struct drm_virtgpu_getparam) 141 142 #define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE \ 143 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE, \ 144 struct drm_virtgpu_resource_create) 145 146 #define DRM_IOCTL_VIRTGPU_RESOURCE_INFO \ 147 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_INFO, \ 148 struct drm_virtgpu_resource_info) 149 150 #define DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST \ 151 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_FROM_HOST, \ 152 struct drm_virtgpu_3d_transfer_from_host) 153 154 #define DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST \ 155 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_TO_HOST, \ 156 struct drm_virtgpu_3d_transfer_to_host) 157 158 #define DRM_IOCTL_VIRTGPU_WAIT \ 159 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_WAIT, \ 160 struct drm_virtgpu_3d_wait) 161 162 #define DRM_IOCTL_VIRTGPU_GET_CAPS \ 163 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GET_CAPS, \ 164 struct drm_virtgpu_get_caps) 165 166 #endif 167