1 /* 2 * Copyright © 2014-2015 Broadcom 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 #ifndef _UAPI_VC4_DRM_H_ 25 #define _UAPI_VC4_DRM_H_ 26 27 #include "drm.h" 28 29 #if defined(__cplusplus) 30 extern "C" { 31 #endif 32 33 #define DRM_VC4_SUBMIT_CL 0x00 34 #define DRM_VC4_WAIT_SEQNO 0x01 35 #define DRM_VC4_WAIT_BO 0x02 36 #define DRM_VC4_CREATE_BO 0x03 37 #define DRM_VC4_MMAP_BO 0x04 38 #define DRM_VC4_CREATE_SHADER_BO 0x05 39 #define DRM_VC4_GET_HANG_STATE 0x06 40 #define DRM_VC4_GET_PARAM 0x07 41 42 #define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl) 43 #define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno) 44 #define DRM_IOCTL_VC4_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo) 45 #define DRM_IOCTL_VC4_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo) 46 #define DRM_IOCTL_VC4_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo) 47 #define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo) 48 #define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state) 49 #define DRM_IOCTL_VC4_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_PARAM, struct drm_vc4_get_param) 50 51 struct drm_vc4_submit_rcl_surface { 52 __u32 hindex; /* Handle index, or ~0 if not present. */ 53 __u32 offset; /* Offset to start of buffer. */ 54 /* 55 * Bits for either render config (color_write) or load/store packet. 56 * Bits should all be 0 for MSAA load/stores. 57 */ 58 __u16 bits; 59 60 #define VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES (1 << 0) 61 __u16 flags; 62 }; 63 64 /** 65 * struct drm_vc4_submit_cl - ioctl argument for submitting commands to the 3D 66 * engine. 67 * 68 * Drivers typically use GPU BOs to store batchbuffers / command lists and 69 * their associated state. However, because the VC4 lacks an MMU, we have to 70 * do validation of memory accesses by the GPU commands. If we were to store 71 * our commands in BOs, we'd need to do uncached readback from them to do the 72 * validation process, which is too expensive. Instead, userspace accumulates 73 * commands and associated state in plain memory, then the kernel copies the 74 * data to its own address space, and then validates and stores it in a GPU 75 * BO. 76 */ 77 struct drm_vc4_submit_cl { 78 /* Pointer to the binner command list. 79 * 80 * This is the first set of commands executed, which runs the 81 * coordinate shader to determine where primitives land on the screen, 82 * then writes out the state updates and draw calls necessary per tile 83 * to the tile allocation BO. 84 */ 85 __u64 bin_cl; 86 87 /* Pointer to the shader records. 88 * 89 * Shader records are the structures read by the hardware that contain 90 * pointers to uniforms, shaders, and vertex attributes. The 91 * reference to the shader record has enough information to determine 92 * how many pointers are necessary (fixed number for shaders/uniforms, 93 * and an attribute count), so those BO indices into bo_handles are 94 * just stored as __u32s before each shader record passed in. 95 */ 96 __u64 shader_rec; 97 98 /* Pointer to uniform data and texture handles for the textures 99 * referenced by the shader. 100 * 101 * For each shader state record, there is a set of uniform data in the 102 * order referenced by the record (FS, VS, then CS). Each set of 103 * uniform data has a __u32 index into bo_handles per texture 104 * sample operation, in the order the QPU_W_TMUn_S writes appear in 105 * the program. Following the texture BO handle indices is the actual 106 * uniform data. 107 * 108 * The individual uniform state blocks don't have sizes passed in, 109 * because the kernel has to determine the sizes anyway during shader 110 * code validation. 111 */ 112 __u64 uniforms; 113 __u64 bo_handles; 114 115 /* Size in bytes of the binner command list. */ 116 __u32 bin_cl_size; 117 /* Size in bytes of the set of shader records. */ 118 __u32 shader_rec_size; 119 /* Number of shader records. 120 * 121 * This could just be computed from the contents of shader_records and 122 * the address bits of references to them from the bin CL, but it 123 * keeps the kernel from having to resize some allocations it makes. 124 */ 125 __u32 shader_rec_count; 126 /* Size in bytes of the uniform state. */ 127 __u32 uniforms_size; 128 129 /* Number of BO handles passed in (size is that times 4). */ 130 __u32 bo_handle_count; 131 132 /* RCL setup: */ 133 __u16 width; 134 __u16 height; 135 __u8 min_x_tile; 136 __u8 min_y_tile; 137 __u8 max_x_tile; 138 __u8 max_y_tile; 139 struct drm_vc4_submit_rcl_surface color_read; 140 struct drm_vc4_submit_rcl_surface color_write; 141 struct drm_vc4_submit_rcl_surface zs_read; 142 struct drm_vc4_submit_rcl_surface zs_write; 143 struct drm_vc4_submit_rcl_surface msaa_color_write; 144 struct drm_vc4_submit_rcl_surface msaa_zs_write; 145 __u32 clear_color[2]; 146 __u32 clear_z; 147 __u8 clear_s; 148 149 __u32 pad:24; 150 151 #define VC4_SUBMIT_CL_USE_CLEAR_COLOR (1 << 0) 152 __u32 flags; 153 154 /* Returned value of the seqno of this render job (for the 155 * wait ioctl). 156 */ 157 __u64 seqno; 158 }; 159 160 /** 161 * struct drm_vc4_wait_seqno - ioctl argument for waiting for 162 * DRM_VC4_SUBMIT_CL completion using its returned seqno. 163 * 164 * timeout_ns is the timeout in nanoseconds, where "0" means "don't 165 * block, just return the status." 166 */ 167 struct drm_vc4_wait_seqno { 168 __u64 seqno; 169 __u64 timeout_ns; 170 }; 171 172 /** 173 * struct drm_vc4_wait_bo - ioctl argument for waiting for 174 * completion of the last DRM_VC4_SUBMIT_CL on a BO. 175 * 176 * This is useful for cases where multiple processes might be 177 * rendering to a BO and you want to wait for all rendering to be 178 * completed. 179 */ 180 struct drm_vc4_wait_bo { 181 __u32 handle; 182 __u32 pad; 183 __u64 timeout_ns; 184 }; 185 186 /** 187 * struct drm_vc4_create_bo - ioctl argument for creating VC4 BOs. 188 * 189 * There are currently no values for the flags argument, but it may be 190 * used in a future extension. 191 */ 192 struct drm_vc4_create_bo { 193 __u32 size; 194 __u32 flags; 195 /** Returned GEM handle for the BO. */ 196 __u32 handle; 197 __u32 pad; 198 }; 199 200 /** 201 * struct drm_vc4_mmap_bo - ioctl argument for mapping VC4 BOs. 202 * 203 * This doesn't actually perform an mmap. Instead, it returns the 204 * offset you need to use in an mmap on the DRM device node. This 205 * means that tools like valgrind end up knowing about the mapped 206 * memory. 207 * 208 * There are currently no values for the flags argument, but it may be 209 * used in a future extension. 210 */ 211 struct drm_vc4_mmap_bo { 212 /** Handle for the object being mapped. */ 213 __u32 handle; 214 __u32 flags; 215 /** offset into the drm node to use for subsequent mmap call. */ 216 __u64 offset; 217 }; 218 219 /** 220 * struct drm_vc4_create_shader_bo - ioctl argument for creating VC4 221 * shader BOs. 222 * 223 * Since allowing a shader to be overwritten while it's also being 224 * executed from would allow privlege escalation, shaders must be 225 * created using this ioctl, and they can't be mmapped later. 226 */ 227 struct drm_vc4_create_shader_bo { 228 /* Size of the data argument. */ 229 __u32 size; 230 /* Flags, currently must be 0. */ 231 __u32 flags; 232 233 /* Pointer to the data. */ 234 __u64 data; 235 236 /** Returned GEM handle for the BO. */ 237 __u32 handle; 238 /* Pad, must be 0. */ 239 __u32 pad; 240 }; 241 242 struct drm_vc4_get_hang_state_bo { 243 __u32 handle; 244 __u32 paddr; 245 __u32 size; 246 __u32 pad; 247 }; 248 249 /** 250 * struct drm_vc4_hang_state - ioctl argument for collecting state 251 * from a GPU hang for analysis. 252 */ 253 struct drm_vc4_get_hang_state { 254 /** Pointer to array of struct drm_vc4_get_hang_state_bo. */ 255 __u64 bo; 256 /** 257 * On input, the size of the bo array. Output is the number 258 * of bos to be returned. 259 */ 260 __u32 bo_count; 261 262 __u32 start_bin, start_render; 263 264 __u32 ct0ca, ct0ea; 265 __u32 ct1ca, ct1ea; 266 __u32 ct0cs, ct1cs; 267 __u32 ct0ra0, ct1ra0; 268 269 __u32 bpca, bpcs; 270 __u32 bpoa, bpos; 271 272 __u32 vpmbase; 273 274 __u32 dbge; 275 __u32 fdbgo; 276 __u32 fdbgb; 277 __u32 fdbgr; 278 __u32 fdbgs; 279 __u32 errstat; 280 281 /* Pad that we may save more registers into in the future. */ 282 __u32 pad[16]; 283 }; 284 285 #define DRM_VC4_PARAM_V3D_IDENT0 0 286 #define DRM_VC4_PARAM_V3D_IDENT1 1 287 #define DRM_VC4_PARAM_V3D_IDENT2 2 288 #define DRM_VC4_PARAM_SUPPORTS_BRANCHES 3 289 #define DRM_VC4_PARAM_SUPPORTS_ETC1 4 290 #define DRM_VC4_PARAM_SUPPORTS_THREADED_FS 5 291 292 struct drm_vc4_get_param { 293 __u32 param; 294 __u32 pad; 295 __u64 value; 296 }; 297 298 #if defined(__cplusplus) 299 } 300 #endif 301 302 #endif /* _UAPI_VC4_DRM_H_ */ 303