1 /* 2 * Copyright © 2014-2015 Broadcom 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 #ifndef _UAPI_VC4_DRM_H_ 25 #define _UAPI_VC4_DRM_H_ 26 27 #include "drm.h" 28 29 #if defined(__cplusplus) 30 extern "C" { 31 #endif 32 33 #define DRM_VC4_SUBMIT_CL 0x00 34 #define DRM_VC4_WAIT_SEQNO 0x01 35 #define DRM_VC4_WAIT_BO 0x02 36 #define DRM_VC4_CREATE_BO 0x03 37 #define DRM_VC4_MMAP_BO 0x04 38 #define DRM_VC4_CREATE_SHADER_BO 0x05 39 #define DRM_VC4_GET_HANG_STATE 0x06 40 #define DRM_VC4_GET_PARAM 0x07 41 #define DRM_VC4_SET_TILING 0x08 42 #define DRM_VC4_GET_TILING 0x09 43 44 #define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl) 45 #define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno) 46 #define DRM_IOCTL_VC4_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo) 47 #define DRM_IOCTL_VC4_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo) 48 #define DRM_IOCTL_VC4_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo) 49 #define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo) 50 #define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state) 51 #define DRM_IOCTL_VC4_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_PARAM, struct drm_vc4_get_param) 52 #define DRM_IOCTL_VC4_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SET_TILING, struct drm_vc4_set_tiling) 53 #define DRM_IOCTL_VC4_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_TILING, struct drm_vc4_get_tiling) 54 55 struct drm_vc4_submit_rcl_surface { 56 __u32 hindex; /* Handle index, or ~0 if not present. */ 57 __u32 offset; /* Offset to start of buffer. */ 58 /* 59 * Bits for either render config (color_write) or load/store packet. 60 * Bits should all be 0 for MSAA load/stores. 61 */ 62 __u16 bits; 63 64 #define VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES (1 << 0) 65 __u16 flags; 66 }; 67 68 /** 69 * struct drm_vc4_submit_cl - ioctl argument for submitting commands to the 3D 70 * engine. 71 * 72 * Drivers typically use GPU BOs to store batchbuffers / command lists and 73 * their associated state. However, because the VC4 lacks an MMU, we have to 74 * do validation of memory accesses by the GPU commands. If we were to store 75 * our commands in BOs, we'd need to do uncached readback from them to do the 76 * validation process, which is too expensive. Instead, userspace accumulates 77 * commands and associated state in plain memory, then the kernel copies the 78 * data to its own address space, and then validates and stores it in a GPU 79 * BO. 80 */ 81 struct drm_vc4_submit_cl { 82 /* Pointer to the binner command list. 83 * 84 * This is the first set of commands executed, which runs the 85 * coordinate shader to determine where primitives land on the screen, 86 * then writes out the state updates and draw calls necessary per tile 87 * to the tile allocation BO. 88 */ 89 __u64 bin_cl; 90 91 /* Pointer to the shader records. 92 * 93 * Shader records are the structures read by the hardware that contain 94 * pointers to uniforms, shaders, and vertex attributes. The 95 * reference to the shader record has enough information to determine 96 * how many pointers are necessary (fixed number for shaders/uniforms, 97 * and an attribute count), so those BO indices into bo_handles are 98 * just stored as __u32s before each shader record passed in. 99 */ 100 __u64 shader_rec; 101 102 /* Pointer to uniform data and texture handles for the textures 103 * referenced by the shader. 104 * 105 * For each shader state record, there is a set of uniform data in the 106 * order referenced by the record (FS, VS, then CS). Each set of 107 * uniform data has a __u32 index into bo_handles per texture 108 * sample operation, in the order the QPU_W_TMUn_S writes appear in 109 * the program. Following the texture BO handle indices is the actual 110 * uniform data. 111 * 112 * The individual uniform state blocks don't have sizes passed in, 113 * because the kernel has to determine the sizes anyway during shader 114 * code validation. 115 */ 116 __u64 uniforms; 117 __u64 bo_handles; 118 119 /* Size in bytes of the binner command list. */ 120 __u32 bin_cl_size; 121 /* Size in bytes of the set of shader records. */ 122 __u32 shader_rec_size; 123 /* Number of shader records. 124 * 125 * This could just be computed from the contents of shader_records and 126 * the address bits of references to them from the bin CL, but it 127 * keeps the kernel from having to resize some allocations it makes. 128 */ 129 __u32 shader_rec_count; 130 /* Size in bytes of the uniform state. */ 131 __u32 uniforms_size; 132 133 /* Number of BO handles passed in (size is that times 4). */ 134 __u32 bo_handle_count; 135 136 /* RCL setup: */ 137 __u16 width; 138 __u16 height; 139 __u8 min_x_tile; 140 __u8 min_y_tile; 141 __u8 max_x_tile; 142 __u8 max_y_tile; 143 struct drm_vc4_submit_rcl_surface color_read; 144 struct drm_vc4_submit_rcl_surface color_write; 145 struct drm_vc4_submit_rcl_surface zs_read; 146 struct drm_vc4_submit_rcl_surface zs_write; 147 struct drm_vc4_submit_rcl_surface msaa_color_write; 148 struct drm_vc4_submit_rcl_surface msaa_zs_write; 149 __u32 clear_color[2]; 150 __u32 clear_z; 151 __u8 clear_s; 152 153 __u32 pad:24; 154 155 #define VC4_SUBMIT_CL_USE_CLEAR_COLOR (1 << 0) 156 __u32 flags; 157 158 /* Returned value of the seqno of this render job (for the 159 * wait ioctl). 160 */ 161 __u64 seqno; 162 }; 163 164 /** 165 * struct drm_vc4_wait_seqno - ioctl argument for waiting for 166 * DRM_VC4_SUBMIT_CL completion using its returned seqno. 167 * 168 * timeout_ns is the timeout in nanoseconds, where "0" means "don't 169 * block, just return the status." 170 */ 171 struct drm_vc4_wait_seqno { 172 __u64 seqno; 173 __u64 timeout_ns; 174 }; 175 176 /** 177 * struct drm_vc4_wait_bo - ioctl argument for waiting for 178 * completion of the last DRM_VC4_SUBMIT_CL on a BO. 179 * 180 * This is useful for cases where multiple processes might be 181 * rendering to a BO and you want to wait for all rendering to be 182 * completed. 183 */ 184 struct drm_vc4_wait_bo { 185 __u32 handle; 186 __u32 pad; 187 __u64 timeout_ns; 188 }; 189 190 /** 191 * struct drm_vc4_create_bo - ioctl argument for creating VC4 BOs. 192 * 193 * There are currently no values for the flags argument, but it may be 194 * used in a future extension. 195 */ 196 struct drm_vc4_create_bo { 197 __u32 size; 198 __u32 flags; 199 /** Returned GEM handle for the BO. */ 200 __u32 handle; 201 __u32 pad; 202 }; 203 204 /** 205 * struct drm_vc4_mmap_bo - ioctl argument for mapping VC4 BOs. 206 * 207 * This doesn't actually perform an mmap. Instead, it returns the 208 * offset you need to use in an mmap on the DRM device node. This 209 * means that tools like valgrind end up knowing about the mapped 210 * memory. 211 * 212 * There are currently no values for the flags argument, but it may be 213 * used in a future extension. 214 */ 215 struct drm_vc4_mmap_bo { 216 /** Handle for the object being mapped. */ 217 __u32 handle; 218 __u32 flags; 219 /** offset into the drm node to use for subsequent mmap call. */ 220 __u64 offset; 221 }; 222 223 /** 224 * struct drm_vc4_create_shader_bo - ioctl argument for creating VC4 225 * shader BOs. 226 * 227 * Since allowing a shader to be overwritten while it's also being 228 * executed from would allow privlege escalation, shaders must be 229 * created using this ioctl, and they can't be mmapped later. 230 */ 231 struct drm_vc4_create_shader_bo { 232 /* Size of the data argument. */ 233 __u32 size; 234 /* Flags, currently must be 0. */ 235 __u32 flags; 236 237 /* Pointer to the data. */ 238 __u64 data; 239 240 /** Returned GEM handle for the BO. */ 241 __u32 handle; 242 /* Pad, must be 0. */ 243 __u32 pad; 244 }; 245 246 struct drm_vc4_get_hang_state_bo { 247 __u32 handle; 248 __u32 paddr; 249 __u32 size; 250 __u32 pad; 251 }; 252 253 /** 254 * struct drm_vc4_hang_state - ioctl argument for collecting state 255 * from a GPU hang for analysis. 256 */ 257 struct drm_vc4_get_hang_state { 258 /** Pointer to array of struct drm_vc4_get_hang_state_bo. */ 259 __u64 bo; 260 /** 261 * On input, the size of the bo array. Output is the number 262 * of bos to be returned. 263 */ 264 __u32 bo_count; 265 266 __u32 start_bin, start_render; 267 268 __u32 ct0ca, ct0ea; 269 __u32 ct1ca, ct1ea; 270 __u32 ct0cs, ct1cs; 271 __u32 ct0ra0, ct1ra0; 272 273 __u32 bpca, bpcs; 274 __u32 bpoa, bpos; 275 276 __u32 vpmbase; 277 278 __u32 dbge; 279 __u32 fdbgo; 280 __u32 fdbgb; 281 __u32 fdbgr; 282 __u32 fdbgs; 283 __u32 errstat; 284 285 /* Pad that we may save more registers into in the future. */ 286 __u32 pad[16]; 287 }; 288 289 #define DRM_VC4_PARAM_V3D_IDENT0 0 290 #define DRM_VC4_PARAM_V3D_IDENT1 1 291 #define DRM_VC4_PARAM_V3D_IDENT2 2 292 #define DRM_VC4_PARAM_SUPPORTS_BRANCHES 3 293 #define DRM_VC4_PARAM_SUPPORTS_ETC1 4 294 #define DRM_VC4_PARAM_SUPPORTS_THREADED_FS 5 295 296 struct drm_vc4_get_param { 297 __u32 param; 298 __u32 pad; 299 __u64 value; 300 }; 301 302 struct drm_vc4_get_tiling { 303 __u32 handle; 304 __u32 flags; 305 __u64 modifier; 306 }; 307 308 struct drm_vc4_set_tiling { 309 __u32 handle; 310 __u32 flags; 311 __u64 modifier; 312 }; 313 314 #if defined(__cplusplus) 315 } 316 #endif 317 318 #endif /* _UAPI_VC4_DRM_H_ */ 319