xref: /openbmc/linux/include/uapi/drm/v3d_drm.h (revision 9b93eb47)
1 /*
2  * Copyright © 2014-2018 Broadcom
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  */
23 
24 #ifndef _V3D_DRM_H_
25 #define _V3D_DRM_H_
26 
27 #include "drm.h"
28 
29 #if defined(__cplusplus)
30 extern "C" {
31 #endif
32 
33 #define DRM_V3D_SUBMIT_CL                         0x00
34 #define DRM_V3D_WAIT_BO                           0x01
35 #define DRM_V3D_CREATE_BO                         0x02
36 #define DRM_V3D_MMAP_BO                           0x03
37 #define DRM_V3D_GET_PARAM                         0x04
38 #define DRM_V3D_GET_BO_OFFSET                     0x05
39 #define DRM_V3D_SUBMIT_TFU                        0x06
40 #define DRM_V3D_SUBMIT_CSD                        0x07
41 
42 #define DRM_IOCTL_V3D_SUBMIT_CL           DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl)
43 #define DRM_IOCTL_V3D_WAIT_BO             DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo)
44 #define DRM_IOCTL_V3D_CREATE_BO           DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_CREATE_BO, struct drm_v3d_create_bo)
45 #define DRM_IOCTL_V3D_MMAP_BO             DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_MMAP_BO, struct drm_v3d_mmap_bo)
46 #define DRM_IOCTL_V3D_GET_PARAM           DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_PARAM, struct drm_v3d_get_param)
47 #define DRM_IOCTL_V3D_GET_BO_OFFSET       DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset)
48 #define DRM_IOCTL_V3D_SUBMIT_TFU          DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_TFU, struct drm_v3d_submit_tfu)
49 #define DRM_IOCTL_V3D_SUBMIT_CSD          DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CSD, struct drm_v3d_submit_csd)
50 
51 /**
52  * struct drm_v3d_submit_cl - ioctl argument for submitting commands to the 3D
53  * engine.
54  *
55  * This asks the kernel to have the GPU execute an optional binner
56  * command list, and a render command list.
57  *
58  * The L1T, slice, L2C, L2T, and GCA caches will be flushed before
59  * each CL executes.  The VCD cache should be flushed (if necessary)
60  * by the submitted CLs.  The TLB writes are guaranteed to have been
61  * flushed by the time the render done IRQ happens, which is the
62  * trigger for out_sync.  Any dirtying of cachelines by the job (only
63  * possible using TMU writes) must be flushed by the caller using the
64  * CL's cache flush commands.
65  */
66 struct drm_v3d_submit_cl {
67 	/* Pointer to the binner command list.
68 	 *
69 	 * This is the first set of commands executed, which runs the
70 	 * coordinate shader to determine where primitives land on the screen,
71 	 * then writes out the state updates and draw calls necessary per tile
72 	 * to the tile allocation BO.
73 	 *
74 	 * This BCL will block on any previous BCL submitted on the
75 	 * same FD, but not on any RCL or BCLs submitted by other
76 	 * clients -- that is left up to the submitter to control
77 	 * using in_sync_bcl if necessary.
78 	 */
79 	__u32 bcl_start;
80 
81 	/** End address of the BCL (first byte after the BCL) */
82 	__u32 bcl_end;
83 
84 	/* Offset of the render command list.
85 	 *
86 	 * This is the second set of commands executed, which will either
87 	 * execute the tiles that have been set up by the BCL, or a fixed set
88 	 * of tiles (in the case of RCL-only blits).
89 	 *
90 	 * This RCL will block on this submit's BCL, and any previous
91 	 * RCL submitted on the same FD, but not on any RCL or BCLs
92 	 * submitted by other clients -- that is left up to the
93 	 * submitter to control using in_sync_rcl if necessary.
94 	 */
95 	__u32 rcl_start;
96 
97 	/** End address of the RCL (first byte after the RCL) */
98 	__u32 rcl_end;
99 
100 	/** An optional sync object to wait on before starting the BCL. */
101 	__u32 in_sync_bcl;
102 	/** An optional sync object to wait on before starting the RCL. */
103 	__u32 in_sync_rcl;
104 	/** An optional sync object to place the completion fence in. */
105 	__u32 out_sync;
106 
107 	/* Offset of the tile alloc memory
108 	 *
109 	 * This is optional on V3D 3.3 (where the CL can set the value) but
110 	 * required on V3D 4.1.
111 	 */
112 	__u32 qma;
113 
114 	/** Size of the tile alloc memory. */
115 	__u32 qms;
116 
117 	/** Offset of the tile state data array. */
118 	__u32 qts;
119 
120 	/* Pointer to a u32 array of the BOs that are referenced by the job.
121 	 */
122 	__u64 bo_handles;
123 
124 	/* Number of BO handles passed in (size is that times 4). */
125 	__u32 bo_handle_count;
126 
127 	/* Pad, must be zero-filled. */
128 	__u32 pad;
129 };
130 
131 /**
132  * struct drm_v3d_wait_bo - ioctl argument for waiting for
133  * completion of the last DRM_V3D_SUBMIT_CL on a BO.
134  *
135  * This is useful for cases where multiple processes might be
136  * rendering to a BO and you want to wait for all rendering to be
137  * completed.
138  */
139 struct drm_v3d_wait_bo {
140 	__u32 handle;
141 	__u32 pad;
142 	__u64 timeout_ns;
143 };
144 
145 /**
146  * struct drm_v3d_create_bo - ioctl argument for creating V3D BOs.
147  *
148  * There are currently no values for the flags argument, but it may be
149  * used in a future extension.
150  */
151 struct drm_v3d_create_bo {
152 	__u32 size;
153 	__u32 flags;
154 	/** Returned GEM handle for the BO. */
155 	__u32 handle;
156 	/**
157 	 * Returned offset for the BO in the V3D address space.  This offset
158 	 * is private to the DRM fd and is valid for the lifetime of the GEM
159 	 * handle.
160 	 *
161 	 * This offset value will always be nonzero, since various HW
162 	 * units treat 0 specially.
163 	 */
164 	__u32 offset;
165 };
166 
167 /**
168  * struct drm_v3d_mmap_bo - ioctl argument for mapping V3D BOs.
169  *
170  * This doesn't actually perform an mmap.  Instead, it returns the
171  * offset you need to use in an mmap on the DRM device node.  This
172  * means that tools like valgrind end up knowing about the mapped
173  * memory.
174  *
175  * There are currently no values for the flags argument, but it may be
176  * used in a future extension.
177  */
178 struct drm_v3d_mmap_bo {
179 	/** Handle for the object being mapped. */
180 	__u32 handle;
181 	__u32 flags;
182 	/** offset into the drm node to use for subsequent mmap call. */
183 	__u64 offset;
184 };
185 
186 enum drm_v3d_param {
187 	DRM_V3D_PARAM_V3D_UIFCFG,
188 	DRM_V3D_PARAM_V3D_HUB_IDENT1,
189 	DRM_V3D_PARAM_V3D_HUB_IDENT2,
190 	DRM_V3D_PARAM_V3D_HUB_IDENT3,
191 	DRM_V3D_PARAM_V3D_CORE0_IDENT0,
192 	DRM_V3D_PARAM_V3D_CORE0_IDENT1,
193 	DRM_V3D_PARAM_V3D_CORE0_IDENT2,
194 	DRM_V3D_PARAM_SUPPORTS_TFU,
195 	DRM_V3D_PARAM_SUPPORTS_CSD,
196 };
197 
198 struct drm_v3d_get_param {
199 	__u32 param;
200 	__u32 pad;
201 	__u64 value;
202 };
203 
204 /**
205  * Returns the offset for the BO in the V3D address space for this DRM fd.
206  * This is the same value returned by drm_v3d_create_bo, if that was called
207  * from this DRM fd.
208  */
209 struct drm_v3d_get_bo_offset {
210 	__u32 handle;
211 	__u32 offset;
212 };
213 
214 struct drm_v3d_submit_tfu {
215 	__u32 icfg;
216 	__u32 iia;
217 	__u32 iis;
218 	__u32 ica;
219 	__u32 iua;
220 	__u32 ioa;
221 	__u32 ios;
222 	__u32 coef[4];
223 	/* First handle is the output BO, following are other inputs.
224 	 * 0 for unused.
225 	 */
226 	__u32 bo_handles[4];
227 	/* sync object to block on before running the TFU job.  Each TFU
228 	 * job will execute in the order submitted to its FD.  Synchronization
229 	 * against rendering jobs requires using sync objects.
230 	 */
231 	__u32 in_sync;
232 	/* Sync object to signal when the TFU job is done. */
233 	__u32 out_sync;
234 };
235 
236 /* Submits a compute shader for dispatch.  This job will block on any
237  * previous compute shaders submitted on this fd, and any other
238  * synchronization must be performed with in_sync/out_sync.
239  */
240 struct drm_v3d_submit_csd {
241 	__u32 cfg[7];
242 	__u32 coef[4];
243 
244 	/* Pointer to a u32 array of the BOs that are referenced by the job.
245 	 */
246 	__u64 bo_handles;
247 
248 	/* Number of BO handles passed in (size is that times 4). */
249 	__u32 bo_handle_count;
250 
251 	/* sync object to block on before running the CSD job.  Each
252 	 * CSD job will execute in the order submitted to its FD.
253 	 * Synchronization against rendering/TFU jobs or CSD from
254 	 * other fds requires using sync objects.
255 	 */
256 	__u32 in_sync;
257 	/* Sync object to signal when the CSD job is done. */
258 	__u32 out_sync;
259 };
260 
261 #if defined(__cplusplus)
262 }
263 #endif
264 
265 #endif /* _V3D_DRM_H_ */
266