1718dceddSDavid Howells /* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*- 2718dceddSDavid Howells * 3718dceddSDavid Howells * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4718dceddSDavid Howells * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5718dceddSDavid Howells * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 6718dceddSDavid Howells * All rights reserved. 7718dceddSDavid Howells * 8718dceddSDavid Howells * Permission is hereby granted, free of charge, to any person obtaining a 9718dceddSDavid Howells * copy of this software and associated documentation files (the "Software"), 10718dceddSDavid Howells * to deal in the Software without restriction, including without limitation 11718dceddSDavid Howells * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12718dceddSDavid Howells * and/or sell copies of the Software, and to permit persons to whom the 13718dceddSDavid Howells * Software is furnished to do so, subject to the following conditions: 14718dceddSDavid Howells * 15718dceddSDavid Howells * The above copyright notice and this permission notice (including the next 16718dceddSDavid Howells * paragraph) shall be included in all copies or substantial portions of the 17718dceddSDavid Howells * Software. 18718dceddSDavid Howells * 19718dceddSDavid Howells * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20718dceddSDavid Howells * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21718dceddSDavid Howells * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22718dceddSDavid Howells * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 23718dceddSDavid Howells * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24718dceddSDavid Howells * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 25718dceddSDavid Howells * DEALINGS IN THE SOFTWARE. 26718dceddSDavid Howells * 27718dceddSDavid Howells * Authors: 28718dceddSDavid Howells * Kevin E. Martin <martin@valinux.com> 29718dceddSDavid Howells * Gareth Hughes <gareth@valinux.com> 30718dceddSDavid Howells * Keith Whitwell <keith@tungstengraphics.com> 31718dceddSDavid Howells */ 32718dceddSDavid Howells 33718dceddSDavid Howells #ifndef __RADEON_DRM_H__ 34718dceddSDavid Howells #define __RADEON_DRM_H__ 35718dceddSDavid Howells 36718dceddSDavid Howells #include <drm/drm.h> 37718dceddSDavid Howells 38718dceddSDavid Howells /* WARNING: If you change any of these defines, make sure to change the 39718dceddSDavid Howells * defines in the X server file (radeon_sarea.h) 40718dceddSDavid Howells */ 41718dceddSDavid Howells #ifndef __RADEON_SAREA_DEFINES__ 42718dceddSDavid Howells #define __RADEON_SAREA_DEFINES__ 43718dceddSDavid Howells 44718dceddSDavid Howells /* Old style state flags, required for sarea interface (1.1 and 1.2 45718dceddSDavid Howells * clears) and 1.2 drm_vertex2 ioctl. 46718dceddSDavid Howells */ 47718dceddSDavid Howells #define RADEON_UPLOAD_CONTEXT 0x00000001 48718dceddSDavid Howells #define RADEON_UPLOAD_VERTFMT 0x00000002 49718dceddSDavid Howells #define RADEON_UPLOAD_LINE 0x00000004 50718dceddSDavid Howells #define RADEON_UPLOAD_BUMPMAP 0x00000008 51718dceddSDavid Howells #define RADEON_UPLOAD_MASKS 0x00000010 52718dceddSDavid Howells #define RADEON_UPLOAD_VIEWPORT 0x00000020 53718dceddSDavid Howells #define RADEON_UPLOAD_SETUP 0x00000040 54718dceddSDavid Howells #define RADEON_UPLOAD_TCL 0x00000080 55718dceddSDavid Howells #define RADEON_UPLOAD_MISC 0x00000100 56718dceddSDavid Howells #define RADEON_UPLOAD_TEX0 0x00000200 57718dceddSDavid Howells #define RADEON_UPLOAD_TEX1 0x00000400 58718dceddSDavid Howells #define RADEON_UPLOAD_TEX2 0x00000800 59718dceddSDavid Howells #define RADEON_UPLOAD_TEX0IMAGES 0x00001000 60718dceddSDavid Howells #define RADEON_UPLOAD_TEX1IMAGES 0x00002000 61718dceddSDavid Howells #define RADEON_UPLOAD_TEX2IMAGES 0x00004000 62718dceddSDavid Howells #define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */ 63718dceddSDavid Howells #define RADEON_REQUIRE_QUIESCENCE 0x00010000 64718dceddSDavid Howells #define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */ 65718dceddSDavid Howells #define RADEON_UPLOAD_ALL 0x003effff 66718dceddSDavid Howells #define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff 67718dceddSDavid Howells 68718dceddSDavid Howells /* New style per-packet identifiers for use in cmd_buffer ioctl with 69718dceddSDavid Howells * the RADEON_EMIT_PACKET command. Comments relate new packets to old 70718dceddSDavid Howells * state bits and the packet size: 71718dceddSDavid Howells */ 72718dceddSDavid Howells #define RADEON_EMIT_PP_MISC 0 /* context/7 */ 73718dceddSDavid Howells #define RADEON_EMIT_PP_CNTL 1 /* context/3 */ 74718dceddSDavid Howells #define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */ 75718dceddSDavid Howells #define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */ 76718dceddSDavid Howells #define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */ 77718dceddSDavid Howells #define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */ 78718dceddSDavid Howells #define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */ 79718dceddSDavid Howells #define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */ 80718dceddSDavid Howells #define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */ 81718dceddSDavid Howells #define RADEON_EMIT_SE_CNTL 9 /* setup/2 */ 82718dceddSDavid Howells #define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */ 83718dceddSDavid Howells #define RADEON_EMIT_RE_MISC 11 /* misc/1 */ 84718dceddSDavid Howells #define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */ 85718dceddSDavid Howells #define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */ 86718dceddSDavid Howells #define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */ 87718dceddSDavid Howells #define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */ 88718dceddSDavid Howells #define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */ 89718dceddSDavid Howells #define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */ 90718dceddSDavid Howells #define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */ 91718dceddSDavid Howells #define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */ 92718dceddSDavid Howells #define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */ 93718dceddSDavid Howells #define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */ 94718dceddSDavid Howells #define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */ 95718dceddSDavid Howells #define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */ 96718dceddSDavid Howells #define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */ 97718dceddSDavid Howells #define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */ 98718dceddSDavid Howells #define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */ 99718dceddSDavid Howells #define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */ 100718dceddSDavid Howells #define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */ 101718dceddSDavid Howells #define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */ 102718dceddSDavid Howells #define R200_EMIT_TFACTOR_0 30 /* tf/7 */ 103718dceddSDavid Howells #define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */ 104718dceddSDavid Howells #define R200_EMIT_VAP_CTL 32 /* vap/1 */ 105718dceddSDavid Howells #define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */ 106718dceddSDavid Howells #define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */ 107718dceddSDavid Howells #define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */ 108718dceddSDavid Howells #define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */ 109718dceddSDavid Howells #define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */ 110718dceddSDavid Howells #define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */ 111718dceddSDavid Howells #define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */ 112718dceddSDavid Howells #define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */ 113718dceddSDavid Howells #define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */ 114718dceddSDavid Howells #define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */ 115718dceddSDavid Howells #define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */ 116718dceddSDavid Howells #define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */ 117718dceddSDavid Howells #define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */ 118718dceddSDavid Howells #define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */ 119718dceddSDavid Howells #define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */ 120718dceddSDavid Howells #define R200_EMIT_VTE_CNTL 48 /* vte/1 */ 121718dceddSDavid Howells #define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */ 122718dceddSDavid Howells #define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */ 123718dceddSDavid Howells #define R200_EMIT_PP_CNTL_X 51 /* cst/1 */ 124718dceddSDavid Howells #define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */ 125718dceddSDavid Howells #define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */ 126718dceddSDavid Howells #define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */ 127718dceddSDavid Howells #define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */ 128718dceddSDavid Howells #define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */ 129718dceddSDavid Howells #define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */ 130718dceddSDavid Howells #define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */ 131718dceddSDavid Howells #define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */ 132718dceddSDavid Howells #define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */ 133718dceddSDavid Howells #define R200_EMIT_PP_CUBIC_FACES_0 61 134718dceddSDavid Howells #define R200_EMIT_PP_CUBIC_OFFSETS_0 62 135718dceddSDavid Howells #define R200_EMIT_PP_CUBIC_FACES_1 63 136718dceddSDavid Howells #define R200_EMIT_PP_CUBIC_OFFSETS_1 64 137718dceddSDavid Howells #define R200_EMIT_PP_CUBIC_FACES_2 65 138718dceddSDavid Howells #define R200_EMIT_PP_CUBIC_OFFSETS_2 66 139718dceddSDavid Howells #define R200_EMIT_PP_CUBIC_FACES_3 67 140718dceddSDavid Howells #define R200_EMIT_PP_CUBIC_OFFSETS_3 68 141718dceddSDavid Howells #define R200_EMIT_PP_CUBIC_FACES_4 69 142718dceddSDavid Howells #define R200_EMIT_PP_CUBIC_OFFSETS_4 70 143718dceddSDavid Howells #define R200_EMIT_PP_CUBIC_FACES_5 71 144718dceddSDavid Howells #define R200_EMIT_PP_CUBIC_OFFSETS_5 72 145718dceddSDavid Howells #define RADEON_EMIT_PP_TEX_SIZE_0 73 146718dceddSDavid Howells #define RADEON_EMIT_PP_TEX_SIZE_1 74 147718dceddSDavid Howells #define RADEON_EMIT_PP_TEX_SIZE_2 75 148718dceddSDavid Howells #define R200_EMIT_RB3D_BLENDCOLOR 76 149718dceddSDavid Howells #define R200_EMIT_TCL_POINT_SPRITE_CNTL 77 150718dceddSDavid Howells #define RADEON_EMIT_PP_CUBIC_FACES_0 78 151718dceddSDavid Howells #define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79 152718dceddSDavid Howells #define RADEON_EMIT_PP_CUBIC_FACES_1 80 153718dceddSDavid Howells #define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81 154718dceddSDavid Howells #define RADEON_EMIT_PP_CUBIC_FACES_2 82 155718dceddSDavid Howells #define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83 156718dceddSDavid Howells #define R200_EMIT_PP_TRI_PERF_CNTL 84 157718dceddSDavid Howells #define R200_EMIT_PP_AFS_0 85 158718dceddSDavid Howells #define R200_EMIT_PP_AFS_1 86 159718dceddSDavid Howells #define R200_EMIT_ATF_TFACTOR 87 160718dceddSDavid Howells #define R200_EMIT_PP_TXCTLALL_0 88 161718dceddSDavid Howells #define R200_EMIT_PP_TXCTLALL_1 89 162718dceddSDavid Howells #define R200_EMIT_PP_TXCTLALL_2 90 163718dceddSDavid Howells #define R200_EMIT_PP_TXCTLALL_3 91 164718dceddSDavid Howells #define R200_EMIT_PP_TXCTLALL_4 92 165718dceddSDavid Howells #define R200_EMIT_PP_TXCTLALL_5 93 166718dceddSDavid Howells #define R200_EMIT_VAP_PVS_CNTL 94 167718dceddSDavid Howells #define RADEON_MAX_STATE_PACKETS 95 168718dceddSDavid Howells 169718dceddSDavid Howells /* Commands understood by cmd_buffer ioctl. More can be added but 170718dceddSDavid Howells * obviously these can't be removed or changed: 171718dceddSDavid Howells */ 172718dceddSDavid Howells #define RADEON_CMD_PACKET 1 /* emit one of the register packets above */ 173718dceddSDavid Howells #define RADEON_CMD_SCALARS 2 /* emit scalar data */ 174718dceddSDavid Howells #define RADEON_CMD_VECTORS 3 /* emit vector data */ 175718dceddSDavid Howells #define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */ 176718dceddSDavid Howells #define RADEON_CMD_PACKET3 5 /* emit hw packet */ 177718dceddSDavid Howells #define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */ 178718dceddSDavid Howells #define RADEON_CMD_SCALARS2 7 /* r200 stopgap */ 179718dceddSDavid Howells #define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note: 180718dceddSDavid Howells * doesn't make the cpu wait, just 181718dceddSDavid Howells * the graphics hardware */ 182718dceddSDavid Howells #define RADEON_CMD_VECLINEAR 9 /* another r200 stopgap */ 183718dceddSDavid Howells 184718dceddSDavid Howells typedef union { 185718dceddSDavid Howells int i; 186718dceddSDavid Howells struct { 187718dceddSDavid Howells unsigned char cmd_type, pad0, pad1, pad2; 188718dceddSDavid Howells } header; 189718dceddSDavid Howells struct { 190718dceddSDavid Howells unsigned char cmd_type, packet_id, pad0, pad1; 191718dceddSDavid Howells } packet; 192718dceddSDavid Howells struct { 193718dceddSDavid Howells unsigned char cmd_type, offset, stride, count; 194718dceddSDavid Howells } scalars; 195718dceddSDavid Howells struct { 196718dceddSDavid Howells unsigned char cmd_type, offset, stride, count; 197718dceddSDavid Howells } vectors; 198718dceddSDavid Howells struct { 199718dceddSDavid Howells unsigned char cmd_type, addr_lo, addr_hi, count; 200718dceddSDavid Howells } veclinear; 201718dceddSDavid Howells struct { 202718dceddSDavid Howells unsigned char cmd_type, buf_idx, pad0, pad1; 203718dceddSDavid Howells } dma; 204718dceddSDavid Howells struct { 205718dceddSDavid Howells unsigned char cmd_type, flags, pad0, pad1; 206718dceddSDavid Howells } wait; 207718dceddSDavid Howells } drm_radeon_cmd_header_t; 208718dceddSDavid Howells 209718dceddSDavid Howells #define RADEON_WAIT_2D 0x1 210718dceddSDavid Howells #define RADEON_WAIT_3D 0x2 211718dceddSDavid Howells 212718dceddSDavid Howells /* Allowed parameters for R300_CMD_PACKET3 213718dceddSDavid Howells */ 214718dceddSDavid Howells #define R300_CMD_PACKET3_CLEAR 0 215718dceddSDavid Howells #define R300_CMD_PACKET3_RAW 1 216718dceddSDavid Howells 217718dceddSDavid Howells /* Commands understood by cmd_buffer ioctl for R300. 218718dceddSDavid Howells * The interface has not been stabilized, so some of these may be removed 219718dceddSDavid Howells * and eventually reordered before stabilization. 220718dceddSDavid Howells */ 221718dceddSDavid Howells #define R300_CMD_PACKET0 1 222718dceddSDavid Howells #define R300_CMD_VPU 2 /* emit vertex program upload */ 223718dceddSDavid Howells #define R300_CMD_PACKET3 3 /* emit a packet3 */ 224718dceddSDavid Howells #define R300_CMD_END3D 4 /* emit sequence ending 3d rendering */ 225718dceddSDavid Howells #define R300_CMD_CP_DELAY 5 226718dceddSDavid Howells #define R300_CMD_DMA_DISCARD 6 227718dceddSDavid Howells #define R300_CMD_WAIT 7 228718dceddSDavid Howells # define R300_WAIT_2D 0x1 229718dceddSDavid Howells # define R300_WAIT_3D 0x2 230718dceddSDavid Howells /* these two defines are DOING IT WRONG - however 231718dceddSDavid Howells * we have userspace which relies on using these. 232718dceddSDavid Howells * The wait interface is backwards compat new 233718dceddSDavid Howells * code should use the NEW_WAIT defines below 234718dceddSDavid Howells * THESE ARE NOT BIT FIELDS 235718dceddSDavid Howells */ 236718dceddSDavid Howells # define R300_WAIT_2D_CLEAN 0x3 237718dceddSDavid Howells # define R300_WAIT_3D_CLEAN 0x4 238718dceddSDavid Howells 239718dceddSDavid Howells # define R300_NEW_WAIT_2D_3D 0x3 240718dceddSDavid Howells # define R300_NEW_WAIT_2D_2D_CLEAN 0x4 241718dceddSDavid Howells # define R300_NEW_WAIT_3D_3D_CLEAN 0x6 242718dceddSDavid Howells # define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8 243718dceddSDavid Howells 244718dceddSDavid Howells #define R300_CMD_SCRATCH 8 245718dceddSDavid Howells #define R300_CMD_R500FP 9 246718dceddSDavid Howells 247718dceddSDavid Howells typedef union { 248718dceddSDavid Howells unsigned int u; 249718dceddSDavid Howells struct { 250718dceddSDavid Howells unsigned char cmd_type, pad0, pad1, pad2; 251718dceddSDavid Howells } header; 252718dceddSDavid Howells struct { 253718dceddSDavid Howells unsigned char cmd_type, count, reglo, reghi; 254718dceddSDavid Howells } packet0; 255718dceddSDavid Howells struct { 256718dceddSDavid Howells unsigned char cmd_type, count, adrlo, adrhi; 257718dceddSDavid Howells } vpu; 258718dceddSDavid Howells struct { 259718dceddSDavid Howells unsigned char cmd_type, packet, pad0, pad1; 260718dceddSDavid Howells } packet3; 261718dceddSDavid Howells struct { 262718dceddSDavid Howells unsigned char cmd_type, packet; 263718dceddSDavid Howells unsigned short count; /* amount of packet2 to emit */ 264718dceddSDavid Howells } delay; 265718dceddSDavid Howells struct { 266718dceddSDavid Howells unsigned char cmd_type, buf_idx, pad0, pad1; 267718dceddSDavid Howells } dma; 268718dceddSDavid Howells struct { 269718dceddSDavid Howells unsigned char cmd_type, flags, pad0, pad1; 270718dceddSDavid Howells } wait; 271718dceddSDavid Howells struct { 272718dceddSDavid Howells unsigned char cmd_type, reg, n_bufs, flags; 273718dceddSDavid Howells } scratch; 274718dceddSDavid Howells struct { 275718dceddSDavid Howells unsigned char cmd_type, count, adrlo, adrhi_flags; 276718dceddSDavid Howells } r500fp; 277718dceddSDavid Howells } drm_r300_cmd_header_t; 278718dceddSDavid Howells 279718dceddSDavid Howells #define RADEON_FRONT 0x1 280718dceddSDavid Howells #define RADEON_BACK 0x2 281718dceddSDavid Howells #define RADEON_DEPTH 0x4 282718dceddSDavid Howells #define RADEON_STENCIL 0x8 283718dceddSDavid Howells #define RADEON_CLEAR_FASTZ 0x80000000 284718dceddSDavid Howells #define RADEON_USE_HIERZ 0x40000000 285718dceddSDavid Howells #define RADEON_USE_COMP_ZBUF 0x20000000 286718dceddSDavid Howells 287718dceddSDavid Howells #define R500FP_CONSTANT_TYPE (1 << 1) 288718dceddSDavid Howells #define R500FP_CONSTANT_CLAMP (1 << 2) 289718dceddSDavid Howells 290718dceddSDavid Howells /* Primitive types 291718dceddSDavid Howells */ 292718dceddSDavid Howells #define RADEON_POINTS 0x1 293718dceddSDavid Howells #define RADEON_LINES 0x2 294718dceddSDavid Howells #define RADEON_LINE_STRIP 0x3 295718dceddSDavid Howells #define RADEON_TRIANGLES 0x4 296718dceddSDavid Howells #define RADEON_TRIANGLE_FAN 0x5 297718dceddSDavid Howells #define RADEON_TRIANGLE_STRIP 0x6 298718dceddSDavid Howells 299718dceddSDavid Howells /* Vertex/indirect buffer size 300718dceddSDavid Howells */ 301718dceddSDavid Howells #define RADEON_BUFFER_SIZE 65536 302718dceddSDavid Howells 303718dceddSDavid Howells /* Byte offsets for indirect buffer data 304718dceddSDavid Howells */ 305718dceddSDavid Howells #define RADEON_INDEX_PRIM_OFFSET 20 306718dceddSDavid Howells 307718dceddSDavid Howells #define RADEON_SCRATCH_REG_OFFSET 32 308718dceddSDavid Howells 309718dceddSDavid Howells #define R600_SCRATCH_REG_OFFSET 256 310718dceddSDavid Howells 311718dceddSDavid Howells #define RADEON_NR_SAREA_CLIPRECTS 12 312718dceddSDavid Howells 313718dceddSDavid Howells /* There are 2 heaps (local/GART). Each region within a heap is a 314718dceddSDavid Howells * minimum of 64k, and there are at most 64 of them per heap. 315718dceddSDavid Howells */ 316718dceddSDavid Howells #define RADEON_LOCAL_TEX_HEAP 0 317718dceddSDavid Howells #define RADEON_GART_TEX_HEAP 1 318718dceddSDavid Howells #define RADEON_NR_TEX_HEAPS 2 319718dceddSDavid Howells #define RADEON_NR_TEX_REGIONS 64 320718dceddSDavid Howells #define RADEON_LOG_TEX_GRANULARITY 16 321718dceddSDavid Howells 322718dceddSDavid Howells #define RADEON_MAX_TEXTURE_LEVELS 12 323718dceddSDavid Howells #define RADEON_MAX_TEXTURE_UNITS 3 324718dceddSDavid Howells 325718dceddSDavid Howells #define RADEON_MAX_SURFACES 8 326718dceddSDavid Howells 327718dceddSDavid Howells /* Blits have strict offset rules. All blit offset must be aligned on 328718dceddSDavid Howells * a 1K-byte boundary. 329718dceddSDavid Howells */ 330718dceddSDavid Howells #define RADEON_OFFSET_SHIFT 10 331718dceddSDavid Howells #define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT) 332718dceddSDavid Howells #define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1) 333718dceddSDavid Howells 334718dceddSDavid Howells #endif /* __RADEON_SAREA_DEFINES__ */ 335718dceddSDavid Howells 336718dceddSDavid Howells typedef struct { 337718dceddSDavid Howells unsigned int red; 338718dceddSDavid Howells unsigned int green; 339718dceddSDavid Howells unsigned int blue; 340718dceddSDavid Howells unsigned int alpha; 341718dceddSDavid Howells } radeon_color_regs_t; 342718dceddSDavid Howells 343718dceddSDavid Howells typedef struct { 344718dceddSDavid Howells /* Context state */ 345718dceddSDavid Howells unsigned int pp_misc; /* 0x1c14 */ 346718dceddSDavid Howells unsigned int pp_fog_color; 347718dceddSDavid Howells unsigned int re_solid_color; 348718dceddSDavid Howells unsigned int rb3d_blendcntl; 349718dceddSDavid Howells unsigned int rb3d_depthoffset; 350718dceddSDavid Howells unsigned int rb3d_depthpitch; 351718dceddSDavid Howells unsigned int rb3d_zstencilcntl; 352718dceddSDavid Howells 353718dceddSDavid Howells unsigned int pp_cntl; /* 0x1c38 */ 354718dceddSDavid Howells unsigned int rb3d_cntl; 355718dceddSDavid Howells unsigned int rb3d_coloroffset; 356718dceddSDavid Howells unsigned int re_width_height; 357718dceddSDavid Howells unsigned int rb3d_colorpitch; 358718dceddSDavid Howells unsigned int se_cntl; 359718dceddSDavid Howells 360718dceddSDavid Howells /* Vertex format state */ 361718dceddSDavid Howells unsigned int se_coord_fmt; /* 0x1c50 */ 362718dceddSDavid Howells 363718dceddSDavid Howells /* Line state */ 364718dceddSDavid Howells unsigned int re_line_pattern; /* 0x1cd0 */ 365718dceddSDavid Howells unsigned int re_line_state; 366718dceddSDavid Howells 367718dceddSDavid Howells unsigned int se_line_width; /* 0x1db8 */ 368718dceddSDavid Howells 369718dceddSDavid Howells /* Bumpmap state */ 370718dceddSDavid Howells unsigned int pp_lum_matrix; /* 0x1d00 */ 371718dceddSDavid Howells 372718dceddSDavid Howells unsigned int pp_rot_matrix_0; /* 0x1d58 */ 373718dceddSDavid Howells unsigned int pp_rot_matrix_1; 374718dceddSDavid Howells 375718dceddSDavid Howells /* Mask state */ 376718dceddSDavid Howells unsigned int rb3d_stencilrefmask; /* 0x1d7c */ 377718dceddSDavid Howells unsigned int rb3d_ropcntl; 378718dceddSDavid Howells unsigned int rb3d_planemask; 379718dceddSDavid Howells 380718dceddSDavid Howells /* Viewport state */ 381718dceddSDavid Howells unsigned int se_vport_xscale; /* 0x1d98 */ 382718dceddSDavid Howells unsigned int se_vport_xoffset; 383718dceddSDavid Howells unsigned int se_vport_yscale; 384718dceddSDavid Howells unsigned int se_vport_yoffset; 385718dceddSDavid Howells unsigned int se_vport_zscale; 386718dceddSDavid Howells unsigned int se_vport_zoffset; 387718dceddSDavid Howells 388718dceddSDavid Howells /* Setup state */ 389718dceddSDavid Howells unsigned int se_cntl_status; /* 0x2140 */ 390718dceddSDavid Howells 391718dceddSDavid Howells /* Misc state */ 392718dceddSDavid Howells unsigned int re_top_left; /* 0x26c0 */ 393718dceddSDavid Howells unsigned int re_misc; 394718dceddSDavid Howells } drm_radeon_context_regs_t; 395718dceddSDavid Howells 396718dceddSDavid Howells typedef struct { 397718dceddSDavid Howells /* Zbias state */ 398718dceddSDavid Howells unsigned int se_zbias_factor; /* 0x1dac */ 399718dceddSDavid Howells unsigned int se_zbias_constant; 400718dceddSDavid Howells } drm_radeon_context2_regs_t; 401718dceddSDavid Howells 402718dceddSDavid Howells /* Setup registers for each texture unit 403718dceddSDavid Howells */ 404718dceddSDavid Howells typedef struct { 405718dceddSDavid Howells unsigned int pp_txfilter; 406718dceddSDavid Howells unsigned int pp_txformat; 407718dceddSDavid Howells unsigned int pp_txoffset; 408718dceddSDavid Howells unsigned int pp_txcblend; 409718dceddSDavid Howells unsigned int pp_txablend; 410718dceddSDavid Howells unsigned int pp_tfactor; 411718dceddSDavid Howells unsigned int pp_border_color; 412718dceddSDavid Howells } drm_radeon_texture_regs_t; 413718dceddSDavid Howells 414718dceddSDavid Howells typedef struct { 415718dceddSDavid Howells unsigned int start; 416718dceddSDavid Howells unsigned int finish; 417718dceddSDavid Howells unsigned int prim:8; 418718dceddSDavid Howells unsigned int stateidx:8; 419718dceddSDavid Howells unsigned int numverts:16; /* overloaded as offset/64 for elt prims */ 420718dceddSDavid Howells unsigned int vc_format; /* vertex format */ 421718dceddSDavid Howells } drm_radeon_prim_t; 422718dceddSDavid Howells 423718dceddSDavid Howells typedef struct { 424718dceddSDavid Howells drm_radeon_context_regs_t context; 425718dceddSDavid Howells drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS]; 426718dceddSDavid Howells drm_radeon_context2_regs_t context2; 427718dceddSDavid Howells unsigned int dirty; 428718dceddSDavid Howells } drm_radeon_state_t; 429718dceddSDavid Howells 430718dceddSDavid Howells typedef struct { 431718dceddSDavid Howells /* The channel for communication of state information to the 432718dceddSDavid Howells * kernel on firing a vertex buffer with either of the 433718dceddSDavid Howells * obsoleted vertex/index ioctls. 434718dceddSDavid Howells */ 435718dceddSDavid Howells drm_radeon_context_regs_t context_state; 436718dceddSDavid Howells drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS]; 437718dceddSDavid Howells unsigned int dirty; 438718dceddSDavid Howells unsigned int vertsize; 439718dceddSDavid Howells unsigned int vc_format; 440718dceddSDavid Howells 441718dceddSDavid Howells /* The current cliprects, or a subset thereof. 442718dceddSDavid Howells */ 443718dceddSDavid Howells struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS]; 444718dceddSDavid Howells unsigned int nbox; 445718dceddSDavid Howells 446718dceddSDavid Howells /* Counters for client-side throttling of rendering clients. 447718dceddSDavid Howells */ 448718dceddSDavid Howells unsigned int last_frame; 449718dceddSDavid Howells unsigned int last_dispatch; 450718dceddSDavid Howells unsigned int last_clear; 451718dceddSDavid Howells 452718dceddSDavid Howells struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS + 453718dceddSDavid Howells 1]; 454718dceddSDavid Howells unsigned int tex_age[RADEON_NR_TEX_HEAPS]; 455718dceddSDavid Howells int ctx_owner; 456718dceddSDavid Howells int pfState; /* number of 3d windows (0,1,2ormore) */ 457718dceddSDavid Howells int pfCurrentPage; /* which buffer is being displayed? */ 458718dceddSDavid Howells int crtc2_base; /* CRTC2 frame offset */ 459718dceddSDavid Howells int tiling_enabled; /* set by drm, read by 2d + 3d clients */ 460718dceddSDavid Howells } drm_radeon_sarea_t; 461718dceddSDavid Howells 462718dceddSDavid Howells /* WARNING: If you change any of these defines, make sure to change the 463718dceddSDavid Howells * defines in the Xserver file (xf86drmRadeon.h) 464718dceddSDavid Howells * 465718dceddSDavid Howells * KW: actually it's illegal to change any of this (backwards compatibility). 466718dceddSDavid Howells */ 467718dceddSDavid Howells 468718dceddSDavid Howells /* Radeon specific ioctls 469718dceddSDavid Howells * The device specific ioctl range is 0x40 to 0x79. 470718dceddSDavid Howells */ 471718dceddSDavid Howells #define DRM_RADEON_CP_INIT 0x00 472718dceddSDavid Howells #define DRM_RADEON_CP_START 0x01 473718dceddSDavid Howells #define DRM_RADEON_CP_STOP 0x02 474718dceddSDavid Howells #define DRM_RADEON_CP_RESET 0x03 475718dceddSDavid Howells #define DRM_RADEON_CP_IDLE 0x04 476718dceddSDavid Howells #define DRM_RADEON_RESET 0x05 477718dceddSDavid Howells #define DRM_RADEON_FULLSCREEN 0x06 478718dceddSDavid Howells #define DRM_RADEON_SWAP 0x07 479718dceddSDavid Howells #define DRM_RADEON_CLEAR 0x08 480718dceddSDavid Howells #define DRM_RADEON_VERTEX 0x09 481718dceddSDavid Howells #define DRM_RADEON_INDICES 0x0A 482718dceddSDavid Howells #define DRM_RADEON_NOT_USED 483718dceddSDavid Howells #define DRM_RADEON_STIPPLE 0x0C 484718dceddSDavid Howells #define DRM_RADEON_INDIRECT 0x0D 485718dceddSDavid Howells #define DRM_RADEON_TEXTURE 0x0E 486718dceddSDavid Howells #define DRM_RADEON_VERTEX2 0x0F 487718dceddSDavid Howells #define DRM_RADEON_CMDBUF 0x10 488718dceddSDavid Howells #define DRM_RADEON_GETPARAM 0x11 489718dceddSDavid Howells #define DRM_RADEON_FLIP 0x12 490718dceddSDavid Howells #define DRM_RADEON_ALLOC 0x13 491718dceddSDavid Howells #define DRM_RADEON_FREE 0x14 492718dceddSDavid Howells #define DRM_RADEON_INIT_HEAP 0x15 493718dceddSDavid Howells #define DRM_RADEON_IRQ_EMIT 0x16 494718dceddSDavid Howells #define DRM_RADEON_IRQ_WAIT 0x17 495718dceddSDavid Howells #define DRM_RADEON_CP_RESUME 0x18 496718dceddSDavid Howells #define DRM_RADEON_SETPARAM 0x19 497718dceddSDavid Howells #define DRM_RADEON_SURF_ALLOC 0x1a 498718dceddSDavid Howells #define DRM_RADEON_SURF_FREE 0x1b 499718dceddSDavid Howells /* KMS ioctl */ 500718dceddSDavid Howells #define DRM_RADEON_GEM_INFO 0x1c 501718dceddSDavid Howells #define DRM_RADEON_GEM_CREATE 0x1d 502718dceddSDavid Howells #define DRM_RADEON_GEM_MMAP 0x1e 503718dceddSDavid Howells #define DRM_RADEON_GEM_PREAD 0x21 504718dceddSDavid Howells #define DRM_RADEON_GEM_PWRITE 0x22 505718dceddSDavid Howells #define DRM_RADEON_GEM_SET_DOMAIN 0x23 506718dceddSDavid Howells #define DRM_RADEON_GEM_WAIT_IDLE 0x24 507718dceddSDavid Howells #define DRM_RADEON_CS 0x26 508718dceddSDavid Howells #define DRM_RADEON_INFO 0x27 509718dceddSDavid Howells #define DRM_RADEON_GEM_SET_TILING 0x28 510718dceddSDavid Howells #define DRM_RADEON_GEM_GET_TILING 0x29 511718dceddSDavid Howells #define DRM_RADEON_GEM_BUSY 0x2a 512718dceddSDavid Howells #define DRM_RADEON_GEM_VA 0x2b 513718dceddSDavid Howells 514718dceddSDavid Howells #define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t) 515718dceddSDavid Howells #define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START) 516718dceddSDavid Howells #define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t) 517718dceddSDavid Howells #define DRM_IOCTL_RADEON_CP_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET) 518718dceddSDavid Howells #define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE) 519718dceddSDavid Howells #define DRM_IOCTL_RADEON_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET) 520718dceddSDavid Howells #define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t) 521718dceddSDavid Howells #define DRM_IOCTL_RADEON_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP) 522718dceddSDavid Howells #define DRM_IOCTL_RADEON_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t) 523718dceddSDavid Howells #define DRM_IOCTL_RADEON_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t) 524718dceddSDavid Howells #define DRM_IOCTL_RADEON_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t) 525718dceddSDavid Howells #define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t) 526718dceddSDavid Howells #define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t) 527718dceddSDavid Howells #define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t) 528718dceddSDavid Howells #define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t) 529718dceddSDavid Howells #define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t) 530718dceddSDavid Howells #define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t) 531718dceddSDavid Howells #define DRM_IOCTL_RADEON_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_FLIP) 532718dceddSDavid Howells #define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t) 533718dceddSDavid Howells #define DRM_IOCTL_RADEON_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t) 534718dceddSDavid Howells #define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t) 535718dceddSDavid Howells #define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t) 536718dceddSDavid Howells #define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t) 537718dceddSDavid Howells #define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME) 538718dceddSDavid Howells #define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t) 539718dceddSDavid Howells #define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t) 540718dceddSDavid Howells #define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t) 541718dceddSDavid Howells /* KMS */ 542718dceddSDavid Howells #define DRM_IOCTL_RADEON_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INFO, struct drm_radeon_gem_info) 543718dceddSDavid Howells #define DRM_IOCTL_RADEON_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, struct drm_radeon_gem_create) 544718dceddSDavid Howells #define DRM_IOCTL_RADEON_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_MMAP, struct drm_radeon_gem_mmap) 545718dceddSDavid Howells #define DRM_IOCTL_RADEON_GEM_PREAD DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread) 546718dceddSDavid Howells #define DRM_IOCTL_RADEON_GEM_PWRITE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite) 547718dceddSDavid Howells #define DRM_IOCTL_RADEON_GEM_SET_DOMAIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain) 548718dceddSDavid Howells #define DRM_IOCTL_RADEON_GEM_WAIT_IDLE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_IDLE, struct drm_radeon_gem_wait_idle) 549718dceddSDavid Howells #define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs) 550718dceddSDavid Howells #define DRM_IOCTL_RADEON_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info) 551718dceddSDavid Howells #define DRM_IOCTL_RADEON_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling) 552718dceddSDavid Howells #define DRM_IOCTL_RADEON_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling) 553718dceddSDavid Howells #define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy) 554718dceddSDavid Howells #define DRM_IOCTL_RADEON_GEM_VA DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_VA, struct drm_radeon_gem_va) 555718dceddSDavid Howells 556718dceddSDavid Howells typedef struct drm_radeon_init { 557718dceddSDavid Howells enum { 558718dceddSDavid Howells RADEON_INIT_CP = 0x01, 559718dceddSDavid Howells RADEON_CLEANUP_CP = 0x02, 560718dceddSDavid Howells RADEON_INIT_R200_CP = 0x03, 561718dceddSDavid Howells RADEON_INIT_R300_CP = 0x04, 562718dceddSDavid Howells RADEON_INIT_R600_CP = 0x05 563718dceddSDavid Howells } func; 564718dceddSDavid Howells unsigned long sarea_priv_offset; 565718dceddSDavid Howells int is_pci; 566718dceddSDavid Howells int cp_mode; 567718dceddSDavid Howells int gart_size; 568718dceddSDavid Howells int ring_size; 569718dceddSDavid Howells int usec_timeout; 570718dceddSDavid Howells 571718dceddSDavid Howells unsigned int fb_bpp; 572718dceddSDavid Howells unsigned int front_offset, front_pitch; 573718dceddSDavid Howells unsigned int back_offset, back_pitch; 574718dceddSDavid Howells unsigned int depth_bpp; 575718dceddSDavid Howells unsigned int depth_offset, depth_pitch; 576718dceddSDavid Howells 577718dceddSDavid Howells unsigned long fb_offset; 578718dceddSDavid Howells unsigned long mmio_offset; 579718dceddSDavid Howells unsigned long ring_offset; 580718dceddSDavid Howells unsigned long ring_rptr_offset; 581718dceddSDavid Howells unsigned long buffers_offset; 582718dceddSDavid Howells unsigned long gart_textures_offset; 583718dceddSDavid Howells } drm_radeon_init_t; 584718dceddSDavid Howells 585718dceddSDavid Howells typedef struct drm_radeon_cp_stop { 586718dceddSDavid Howells int flush; 587718dceddSDavid Howells int idle; 588718dceddSDavid Howells } drm_radeon_cp_stop_t; 589718dceddSDavid Howells 590718dceddSDavid Howells typedef struct drm_radeon_fullscreen { 591718dceddSDavid Howells enum { 592718dceddSDavid Howells RADEON_INIT_FULLSCREEN = 0x01, 593718dceddSDavid Howells RADEON_CLEANUP_FULLSCREEN = 0x02 594718dceddSDavid Howells } func; 595718dceddSDavid Howells } drm_radeon_fullscreen_t; 596718dceddSDavid Howells 597718dceddSDavid Howells #define CLEAR_X1 0 598718dceddSDavid Howells #define CLEAR_Y1 1 599718dceddSDavid Howells #define CLEAR_X2 2 600718dceddSDavid Howells #define CLEAR_Y2 3 601718dceddSDavid Howells #define CLEAR_DEPTH 4 602718dceddSDavid Howells 603718dceddSDavid Howells typedef union drm_radeon_clear_rect { 604718dceddSDavid Howells float f[5]; 605718dceddSDavid Howells unsigned int ui[5]; 606718dceddSDavid Howells } drm_radeon_clear_rect_t; 607718dceddSDavid Howells 608718dceddSDavid Howells typedef struct drm_radeon_clear { 609718dceddSDavid Howells unsigned int flags; 610718dceddSDavid Howells unsigned int clear_color; 611718dceddSDavid Howells unsigned int clear_depth; 612718dceddSDavid Howells unsigned int color_mask; 613718dceddSDavid Howells unsigned int depth_mask; /* misnamed field: should be stencil */ 614718dceddSDavid Howells drm_radeon_clear_rect_t __user *depth_boxes; 615718dceddSDavid Howells } drm_radeon_clear_t; 616718dceddSDavid Howells 617718dceddSDavid Howells typedef struct drm_radeon_vertex { 618718dceddSDavid Howells int prim; 619718dceddSDavid Howells int idx; /* Index of vertex buffer */ 620718dceddSDavid Howells int count; /* Number of vertices in buffer */ 621718dceddSDavid Howells int discard; /* Client finished with buffer? */ 622718dceddSDavid Howells } drm_radeon_vertex_t; 623718dceddSDavid Howells 624718dceddSDavid Howells typedef struct drm_radeon_indices { 625718dceddSDavid Howells int prim; 626718dceddSDavid Howells int idx; 627718dceddSDavid Howells int start; 628718dceddSDavid Howells int end; 629718dceddSDavid Howells int discard; /* Client finished with buffer? */ 630718dceddSDavid Howells } drm_radeon_indices_t; 631718dceddSDavid Howells 632718dceddSDavid Howells /* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices 633718dceddSDavid Howells * - allows multiple primitives and state changes in a single ioctl 634718dceddSDavid Howells * - supports driver change to emit native primitives 635718dceddSDavid Howells */ 636718dceddSDavid Howells typedef struct drm_radeon_vertex2 { 637718dceddSDavid Howells int idx; /* Index of vertex buffer */ 638718dceddSDavid Howells int discard; /* Client finished with buffer? */ 639718dceddSDavid Howells int nr_states; 640718dceddSDavid Howells drm_radeon_state_t __user *state; 641718dceddSDavid Howells int nr_prims; 642718dceddSDavid Howells drm_radeon_prim_t __user *prim; 643718dceddSDavid Howells } drm_radeon_vertex2_t; 644718dceddSDavid Howells 645718dceddSDavid Howells /* v1.3 - obsoletes drm_radeon_vertex2 646718dceddSDavid Howells * - allows arbitrarily large cliprect list 647718dceddSDavid Howells * - allows updating of tcl packet, vector and scalar state 648718dceddSDavid Howells * - allows memory-efficient description of state updates 649718dceddSDavid Howells * - allows state to be emitted without a primitive 650718dceddSDavid Howells * (for clears, ctx switches) 651718dceddSDavid Howells * - allows more than one dma buffer to be referenced per ioctl 652718dceddSDavid Howells * - supports tcl driver 653718dceddSDavid Howells * - may be extended in future versions with new cmd types, packets 654718dceddSDavid Howells */ 655718dceddSDavid Howells typedef struct drm_radeon_cmd_buffer { 656718dceddSDavid Howells int bufsz; 657718dceddSDavid Howells char __user *buf; 658718dceddSDavid Howells int nbox; 659718dceddSDavid Howells struct drm_clip_rect __user *boxes; 660718dceddSDavid Howells } drm_radeon_cmd_buffer_t; 661718dceddSDavid Howells 662718dceddSDavid Howells typedef struct drm_radeon_tex_image { 663718dceddSDavid Howells unsigned int x, y; /* Blit coordinates */ 664718dceddSDavid Howells unsigned int width, height; 665718dceddSDavid Howells const void __user *data; 666718dceddSDavid Howells } drm_radeon_tex_image_t; 667718dceddSDavid Howells 668718dceddSDavid Howells typedef struct drm_radeon_texture { 669718dceddSDavid Howells unsigned int offset; 670718dceddSDavid Howells int pitch; 671718dceddSDavid Howells int format; 672718dceddSDavid Howells int width; /* Texture image coordinates */ 673718dceddSDavid Howells int height; 674718dceddSDavid Howells drm_radeon_tex_image_t __user *image; 675718dceddSDavid Howells } drm_radeon_texture_t; 676718dceddSDavid Howells 677718dceddSDavid Howells typedef struct drm_radeon_stipple { 678718dceddSDavid Howells unsigned int __user *mask; 679718dceddSDavid Howells } drm_radeon_stipple_t; 680718dceddSDavid Howells 681718dceddSDavid Howells typedef struct drm_radeon_indirect { 682718dceddSDavid Howells int idx; 683718dceddSDavid Howells int start; 684718dceddSDavid Howells int end; 685718dceddSDavid Howells int discard; 686718dceddSDavid Howells } drm_radeon_indirect_t; 687718dceddSDavid Howells 688718dceddSDavid Howells /* enum for card type parameters */ 689718dceddSDavid Howells #define RADEON_CARD_PCI 0 690718dceddSDavid Howells #define RADEON_CARD_AGP 1 691718dceddSDavid Howells #define RADEON_CARD_PCIE 2 692718dceddSDavid Howells 693718dceddSDavid Howells /* 1.3: An ioctl to get parameters that aren't available to the 3d 694718dceddSDavid Howells * client any other way. 695718dceddSDavid Howells */ 696718dceddSDavid Howells #define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */ 697718dceddSDavid Howells #define RADEON_PARAM_LAST_FRAME 2 698718dceddSDavid Howells #define RADEON_PARAM_LAST_DISPATCH 3 699718dceddSDavid Howells #define RADEON_PARAM_LAST_CLEAR 4 700718dceddSDavid Howells /* Added with DRM version 1.6. */ 701718dceddSDavid Howells #define RADEON_PARAM_IRQ_NR 5 702718dceddSDavid Howells #define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */ 703718dceddSDavid Howells /* Added with DRM version 1.8. */ 704718dceddSDavid Howells #define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */ 705718dceddSDavid Howells #define RADEON_PARAM_STATUS_HANDLE 8 706718dceddSDavid Howells #define RADEON_PARAM_SAREA_HANDLE 9 707718dceddSDavid Howells #define RADEON_PARAM_GART_TEX_HANDLE 10 708718dceddSDavid Howells #define RADEON_PARAM_SCRATCH_OFFSET 11 709718dceddSDavid Howells #define RADEON_PARAM_CARD_TYPE 12 710718dceddSDavid Howells #define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */ 711718dceddSDavid Howells #define RADEON_PARAM_FB_LOCATION 14 /* FB location */ 712718dceddSDavid Howells #define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */ 713718dceddSDavid Howells #define RADEON_PARAM_DEVICE_ID 16 714718dceddSDavid Howells #define RADEON_PARAM_NUM_Z_PIPES 17 /* num Z pipes */ 715718dceddSDavid Howells 716718dceddSDavid Howells typedef struct drm_radeon_getparam { 717718dceddSDavid Howells int param; 718718dceddSDavid Howells void __user *value; 719718dceddSDavid Howells } drm_radeon_getparam_t; 720718dceddSDavid Howells 721718dceddSDavid Howells /* 1.6: Set up a memory manager for regions of shared memory: 722718dceddSDavid Howells */ 723718dceddSDavid Howells #define RADEON_MEM_REGION_GART 1 724718dceddSDavid Howells #define RADEON_MEM_REGION_FB 2 725718dceddSDavid Howells 726718dceddSDavid Howells typedef struct drm_radeon_mem_alloc { 727718dceddSDavid Howells int region; 728718dceddSDavid Howells int alignment; 729718dceddSDavid Howells int size; 730718dceddSDavid Howells int __user *region_offset; /* offset from start of fb or GART */ 731718dceddSDavid Howells } drm_radeon_mem_alloc_t; 732718dceddSDavid Howells 733718dceddSDavid Howells typedef struct drm_radeon_mem_free { 734718dceddSDavid Howells int region; 735718dceddSDavid Howells int region_offset; 736718dceddSDavid Howells } drm_radeon_mem_free_t; 737718dceddSDavid Howells 738718dceddSDavid Howells typedef struct drm_radeon_mem_init_heap { 739718dceddSDavid Howells int region; 740718dceddSDavid Howells int size; 741718dceddSDavid Howells int start; 742718dceddSDavid Howells } drm_radeon_mem_init_heap_t; 743718dceddSDavid Howells 744718dceddSDavid Howells /* 1.6: Userspace can request & wait on irq's: 745718dceddSDavid Howells */ 746718dceddSDavid Howells typedef struct drm_radeon_irq_emit { 747718dceddSDavid Howells int __user *irq_seq; 748718dceddSDavid Howells } drm_radeon_irq_emit_t; 749718dceddSDavid Howells 750718dceddSDavid Howells typedef struct drm_radeon_irq_wait { 751718dceddSDavid Howells int irq_seq; 752718dceddSDavid Howells } drm_radeon_irq_wait_t; 753718dceddSDavid Howells 754718dceddSDavid Howells /* 1.10: Clients tell the DRM where they think the framebuffer is located in 755718dceddSDavid Howells * the card's address space, via a new generic ioctl to set parameters 756718dceddSDavid Howells */ 757718dceddSDavid Howells 758718dceddSDavid Howells typedef struct drm_radeon_setparam { 759718dceddSDavid Howells unsigned int param; 760718dceddSDavid Howells __s64 value; 761718dceddSDavid Howells } drm_radeon_setparam_t; 762718dceddSDavid Howells 763718dceddSDavid Howells #define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */ 764718dceddSDavid Howells #define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */ 765718dceddSDavid Howells #define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */ 766718dceddSDavid Howells #define RADEON_SETPARAM_NEW_MEMMAP 4 /* Use new memory map */ 767718dceddSDavid Howells #define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 /* PCI GART Table Size */ 768718dceddSDavid Howells #define RADEON_SETPARAM_VBLANK_CRTC 6 /* VBLANK CRTC */ 769718dceddSDavid Howells /* 1.14: Clients can allocate/free a surface 770718dceddSDavid Howells */ 771718dceddSDavid Howells typedef struct drm_radeon_surface_alloc { 772718dceddSDavid Howells unsigned int address; 773718dceddSDavid Howells unsigned int size; 774718dceddSDavid Howells unsigned int flags; 775718dceddSDavid Howells } drm_radeon_surface_alloc_t; 776718dceddSDavid Howells 777718dceddSDavid Howells typedef struct drm_radeon_surface_free { 778718dceddSDavid Howells unsigned int address; 779718dceddSDavid Howells } drm_radeon_surface_free_t; 780718dceddSDavid Howells 781718dceddSDavid Howells #define DRM_RADEON_VBLANK_CRTC1 1 782718dceddSDavid Howells #define DRM_RADEON_VBLANK_CRTC2 2 783718dceddSDavid Howells 784718dceddSDavid Howells /* 785718dceddSDavid Howells * Kernel modesetting world below. 786718dceddSDavid Howells */ 787718dceddSDavid Howells #define RADEON_GEM_DOMAIN_CPU 0x1 788718dceddSDavid Howells #define RADEON_GEM_DOMAIN_GTT 0x2 789718dceddSDavid Howells #define RADEON_GEM_DOMAIN_VRAM 0x4 790718dceddSDavid Howells 791718dceddSDavid Howells struct drm_radeon_gem_info { 792718dceddSDavid Howells uint64_t gart_size; 793718dceddSDavid Howells uint64_t vram_size; 794718dceddSDavid Howells uint64_t vram_visible; 795718dceddSDavid Howells }; 796718dceddSDavid Howells 797718dceddSDavid Howells #define RADEON_GEM_NO_BACKING_STORE 1 798718dceddSDavid Howells 799718dceddSDavid Howells struct drm_radeon_gem_create { 800718dceddSDavid Howells uint64_t size; 801718dceddSDavid Howells uint64_t alignment; 802718dceddSDavid Howells uint32_t handle; 803718dceddSDavid Howells uint32_t initial_domain; 804718dceddSDavid Howells uint32_t flags; 805718dceddSDavid Howells }; 806718dceddSDavid Howells 807718dceddSDavid Howells #define RADEON_TILING_MACRO 0x1 808718dceddSDavid Howells #define RADEON_TILING_MICRO 0x2 809718dceddSDavid Howells #define RADEON_TILING_SWAP_16BIT 0x4 810718dceddSDavid Howells #define RADEON_TILING_SWAP_32BIT 0x8 811718dceddSDavid Howells /* this object requires a surface when mapped - i.e. front buffer */ 812718dceddSDavid Howells #define RADEON_TILING_SURFACE 0x10 813718dceddSDavid Howells #define RADEON_TILING_MICRO_SQUARE 0x20 814718dceddSDavid Howells #define RADEON_TILING_EG_BANKW_SHIFT 8 815718dceddSDavid Howells #define RADEON_TILING_EG_BANKW_MASK 0xf 816718dceddSDavid Howells #define RADEON_TILING_EG_BANKH_SHIFT 12 817718dceddSDavid Howells #define RADEON_TILING_EG_BANKH_MASK 0xf 818718dceddSDavid Howells #define RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT 16 819718dceddSDavid Howells #define RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK 0xf 820718dceddSDavid Howells #define RADEON_TILING_EG_TILE_SPLIT_SHIFT 24 821718dceddSDavid Howells #define RADEON_TILING_EG_TILE_SPLIT_MASK 0xf 822718dceddSDavid Howells #define RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT 28 823718dceddSDavid Howells #define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf 824718dceddSDavid Howells 825718dceddSDavid Howells struct drm_radeon_gem_set_tiling { 826718dceddSDavid Howells uint32_t handle; 827718dceddSDavid Howells uint32_t tiling_flags; 828718dceddSDavid Howells uint32_t pitch; 829718dceddSDavid Howells }; 830718dceddSDavid Howells 831718dceddSDavid Howells struct drm_radeon_gem_get_tiling { 832718dceddSDavid Howells uint32_t handle; 833718dceddSDavid Howells uint32_t tiling_flags; 834718dceddSDavid Howells uint32_t pitch; 835718dceddSDavid Howells }; 836718dceddSDavid Howells 837718dceddSDavid Howells struct drm_radeon_gem_mmap { 838718dceddSDavid Howells uint32_t handle; 839718dceddSDavid Howells uint32_t pad; 840718dceddSDavid Howells uint64_t offset; 841718dceddSDavid Howells uint64_t size; 842718dceddSDavid Howells uint64_t addr_ptr; 843718dceddSDavid Howells }; 844718dceddSDavid Howells 845718dceddSDavid Howells struct drm_radeon_gem_set_domain { 846718dceddSDavid Howells uint32_t handle; 847718dceddSDavid Howells uint32_t read_domains; 848718dceddSDavid Howells uint32_t write_domain; 849718dceddSDavid Howells }; 850718dceddSDavid Howells 851718dceddSDavid Howells struct drm_radeon_gem_wait_idle { 852718dceddSDavid Howells uint32_t handle; 853718dceddSDavid Howells uint32_t pad; 854718dceddSDavid Howells }; 855718dceddSDavid Howells 856718dceddSDavid Howells struct drm_radeon_gem_busy { 857718dceddSDavid Howells uint32_t handle; 858718dceddSDavid Howells uint32_t domain; 859718dceddSDavid Howells }; 860718dceddSDavid Howells 861718dceddSDavid Howells struct drm_radeon_gem_pread { 862718dceddSDavid Howells /** Handle for the object being read. */ 863718dceddSDavid Howells uint32_t handle; 864718dceddSDavid Howells uint32_t pad; 865718dceddSDavid Howells /** Offset into the object to read from */ 866718dceddSDavid Howells uint64_t offset; 867718dceddSDavid Howells /** Length of data to read */ 868718dceddSDavid Howells uint64_t size; 869718dceddSDavid Howells /** Pointer to write the data into. */ 870718dceddSDavid Howells /* void *, but pointers are not 32/64 compatible */ 871718dceddSDavid Howells uint64_t data_ptr; 872718dceddSDavid Howells }; 873718dceddSDavid Howells 874718dceddSDavid Howells struct drm_radeon_gem_pwrite { 875718dceddSDavid Howells /** Handle for the object being written to. */ 876718dceddSDavid Howells uint32_t handle; 877718dceddSDavid Howells uint32_t pad; 878718dceddSDavid Howells /** Offset into the object to write to */ 879718dceddSDavid Howells uint64_t offset; 880718dceddSDavid Howells /** Length of data to write */ 881718dceddSDavid Howells uint64_t size; 882718dceddSDavid Howells /** Pointer to read the data from. */ 883718dceddSDavid Howells /* void *, but pointers are not 32/64 compatible */ 884718dceddSDavid Howells uint64_t data_ptr; 885718dceddSDavid Howells }; 886718dceddSDavid Howells 887718dceddSDavid Howells #define RADEON_VA_MAP 1 888718dceddSDavid Howells #define RADEON_VA_UNMAP 2 889718dceddSDavid Howells 890718dceddSDavid Howells #define RADEON_VA_RESULT_OK 0 891718dceddSDavid Howells #define RADEON_VA_RESULT_ERROR 1 892718dceddSDavid Howells #define RADEON_VA_RESULT_VA_EXIST 2 893718dceddSDavid Howells 894718dceddSDavid Howells #define RADEON_VM_PAGE_VALID (1 << 0) 895718dceddSDavid Howells #define RADEON_VM_PAGE_READABLE (1 << 1) 896718dceddSDavid Howells #define RADEON_VM_PAGE_WRITEABLE (1 << 2) 897718dceddSDavid Howells #define RADEON_VM_PAGE_SYSTEM (1 << 3) 898718dceddSDavid Howells #define RADEON_VM_PAGE_SNOOPED (1 << 4) 899718dceddSDavid Howells 900718dceddSDavid Howells struct drm_radeon_gem_va { 901718dceddSDavid Howells uint32_t handle; 902718dceddSDavid Howells uint32_t operation; 903718dceddSDavid Howells uint32_t vm_id; 904718dceddSDavid Howells uint32_t flags; 905718dceddSDavid Howells uint64_t offset; 906718dceddSDavid Howells }; 907718dceddSDavid Howells 908718dceddSDavid Howells #define RADEON_CHUNK_ID_RELOCS 0x01 909718dceddSDavid Howells #define RADEON_CHUNK_ID_IB 0x02 910718dceddSDavid Howells #define RADEON_CHUNK_ID_FLAGS 0x03 911718dceddSDavid Howells #define RADEON_CHUNK_ID_CONST_IB 0x04 912718dceddSDavid Howells 913718dceddSDavid Howells /* The first dword of RADEON_CHUNK_ID_FLAGS is a uint32 of these flags: */ 914718dceddSDavid Howells #define RADEON_CS_KEEP_TILING_FLAGS 0x01 915718dceddSDavid Howells #define RADEON_CS_USE_VM 0x02 91657f57083SMarek Olšák #define RADEON_CS_END_OF_FRAME 0x04 /* a hint from userspace which CS is the last one */ 917718dceddSDavid Howells /* The second dword of RADEON_CHUNK_ID_FLAGS is a uint32 that sets the ring type */ 918718dceddSDavid Howells #define RADEON_CS_RING_GFX 0 919718dceddSDavid Howells #define RADEON_CS_RING_COMPUTE 1 920278a334cSAlex Deucher #define RADEON_CS_RING_DMA 2 921f2ba57b5SChristian König #define RADEON_CS_RING_UVD 3 922718dceddSDavid Howells /* The third dword of RADEON_CHUNK_ID_FLAGS is a sint32 that sets the priority */ 923718dceddSDavid Howells /* 0 = normal, + = higher priority, - = lower priority */ 924718dceddSDavid Howells 925718dceddSDavid Howells struct drm_radeon_cs_chunk { 926718dceddSDavid Howells uint32_t chunk_id; 927718dceddSDavid Howells uint32_t length_dw; 928718dceddSDavid Howells uint64_t chunk_data; 929718dceddSDavid Howells }; 930718dceddSDavid Howells 931718dceddSDavid Howells /* drm_radeon_cs_reloc.flags */ 932718dceddSDavid Howells 933718dceddSDavid Howells struct drm_radeon_cs_reloc { 934718dceddSDavid Howells uint32_t handle; 935718dceddSDavid Howells uint32_t read_domains; 936718dceddSDavid Howells uint32_t write_domain; 937718dceddSDavid Howells uint32_t flags; 938718dceddSDavid Howells }; 939718dceddSDavid Howells 940718dceddSDavid Howells struct drm_radeon_cs { 941718dceddSDavid Howells uint32_t num_chunks; 942718dceddSDavid Howells uint32_t cs_id; 943718dceddSDavid Howells /* this points to uint64_t * which point to cs chunks */ 944718dceddSDavid Howells uint64_t chunks; 945718dceddSDavid Howells /* updates to the limits after this CS ioctl */ 946718dceddSDavid Howells uint64_t gart_limit; 947718dceddSDavid Howells uint64_t vram_limit; 948718dceddSDavid Howells }; 949718dceddSDavid Howells 950718dceddSDavid Howells #define RADEON_INFO_DEVICE_ID 0x00 951718dceddSDavid Howells #define RADEON_INFO_NUM_GB_PIPES 0x01 952718dceddSDavid Howells #define RADEON_INFO_NUM_Z_PIPES 0x02 953718dceddSDavid Howells #define RADEON_INFO_ACCEL_WORKING 0x03 954718dceddSDavid Howells #define RADEON_INFO_CRTC_FROM_ID 0x04 955718dceddSDavid Howells #define RADEON_INFO_ACCEL_WORKING2 0x05 956718dceddSDavid Howells #define RADEON_INFO_TILING_CONFIG 0x06 957718dceddSDavid Howells #define RADEON_INFO_WANT_HYPERZ 0x07 958718dceddSDavid Howells #define RADEON_INFO_WANT_CMASK 0x08 /* get access to CMASK on r300 */ 959718dceddSDavid Howells #define RADEON_INFO_CLOCK_CRYSTAL_FREQ 0x09 /* clock crystal frequency */ 960718dceddSDavid Howells #define RADEON_INFO_NUM_BACKENDS 0x0a /* DB/backends for r600+ - need for OQ */ 961718dceddSDavid Howells #define RADEON_INFO_NUM_TILE_PIPES 0x0b /* tile pipes for r600+ */ 962718dceddSDavid Howells #define RADEON_INFO_FUSION_GART_WORKING 0x0c /* fusion writes to GTT were broken before this */ 963718dceddSDavid Howells #define RADEON_INFO_BACKEND_MAP 0x0d /* pipe to backend map, needed by mesa */ 964718dceddSDavid Howells /* virtual address start, va < start are reserved by the kernel */ 965718dceddSDavid Howells #define RADEON_INFO_VA_START 0x0e 966718dceddSDavid Howells /* maximum size of ib using the virtual memory cs */ 967718dceddSDavid Howells #define RADEON_INFO_IB_VM_MAX_SIZE 0x0f 968718dceddSDavid Howells /* max pipes - needed for compute shaders */ 969718dceddSDavid Howells #define RADEON_INFO_MAX_PIPES 0x10 970718dceddSDavid Howells /* timestamp for GL_ARB_timer_query (OpenGL), returns the current GPU clock */ 971718dceddSDavid Howells #define RADEON_INFO_TIMESTAMP 0x11 9722e1a7674SAlex Deucher /* max shader engines (SE) - needed for geometry shaders, etc. */ 9732e1a7674SAlex Deucher #define RADEON_INFO_MAX_SE 0x12 9742e1a7674SAlex Deucher /* max SH per SE */ 9752e1a7674SAlex Deucher #define RADEON_INFO_MAX_SH_PER_SE 0x13 976a0a53aa8SSamuel Li /* fast fb access is enabled */ 977a0a53aa8SSamuel Li #define RADEON_INFO_FASTFB_WORKING 0x14 978902aaef6SChristian König /* query if a RADEON_CS_RING_* submission is supported */ 979902aaef6SChristian König #define RADEON_INFO_RING_WORKING 0x15 98064d7b8beSJerome Glisse /* SI tile mode array */ 98164d7b8beSJerome Glisse #define RADEON_INFO_SI_TILE_MODE_ARRAY 0x16 982e5b9e750STom Stellard /* query if CP DMA is supported on the compute ring */ 983e5b9e750STom Stellard #define RADEON_INFO_SI_CP_DMA_COMPUTE 0x17 98432f79a8aSMichel Dänzer /* CIK macrotile mode array */ 98532f79a8aSMichel Dänzer #define RADEON_INFO_CIK_MACROTILE_MODE_ARRAY 0x18 986a0a53aa8SSamuel Li 987718dceddSDavid Howells 988718dceddSDavid Howells struct drm_radeon_info { 989718dceddSDavid Howells uint32_t request; 990718dceddSDavid Howells uint32_t pad; 991718dceddSDavid Howells uint64_t value; 992718dceddSDavid Howells }; 993718dceddSDavid Howells 99464d7b8beSJerome Glisse /* Those correspond to the tile index to use, this is to explicitly state 99564d7b8beSJerome Glisse * the API that is implicitly defined by the tile mode array. 99664d7b8beSJerome Glisse */ 99764d7b8beSJerome Glisse #define SI_TILE_MODE_COLOR_LINEAR_ALIGNED 8 99864d7b8beSJerome Glisse #define SI_TILE_MODE_COLOR_1D 13 99964d7b8beSJerome Glisse #define SI_TILE_MODE_COLOR_1D_SCANOUT 9 100064d7b8beSJerome Glisse #define SI_TILE_MODE_COLOR_2D_8BPP 14 100164d7b8beSJerome Glisse #define SI_TILE_MODE_COLOR_2D_16BPP 15 100264d7b8beSJerome Glisse #define SI_TILE_MODE_COLOR_2D_32BPP 16 100364d7b8beSJerome Glisse #define SI_TILE_MODE_COLOR_2D_64BPP 17 100464d7b8beSJerome Glisse #define SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP 11 100564d7b8beSJerome Glisse #define SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP 12 100664d7b8beSJerome Glisse #define SI_TILE_MODE_DEPTH_STENCIL_1D 4 100764d7b8beSJerome Glisse #define SI_TILE_MODE_DEPTH_STENCIL_2D 0 100864d7b8beSJerome Glisse #define SI_TILE_MODE_DEPTH_STENCIL_2D_2AA 3 100964d7b8beSJerome Glisse #define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA 3 101064d7b8beSJerome Glisse #define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA 2 101164d7b8beSJerome Glisse 101242baf21dSMichel Dänzer #define CIK_TILE_MODE_DEPTH_STENCIL_1D 5 101342baf21dSMichel Dänzer 1014718dceddSDavid Howells #endif 1015