1*c501ca23SJeffrey Hugo /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note 2*c501ca23SJeffrey Hugo * 3*c501ca23SJeffrey Hugo * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. 4*c501ca23SJeffrey Hugo * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 5*c501ca23SJeffrey Hugo */ 6*c501ca23SJeffrey Hugo 7*c501ca23SJeffrey Hugo #ifndef QAIC_ACCEL_H_ 8*c501ca23SJeffrey Hugo #define QAIC_ACCEL_H_ 9*c501ca23SJeffrey Hugo 10*c501ca23SJeffrey Hugo #include "drm.h" 11*c501ca23SJeffrey Hugo 12*c501ca23SJeffrey Hugo #if defined(__cplusplus) 13*c501ca23SJeffrey Hugo extern "C" { 14*c501ca23SJeffrey Hugo #endif 15*c501ca23SJeffrey Hugo 16*c501ca23SJeffrey Hugo /* The length(4K) includes len and count fields of qaic_manage_msg */ 17*c501ca23SJeffrey Hugo #define QAIC_MANAGE_MAX_MSG_LENGTH SZ_4K 18*c501ca23SJeffrey Hugo 19*c501ca23SJeffrey Hugo /* semaphore flags */ 20*c501ca23SJeffrey Hugo #define QAIC_SEM_INSYNCFENCE 2 21*c501ca23SJeffrey Hugo #define QAIC_SEM_OUTSYNCFENCE 1 22*c501ca23SJeffrey Hugo 23*c501ca23SJeffrey Hugo /* Semaphore commands */ 24*c501ca23SJeffrey Hugo #define QAIC_SEM_NOP 0 25*c501ca23SJeffrey Hugo #define QAIC_SEM_INIT 1 26*c501ca23SJeffrey Hugo #define QAIC_SEM_INC 2 27*c501ca23SJeffrey Hugo #define QAIC_SEM_DEC 3 28*c501ca23SJeffrey Hugo #define QAIC_SEM_WAIT_EQUAL 4 29*c501ca23SJeffrey Hugo #define QAIC_SEM_WAIT_GT_EQ 5 /* Greater than or equal */ 30*c501ca23SJeffrey Hugo #define QAIC_SEM_WAIT_GT_0 6 /* Greater than 0 */ 31*c501ca23SJeffrey Hugo 32*c501ca23SJeffrey Hugo #define QAIC_TRANS_UNDEFINED 0 33*c501ca23SJeffrey Hugo #define QAIC_TRANS_PASSTHROUGH_FROM_USR 1 34*c501ca23SJeffrey Hugo #define QAIC_TRANS_PASSTHROUGH_TO_USR 2 35*c501ca23SJeffrey Hugo #define QAIC_TRANS_PASSTHROUGH_FROM_DEV 3 36*c501ca23SJeffrey Hugo #define QAIC_TRANS_PASSTHROUGH_TO_DEV 4 37*c501ca23SJeffrey Hugo #define QAIC_TRANS_DMA_XFER_FROM_USR 5 38*c501ca23SJeffrey Hugo #define QAIC_TRANS_DMA_XFER_TO_DEV 6 39*c501ca23SJeffrey Hugo #define QAIC_TRANS_ACTIVATE_FROM_USR 7 40*c501ca23SJeffrey Hugo #define QAIC_TRANS_ACTIVATE_FROM_DEV 8 41*c501ca23SJeffrey Hugo #define QAIC_TRANS_ACTIVATE_TO_DEV 9 42*c501ca23SJeffrey Hugo #define QAIC_TRANS_DEACTIVATE_FROM_USR 10 43*c501ca23SJeffrey Hugo #define QAIC_TRANS_DEACTIVATE_FROM_DEV 11 44*c501ca23SJeffrey Hugo #define QAIC_TRANS_STATUS_FROM_USR 12 45*c501ca23SJeffrey Hugo #define QAIC_TRANS_STATUS_TO_USR 13 46*c501ca23SJeffrey Hugo #define QAIC_TRANS_STATUS_FROM_DEV 14 47*c501ca23SJeffrey Hugo #define QAIC_TRANS_STATUS_TO_DEV 15 48*c501ca23SJeffrey Hugo #define QAIC_TRANS_TERMINATE_FROM_DEV 16 49*c501ca23SJeffrey Hugo #define QAIC_TRANS_TERMINATE_TO_DEV 17 50*c501ca23SJeffrey Hugo #define QAIC_TRANS_DMA_XFER_CONT 18 51*c501ca23SJeffrey Hugo #define QAIC_TRANS_VALIDATE_PARTITION_FROM_DEV 19 52*c501ca23SJeffrey Hugo #define QAIC_TRANS_VALIDATE_PARTITION_TO_DEV 20 53*c501ca23SJeffrey Hugo 54*c501ca23SJeffrey Hugo /** 55*c501ca23SJeffrey Hugo * struct qaic_manage_trans_hdr - Header for a transaction in a manage message. 56*c501ca23SJeffrey Hugo * @type: In. Identifies this transaction. See QAIC_TRANS_* defines. 57*c501ca23SJeffrey Hugo * @len: In. Length of this transaction, including this header. 58*c501ca23SJeffrey Hugo */ 59*c501ca23SJeffrey Hugo struct qaic_manage_trans_hdr { 60*c501ca23SJeffrey Hugo __u32 type; 61*c501ca23SJeffrey Hugo __u32 len; 62*c501ca23SJeffrey Hugo }; 63*c501ca23SJeffrey Hugo 64*c501ca23SJeffrey Hugo /** 65*c501ca23SJeffrey Hugo * struct qaic_manage_trans_passthrough - Defines a passthrough transaction. 66*c501ca23SJeffrey Hugo * @hdr: In. Header to identify this transaction. 67*c501ca23SJeffrey Hugo * @data: In. Payload of this ransaction. Opaque to the driver. Userspace must 68*c501ca23SJeffrey Hugo * encode in little endian and align/pad to 64-bit. 69*c501ca23SJeffrey Hugo */ 70*c501ca23SJeffrey Hugo struct qaic_manage_trans_passthrough { 71*c501ca23SJeffrey Hugo struct qaic_manage_trans_hdr hdr; 72*c501ca23SJeffrey Hugo __u8 data[]; 73*c501ca23SJeffrey Hugo }; 74*c501ca23SJeffrey Hugo 75*c501ca23SJeffrey Hugo /** 76*c501ca23SJeffrey Hugo * struct qaic_manage_trans_dma_xfer - Defines a DMA transfer transaction. 77*c501ca23SJeffrey Hugo * @hdr: In. Header to identify this transaction. 78*c501ca23SJeffrey Hugo * @tag: In. Identified this transfer in other transactions. Opaque to the 79*c501ca23SJeffrey Hugo * driver. 80*c501ca23SJeffrey Hugo * @pad: Structure padding. 81*c501ca23SJeffrey Hugo * @addr: In. Address of the data to DMA to the device. 82*c501ca23SJeffrey Hugo * @size: In. Length of the data to DMA to the device. 83*c501ca23SJeffrey Hugo */ 84*c501ca23SJeffrey Hugo struct qaic_manage_trans_dma_xfer { 85*c501ca23SJeffrey Hugo struct qaic_manage_trans_hdr hdr; 86*c501ca23SJeffrey Hugo __u32 tag; 87*c501ca23SJeffrey Hugo __u32 pad; 88*c501ca23SJeffrey Hugo __u64 addr; 89*c501ca23SJeffrey Hugo __u64 size; 90*c501ca23SJeffrey Hugo }; 91*c501ca23SJeffrey Hugo 92*c501ca23SJeffrey Hugo /** 93*c501ca23SJeffrey Hugo * struct qaic_manage_trans_activate_to_dev - Defines an activate request. 94*c501ca23SJeffrey Hugo * @hdr: In. Header to identify this transaction. 95*c501ca23SJeffrey Hugo * @queue_size: In. Number of elements for DBC request and response queues. 96*c501ca23SJeffrey Hugo * @eventfd: Unused. 97*c501ca23SJeffrey Hugo * @options: In. Device specific options for this activate. 98*c501ca23SJeffrey Hugo * @pad: Structure padding. Must be 0. 99*c501ca23SJeffrey Hugo */ 100*c501ca23SJeffrey Hugo struct qaic_manage_trans_activate_to_dev { 101*c501ca23SJeffrey Hugo struct qaic_manage_trans_hdr hdr; 102*c501ca23SJeffrey Hugo __u32 queue_size; 103*c501ca23SJeffrey Hugo __u32 eventfd; 104*c501ca23SJeffrey Hugo __u32 options; 105*c501ca23SJeffrey Hugo __u32 pad; 106*c501ca23SJeffrey Hugo }; 107*c501ca23SJeffrey Hugo 108*c501ca23SJeffrey Hugo /** 109*c501ca23SJeffrey Hugo * struct qaic_manage_trans_activate_from_dev - Defines an activate response. 110*c501ca23SJeffrey Hugo * @hdr: Out. Header to identify this transaction. 111*c501ca23SJeffrey Hugo * @status: Out. Return code of the request from the device. 112*c501ca23SJeffrey Hugo * @dbc_id: Out. Id of the assigned DBC for successful request. 113*c501ca23SJeffrey Hugo * @options: Out. Device specific options for this activate. 114*c501ca23SJeffrey Hugo */ 115*c501ca23SJeffrey Hugo struct qaic_manage_trans_activate_from_dev { 116*c501ca23SJeffrey Hugo struct qaic_manage_trans_hdr hdr; 117*c501ca23SJeffrey Hugo __u32 status; 118*c501ca23SJeffrey Hugo __u32 dbc_id; 119*c501ca23SJeffrey Hugo __u64 options; 120*c501ca23SJeffrey Hugo }; 121*c501ca23SJeffrey Hugo 122*c501ca23SJeffrey Hugo /** 123*c501ca23SJeffrey Hugo * struct qaic_manage_trans_deactivate - Defines a deactivate request. 124*c501ca23SJeffrey Hugo * @hdr: In. Header to identify this transaction. 125*c501ca23SJeffrey Hugo * @dbc_id: In. Id of assigned DBC. 126*c501ca23SJeffrey Hugo * @pad: Structure padding. Must be 0. 127*c501ca23SJeffrey Hugo */ 128*c501ca23SJeffrey Hugo struct qaic_manage_trans_deactivate { 129*c501ca23SJeffrey Hugo struct qaic_manage_trans_hdr hdr; 130*c501ca23SJeffrey Hugo __u32 dbc_id; 131*c501ca23SJeffrey Hugo __u32 pad; 132*c501ca23SJeffrey Hugo }; 133*c501ca23SJeffrey Hugo 134*c501ca23SJeffrey Hugo /** 135*c501ca23SJeffrey Hugo * struct qaic_manage_trans_status_to_dev - Defines a status request. 136*c501ca23SJeffrey Hugo * @hdr: In. Header to identify this transaction. 137*c501ca23SJeffrey Hugo */ 138*c501ca23SJeffrey Hugo struct qaic_manage_trans_status_to_dev { 139*c501ca23SJeffrey Hugo struct qaic_manage_trans_hdr hdr; 140*c501ca23SJeffrey Hugo }; 141*c501ca23SJeffrey Hugo 142*c501ca23SJeffrey Hugo /** 143*c501ca23SJeffrey Hugo * struct qaic_manage_trans_status_from_dev - Defines a status response. 144*c501ca23SJeffrey Hugo * @hdr: Out. Header to identify this transaction. 145*c501ca23SJeffrey Hugo * @major: Out. NNC protocol version major number. 146*c501ca23SJeffrey Hugo * @minor: Out. NNC protocol version minor number. 147*c501ca23SJeffrey Hugo * @status: Out. Return code from device. 148*c501ca23SJeffrey Hugo * @status_flags: Out. Flags from device. Bit 0 indicates if CRCs are required. 149*c501ca23SJeffrey Hugo */ 150*c501ca23SJeffrey Hugo struct qaic_manage_trans_status_from_dev { 151*c501ca23SJeffrey Hugo struct qaic_manage_trans_hdr hdr; 152*c501ca23SJeffrey Hugo __u16 major; 153*c501ca23SJeffrey Hugo __u16 minor; 154*c501ca23SJeffrey Hugo __u32 status; 155*c501ca23SJeffrey Hugo __u64 status_flags; 156*c501ca23SJeffrey Hugo }; 157*c501ca23SJeffrey Hugo 158*c501ca23SJeffrey Hugo /** 159*c501ca23SJeffrey Hugo * struct qaic_manage_msg - Defines a message to the device. 160*c501ca23SJeffrey Hugo * @len: In. Length of all the transactions contained within this message. 161*c501ca23SJeffrey Hugo * @count: In. Number of transactions in this message. 162*c501ca23SJeffrey Hugo * @data: In. Address to an array where the transactions can be found. 163*c501ca23SJeffrey Hugo */ 164*c501ca23SJeffrey Hugo struct qaic_manage_msg { 165*c501ca23SJeffrey Hugo __u32 len; 166*c501ca23SJeffrey Hugo __u32 count; 167*c501ca23SJeffrey Hugo __u64 data; 168*c501ca23SJeffrey Hugo }; 169*c501ca23SJeffrey Hugo 170*c501ca23SJeffrey Hugo /** 171*c501ca23SJeffrey Hugo * struct qaic_create_bo - Defines a request to create a buffer object. 172*c501ca23SJeffrey Hugo * @size: In. Size of the buffer in bytes. 173*c501ca23SJeffrey Hugo * @handle: Out. GEM handle for the BO. 174*c501ca23SJeffrey Hugo * @pad: Structure padding. Must be 0. 175*c501ca23SJeffrey Hugo */ 176*c501ca23SJeffrey Hugo struct qaic_create_bo { 177*c501ca23SJeffrey Hugo __u64 size; 178*c501ca23SJeffrey Hugo __u32 handle; 179*c501ca23SJeffrey Hugo __u32 pad; 180*c501ca23SJeffrey Hugo }; 181*c501ca23SJeffrey Hugo 182*c501ca23SJeffrey Hugo /** 183*c501ca23SJeffrey Hugo * struct qaic_mmap_bo - Defines a request to prepare a BO for mmap(). 184*c501ca23SJeffrey Hugo * @handle: In. Handle of the GEM BO to prepare for mmap(). 185*c501ca23SJeffrey Hugo * @pad: Structure padding. Must be 0. 186*c501ca23SJeffrey Hugo * @offset: Out. Offset value to provide to mmap(). 187*c501ca23SJeffrey Hugo */ 188*c501ca23SJeffrey Hugo struct qaic_mmap_bo { 189*c501ca23SJeffrey Hugo __u32 handle; 190*c501ca23SJeffrey Hugo __u32 pad; 191*c501ca23SJeffrey Hugo __u64 offset; 192*c501ca23SJeffrey Hugo }; 193*c501ca23SJeffrey Hugo 194*c501ca23SJeffrey Hugo /** 195*c501ca23SJeffrey Hugo * struct qaic_sem - Defines a semaphore command for a BO slice. 196*c501ca23SJeffrey Hugo * @val: In. Only lower 12 bits are valid. 197*c501ca23SJeffrey Hugo * @index: In. Only lower 5 bits are valid. 198*c501ca23SJeffrey Hugo * @presync: In. 1 if presync operation, 0 if postsync. 199*c501ca23SJeffrey Hugo * @cmd: In. One of QAIC_SEM_*. 200*c501ca23SJeffrey Hugo * @flags: In. Bitfield. See QAIC_SEM_INSYNCFENCE and QAIC_SEM_OUTSYNCFENCE 201*c501ca23SJeffrey Hugo * @pad: Structure padding. Must be 0. 202*c501ca23SJeffrey Hugo */ 203*c501ca23SJeffrey Hugo struct qaic_sem { 204*c501ca23SJeffrey Hugo __u16 val; 205*c501ca23SJeffrey Hugo __u8 index; 206*c501ca23SJeffrey Hugo __u8 presync; 207*c501ca23SJeffrey Hugo __u8 cmd; 208*c501ca23SJeffrey Hugo __u8 flags; 209*c501ca23SJeffrey Hugo __u16 pad; 210*c501ca23SJeffrey Hugo }; 211*c501ca23SJeffrey Hugo 212*c501ca23SJeffrey Hugo /** 213*c501ca23SJeffrey Hugo * struct qaic_attach_slice_entry - Defines a single BO slice. 214*c501ca23SJeffrey Hugo * @size: In. Size of this slice in bytes. 215*c501ca23SJeffrey Hugo * @sem0: In. Semaphore command 0. Must be 0 is not valid. 216*c501ca23SJeffrey Hugo * @sem1: In. Semaphore command 1. Must be 0 is not valid. 217*c501ca23SJeffrey Hugo * @sem2: In. Semaphore command 2. Must be 0 is not valid. 218*c501ca23SJeffrey Hugo * @sem3: In. Semaphore command 3. Must be 0 is not valid. 219*c501ca23SJeffrey Hugo * @dev_addr: In. Device address this slice pushes to or pulls from. 220*c501ca23SJeffrey Hugo * @db_addr: In. Address of the doorbell to ring. 221*c501ca23SJeffrey Hugo * @db_data: In. Data to write to the doorbell. 222*c501ca23SJeffrey Hugo * @db_len: In. Size of the doorbell data in bits - 32, 16, or 8. 0 is for 223*c501ca23SJeffrey Hugo * inactive doorbells. 224*c501ca23SJeffrey Hugo * @offset: In. Start of this slice as an offset from the start of the BO. 225*c501ca23SJeffrey Hugo */ 226*c501ca23SJeffrey Hugo struct qaic_attach_slice_entry { 227*c501ca23SJeffrey Hugo __u64 size; 228*c501ca23SJeffrey Hugo struct qaic_sem sem0; 229*c501ca23SJeffrey Hugo struct qaic_sem sem1; 230*c501ca23SJeffrey Hugo struct qaic_sem sem2; 231*c501ca23SJeffrey Hugo struct qaic_sem sem3; 232*c501ca23SJeffrey Hugo __u64 dev_addr; 233*c501ca23SJeffrey Hugo __u64 db_addr; 234*c501ca23SJeffrey Hugo __u32 db_data; 235*c501ca23SJeffrey Hugo __u32 db_len; 236*c501ca23SJeffrey Hugo __u64 offset; 237*c501ca23SJeffrey Hugo }; 238*c501ca23SJeffrey Hugo 239*c501ca23SJeffrey Hugo /** 240*c501ca23SJeffrey Hugo * struct qaic_attach_slice_hdr - Defines metadata for a set of BO slices. 241*c501ca23SJeffrey Hugo * @count: In. Number of slices for this BO. 242*c501ca23SJeffrey Hugo * @dbc_id: In. Associate the sliced BO with this DBC. 243*c501ca23SJeffrey Hugo * @handle: In. GEM handle of the BO to slice. 244*c501ca23SJeffrey Hugo * @dir: In. Direction of data flow. 1 = DMA_TO_DEVICE, 2 = DMA_FROM_DEVICE 245*c501ca23SJeffrey Hugo * @size: In. Total length of the BO. 246*c501ca23SJeffrey Hugo * If BO is imported (DMABUF/PRIME) then this size 247*c501ca23SJeffrey Hugo * should not exceed the size of DMABUF provided. 248*c501ca23SJeffrey Hugo * If BO is allocated using DRM_IOCTL_QAIC_CREATE_BO 249*c501ca23SJeffrey Hugo * then this size should be exactly same as the size 250*c501ca23SJeffrey Hugo * provided during DRM_IOCTL_QAIC_CREATE_BO. 251*c501ca23SJeffrey Hugo * @dev_addr: In. Device address this slice pushes to or pulls from. 252*c501ca23SJeffrey Hugo * @db_addr: In. Address of the doorbell to ring. 253*c501ca23SJeffrey Hugo * @db_data: In. Data to write to the doorbell. 254*c501ca23SJeffrey Hugo * @db_len: In. Size of the doorbell data in bits - 32, 16, or 8. 0 is for 255*c501ca23SJeffrey Hugo * inactive doorbells. 256*c501ca23SJeffrey Hugo * @offset: In. Start of this slice as an offset from the start of the BO. 257*c501ca23SJeffrey Hugo */ 258*c501ca23SJeffrey Hugo struct qaic_attach_slice_hdr { 259*c501ca23SJeffrey Hugo __u32 count; 260*c501ca23SJeffrey Hugo __u32 dbc_id; 261*c501ca23SJeffrey Hugo __u32 handle; 262*c501ca23SJeffrey Hugo __u32 dir; 263*c501ca23SJeffrey Hugo __u64 size; 264*c501ca23SJeffrey Hugo }; 265*c501ca23SJeffrey Hugo 266*c501ca23SJeffrey Hugo /** 267*c501ca23SJeffrey Hugo * struct qaic_attach_slice - Defines a set of BO slices. 268*c501ca23SJeffrey Hugo * @hdr: In. Metadata of the set of slices. 269*c501ca23SJeffrey Hugo * @data: In. Pointer to an array containing the slice definitions. 270*c501ca23SJeffrey Hugo */ 271*c501ca23SJeffrey Hugo struct qaic_attach_slice { 272*c501ca23SJeffrey Hugo struct qaic_attach_slice_hdr hdr; 273*c501ca23SJeffrey Hugo __u64 data; 274*c501ca23SJeffrey Hugo }; 275*c501ca23SJeffrey Hugo 276*c501ca23SJeffrey Hugo /** 277*c501ca23SJeffrey Hugo * struct qaic_execute_entry - Defines a BO to submit to the device. 278*c501ca23SJeffrey Hugo * @handle: In. GEM handle of the BO to commit to the device. 279*c501ca23SJeffrey Hugo * @dir: In. Direction of data. 1 = to device, 2 = from device. 280*c501ca23SJeffrey Hugo */ 281*c501ca23SJeffrey Hugo struct qaic_execute_entry { 282*c501ca23SJeffrey Hugo __u32 handle; 283*c501ca23SJeffrey Hugo __u32 dir; 284*c501ca23SJeffrey Hugo }; 285*c501ca23SJeffrey Hugo 286*c501ca23SJeffrey Hugo /** 287*c501ca23SJeffrey Hugo * struct qaic_partial_execute_entry - Defines a BO to resize and submit. 288*c501ca23SJeffrey Hugo * @handle: In. GEM handle of the BO to commit to the device. 289*c501ca23SJeffrey Hugo * @dir: In. Direction of data. 1 = to device, 2 = from device. 290*c501ca23SJeffrey Hugo * @resize: In. New size of the BO. Must be <= the original BO size. 0 is 291*c501ca23SJeffrey Hugo * short for no resize. 292*c501ca23SJeffrey Hugo */ 293*c501ca23SJeffrey Hugo struct qaic_partial_execute_entry { 294*c501ca23SJeffrey Hugo __u32 handle; 295*c501ca23SJeffrey Hugo __u32 dir; 296*c501ca23SJeffrey Hugo __u64 resize; 297*c501ca23SJeffrey Hugo }; 298*c501ca23SJeffrey Hugo 299*c501ca23SJeffrey Hugo /** 300*c501ca23SJeffrey Hugo * struct qaic_execute_hdr - Defines metadata for BO submission. 301*c501ca23SJeffrey Hugo * @count: In. Number of BOs to submit. 302*c501ca23SJeffrey Hugo * @dbc_id: In. DBC to submit the BOs on. 303*c501ca23SJeffrey Hugo */ 304*c501ca23SJeffrey Hugo struct qaic_execute_hdr { 305*c501ca23SJeffrey Hugo __u32 count; 306*c501ca23SJeffrey Hugo __u32 dbc_id; 307*c501ca23SJeffrey Hugo }; 308*c501ca23SJeffrey Hugo 309*c501ca23SJeffrey Hugo /** 310*c501ca23SJeffrey Hugo * struct qaic_execute - Defines a list of BOs to submit to the device. 311*c501ca23SJeffrey Hugo * @hdr: In. BO list metadata. 312*c501ca23SJeffrey Hugo * @data: In. Pointer to an array of BOs to submit. 313*c501ca23SJeffrey Hugo */ 314*c501ca23SJeffrey Hugo struct qaic_execute { 315*c501ca23SJeffrey Hugo struct qaic_execute_hdr hdr; 316*c501ca23SJeffrey Hugo __u64 data; 317*c501ca23SJeffrey Hugo }; 318*c501ca23SJeffrey Hugo 319*c501ca23SJeffrey Hugo /** 320*c501ca23SJeffrey Hugo * struct qaic_wait - Defines a blocking wait for BO execution. 321*c501ca23SJeffrey Hugo * @handle: In. GEM handle of the BO to wait on. 322*c501ca23SJeffrey Hugo * @timeout: In. Maximum time in ms to wait for the BO. 323*c501ca23SJeffrey Hugo * @dbc_id: In. DBC the BO is submitted to. 324*c501ca23SJeffrey Hugo * @pad: Structure padding. Must be 0. 325*c501ca23SJeffrey Hugo */ 326*c501ca23SJeffrey Hugo struct qaic_wait { 327*c501ca23SJeffrey Hugo __u32 handle; 328*c501ca23SJeffrey Hugo __u32 timeout; 329*c501ca23SJeffrey Hugo __u32 dbc_id; 330*c501ca23SJeffrey Hugo __u32 pad; 331*c501ca23SJeffrey Hugo }; 332*c501ca23SJeffrey Hugo 333*c501ca23SJeffrey Hugo /** 334*c501ca23SJeffrey Hugo * struct qaic_perf_stats_hdr - Defines metadata for getting BO perf info. 335*c501ca23SJeffrey Hugo * @count: In. Number of BOs requested. 336*c501ca23SJeffrey Hugo * @pad: Structure padding. Must be 0. 337*c501ca23SJeffrey Hugo * @dbc_id: In. DBC the BO are associated with. 338*c501ca23SJeffrey Hugo */ 339*c501ca23SJeffrey Hugo struct qaic_perf_stats_hdr { 340*c501ca23SJeffrey Hugo __u16 count; 341*c501ca23SJeffrey Hugo __u16 pad; 342*c501ca23SJeffrey Hugo __u32 dbc_id; 343*c501ca23SJeffrey Hugo }; 344*c501ca23SJeffrey Hugo 345*c501ca23SJeffrey Hugo /** 346*c501ca23SJeffrey Hugo * struct qaic_perf_stats - Defines a request for getting BO perf info. 347*c501ca23SJeffrey Hugo * @hdr: In. Request metadata 348*c501ca23SJeffrey Hugo * @data: In. Pointer to array of stats structures that will receive the data. 349*c501ca23SJeffrey Hugo */ 350*c501ca23SJeffrey Hugo struct qaic_perf_stats { 351*c501ca23SJeffrey Hugo struct qaic_perf_stats_hdr hdr; 352*c501ca23SJeffrey Hugo __u64 data; 353*c501ca23SJeffrey Hugo }; 354*c501ca23SJeffrey Hugo 355*c501ca23SJeffrey Hugo /** 356*c501ca23SJeffrey Hugo * struct qaic_perf_stats_entry - Defines a BO perf info. 357*c501ca23SJeffrey Hugo * @handle: In. GEM handle of the BO to get perf stats for. 358*c501ca23SJeffrey Hugo * @queue_level_before: Out. Number of elements in the queue before this BO 359*c501ca23SJeffrey Hugo * was submitted. 360*c501ca23SJeffrey Hugo * @num_queue_element: Out. Number of elements added to the queue to submit 361*c501ca23SJeffrey Hugo * this BO. 362*c501ca23SJeffrey Hugo * @submit_latency_us: Out. Time taken by the driver to submit this BO. 363*c501ca23SJeffrey Hugo * @device_latency_us: Out. Time taken by the device to execute this BO. 364*c501ca23SJeffrey Hugo * @pad: Structure padding. Must be 0. 365*c501ca23SJeffrey Hugo */ 366*c501ca23SJeffrey Hugo struct qaic_perf_stats_entry { 367*c501ca23SJeffrey Hugo __u32 handle; 368*c501ca23SJeffrey Hugo __u32 queue_level_before; 369*c501ca23SJeffrey Hugo __u32 num_queue_element; 370*c501ca23SJeffrey Hugo __u32 submit_latency_us; 371*c501ca23SJeffrey Hugo __u32 device_latency_us; 372*c501ca23SJeffrey Hugo __u32 pad; 373*c501ca23SJeffrey Hugo }; 374*c501ca23SJeffrey Hugo 375*c501ca23SJeffrey Hugo #define DRM_QAIC_MANAGE 0x00 376*c501ca23SJeffrey Hugo #define DRM_QAIC_CREATE_BO 0x01 377*c501ca23SJeffrey Hugo #define DRM_QAIC_MMAP_BO 0x02 378*c501ca23SJeffrey Hugo #define DRM_QAIC_ATTACH_SLICE_BO 0x03 379*c501ca23SJeffrey Hugo #define DRM_QAIC_EXECUTE_BO 0x04 380*c501ca23SJeffrey Hugo #define DRM_QAIC_PARTIAL_EXECUTE_BO 0x05 381*c501ca23SJeffrey Hugo #define DRM_QAIC_WAIT_BO 0x06 382*c501ca23SJeffrey Hugo #define DRM_QAIC_PERF_STATS_BO 0x07 383*c501ca23SJeffrey Hugo 384*c501ca23SJeffrey Hugo #define DRM_IOCTL_QAIC_MANAGE DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_MANAGE, struct qaic_manage_msg) 385*c501ca23SJeffrey Hugo #define DRM_IOCTL_QAIC_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_CREATE_BO, struct qaic_create_bo) 386*c501ca23SJeffrey Hugo #define DRM_IOCTL_QAIC_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_MMAP_BO, struct qaic_mmap_bo) 387*c501ca23SJeffrey Hugo #define DRM_IOCTL_QAIC_ATTACH_SLICE_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_ATTACH_SLICE_BO, struct qaic_attach_slice) 388*c501ca23SJeffrey Hugo #define DRM_IOCTL_QAIC_EXECUTE_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_EXECUTE_BO, struct qaic_execute) 389*c501ca23SJeffrey Hugo #define DRM_IOCTL_QAIC_PARTIAL_EXECUTE_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_PARTIAL_EXECUTE_BO, struct qaic_execute) 390*c501ca23SJeffrey Hugo #define DRM_IOCTL_QAIC_WAIT_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_WAIT_BO, struct qaic_wait) 391*c501ca23SJeffrey Hugo #define DRM_IOCTL_QAIC_PERF_STATS_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_PERF_STATS_BO, struct qaic_perf_stats) 392*c501ca23SJeffrey Hugo 393*c501ca23SJeffrey Hugo #if defined(__cplusplus) 394*c501ca23SJeffrey Hugo } 395*c501ca23SJeffrey Hugo #endif 396*c501ca23SJeffrey Hugo 397*c501ca23SJeffrey Hugo #endif /* QAIC_ACCEL_H_ */ 398