1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2014-2018 Broadcom 4 * Copyright © 2019 Collabora ltd. 5 */ 6 #ifndef _PANFROST_DRM_H_ 7 #define _PANFROST_DRM_H_ 8 9 #include "drm.h" 10 11 #if defined(__cplusplus) 12 extern "C" { 13 #endif 14 15 #define DRM_PANFROST_SUBMIT 0x00 16 #define DRM_PANFROST_WAIT_BO 0x01 17 #define DRM_PANFROST_CREATE_BO 0x02 18 #define DRM_PANFROST_MMAP_BO 0x03 19 #define DRM_PANFROST_GET_PARAM 0x04 20 #define DRM_PANFROST_GET_BO_OFFSET 0x05 21 #define DRM_PANFROST_PERFCNT_ENABLE 0x06 22 #define DRM_PANFROST_PERFCNT_DUMP 0x07 23 24 #define DRM_IOCTL_PANFROST_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_SUBMIT, struct drm_panfrost_submit) 25 #define DRM_IOCTL_PANFROST_WAIT_BO DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_WAIT_BO, struct drm_panfrost_wait_bo) 26 #define DRM_IOCTL_PANFROST_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_CREATE_BO, struct drm_panfrost_create_bo) 27 #define DRM_IOCTL_PANFROST_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_MMAP_BO, struct drm_panfrost_mmap_bo) 28 #define DRM_IOCTL_PANFROST_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_GET_PARAM, struct drm_panfrost_get_param) 29 #define DRM_IOCTL_PANFROST_GET_BO_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_GET_BO_OFFSET, struct drm_panfrost_get_bo_offset) 30 31 /* 32 * Unstable ioctl(s): only exposed when the unsafe unstable_ioctls module 33 * param is set to true. 34 * All these ioctl(s) are subject to deprecation, so please don't rely on 35 * them for anything but debugging purpose. 36 */ 37 #define DRM_IOCTL_PANFROST_PERFCNT_ENABLE DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_PERFCNT_ENABLE, struct drm_panfrost_perfcnt_enable) 38 #define DRM_IOCTL_PANFROST_PERFCNT_DUMP DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_PERFCNT_DUMP, struct drm_panfrost_perfcnt_dump) 39 40 #define PANFROST_JD_REQ_FS (1 << 0) 41 /** 42 * struct drm_panfrost_submit - ioctl argument for submitting commands to the 3D 43 * engine. 44 * 45 * This asks the kernel to have the GPU execute a render command list. 46 */ 47 struct drm_panfrost_submit { 48 49 /** Address to GPU mapping of job descriptor */ 50 __u64 jc; 51 52 /** An optional array of sync objects to wait on before starting this job. */ 53 __u64 in_syncs; 54 55 /** Number of sync objects to wait on before starting this job. */ 56 __u32 in_sync_count; 57 58 /** An optional sync object to place the completion fence in. */ 59 __u32 out_sync; 60 61 /** Pointer to a u32 array of the BOs that are referenced by the job. */ 62 __u64 bo_handles; 63 64 /** Number of BO handles passed in (size is that times 4). */ 65 __u32 bo_handle_count; 66 67 /** A combination of PANFROST_JD_REQ_* */ 68 __u32 requirements; 69 }; 70 71 /** 72 * struct drm_panfrost_wait_bo - ioctl argument for waiting for 73 * completion of the last DRM_PANFROST_SUBMIT on a BO. 74 * 75 * This is useful for cases where multiple processes might be 76 * rendering to a BO and you want to wait for all rendering to be 77 * completed. 78 */ 79 struct drm_panfrost_wait_bo { 80 __u32 handle; 81 __u32 pad; 82 __s64 timeout_ns; /* absolute */ 83 }; 84 85 /** 86 * struct drm_panfrost_create_bo - ioctl argument for creating Panfrost BOs. 87 * 88 * There are currently no values for the flags argument, but it may be 89 * used in a future extension. 90 */ 91 struct drm_panfrost_create_bo { 92 __u32 size; 93 __u32 flags; 94 /** Returned GEM handle for the BO. */ 95 __u32 handle; 96 /* Pad, must be zero-filled. */ 97 __u32 pad; 98 /** 99 * Returned offset for the BO in the GPU address space. This offset 100 * is private to the DRM fd and is valid for the lifetime of the GEM 101 * handle. 102 * 103 * This offset value will always be nonzero, since various HW 104 * units treat 0 specially. 105 */ 106 __u64 offset; 107 }; 108 109 /** 110 * struct drm_panfrost_mmap_bo - ioctl argument for mapping Panfrost BOs. 111 * 112 * This doesn't actually perform an mmap. Instead, it returns the 113 * offset you need to use in an mmap on the DRM device node. This 114 * means that tools like valgrind end up knowing about the mapped 115 * memory. 116 * 117 * There are currently no values for the flags argument, but it may be 118 * used in a future extension. 119 */ 120 struct drm_panfrost_mmap_bo { 121 /** Handle for the object being mapped. */ 122 __u32 handle; 123 __u32 flags; 124 /** offset into the drm node to use for subsequent mmap call. */ 125 __u64 offset; 126 }; 127 128 enum drm_panfrost_param { 129 DRM_PANFROST_PARAM_GPU_PROD_ID, 130 DRM_PANFROST_PARAM_GPU_REVISION, 131 DRM_PANFROST_PARAM_SHADER_PRESENT, 132 DRM_PANFROST_PARAM_TILER_PRESENT, 133 DRM_PANFROST_PARAM_L2_PRESENT, 134 DRM_PANFROST_PARAM_STACK_PRESENT, 135 DRM_PANFROST_PARAM_AS_PRESENT, 136 DRM_PANFROST_PARAM_JS_PRESENT, 137 DRM_PANFROST_PARAM_L2_FEATURES, 138 DRM_PANFROST_PARAM_CORE_FEATURES, 139 DRM_PANFROST_PARAM_TILER_FEATURES, 140 DRM_PANFROST_PARAM_MEM_FEATURES, 141 DRM_PANFROST_PARAM_MMU_FEATURES, 142 DRM_PANFROST_PARAM_THREAD_FEATURES, 143 DRM_PANFROST_PARAM_MAX_THREADS, 144 DRM_PANFROST_PARAM_THREAD_MAX_WORKGROUP_SZ, 145 DRM_PANFROST_PARAM_THREAD_MAX_BARRIER_SZ, 146 DRM_PANFROST_PARAM_COHERENCY_FEATURES, 147 DRM_PANFROST_PARAM_TEXTURE_FEATURES0, 148 DRM_PANFROST_PARAM_TEXTURE_FEATURES1, 149 DRM_PANFROST_PARAM_TEXTURE_FEATURES2, 150 DRM_PANFROST_PARAM_TEXTURE_FEATURES3, 151 DRM_PANFROST_PARAM_JS_FEATURES0, 152 DRM_PANFROST_PARAM_JS_FEATURES1, 153 DRM_PANFROST_PARAM_JS_FEATURES2, 154 DRM_PANFROST_PARAM_JS_FEATURES3, 155 DRM_PANFROST_PARAM_JS_FEATURES4, 156 DRM_PANFROST_PARAM_JS_FEATURES5, 157 DRM_PANFROST_PARAM_JS_FEATURES6, 158 DRM_PANFROST_PARAM_JS_FEATURES7, 159 DRM_PANFROST_PARAM_JS_FEATURES8, 160 DRM_PANFROST_PARAM_JS_FEATURES9, 161 DRM_PANFROST_PARAM_JS_FEATURES10, 162 DRM_PANFROST_PARAM_JS_FEATURES11, 163 DRM_PANFROST_PARAM_JS_FEATURES12, 164 DRM_PANFROST_PARAM_JS_FEATURES13, 165 DRM_PANFROST_PARAM_JS_FEATURES14, 166 DRM_PANFROST_PARAM_JS_FEATURES15, 167 DRM_PANFROST_PARAM_NR_CORE_GROUPS, 168 DRM_PANFROST_PARAM_THREAD_TLS_ALLOC, 169 }; 170 171 struct drm_panfrost_get_param { 172 __u32 param; 173 __u32 pad; 174 __u64 value; 175 }; 176 177 /** 178 * Returns the offset for the BO in the GPU address space for this DRM fd. 179 * This is the same value returned by drm_panfrost_create_bo, if that was called 180 * from this DRM fd. 181 */ 182 struct drm_panfrost_get_bo_offset { 183 __u32 handle; 184 __u32 pad; 185 __u64 offset; 186 }; 187 188 struct drm_panfrost_perfcnt_enable { 189 __u32 enable; 190 /* 191 * On bifrost we have 2 sets of counters, this parameter defines the 192 * one to track. 193 */ 194 __u32 counterset; 195 }; 196 197 struct drm_panfrost_perfcnt_dump { 198 __u64 buf_ptr; 199 }; 200 201 #if defined(__cplusplus) 202 } 203 #endif 204 205 #endif /* _PANFROST_DRM_H_ */ 206