1 /* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef __NOUVEAU_DRM_H__ 26 #define __NOUVEAU_DRM_H__ 27 28 #define DRM_NOUVEAU_EVENT_NVIF 0x80000000 29 30 #include "drm.h" 31 32 #if defined(__cplusplus) 33 extern "C" { 34 #endif 35 36 #define NOUVEAU_GETPARAM_PCI_VENDOR 3 37 #define NOUVEAU_GETPARAM_PCI_DEVICE 4 38 #define NOUVEAU_GETPARAM_BUS_TYPE 5 39 #define NOUVEAU_GETPARAM_FB_SIZE 8 40 #define NOUVEAU_GETPARAM_AGP_SIZE 9 41 #define NOUVEAU_GETPARAM_CHIPSET_ID 11 42 #define NOUVEAU_GETPARAM_VM_VRAM_BASE 12 43 #define NOUVEAU_GETPARAM_GRAPH_UNITS 13 44 #define NOUVEAU_GETPARAM_PTIMER_TIME 14 45 #define NOUVEAU_GETPARAM_HAS_BO_USAGE 15 46 #define NOUVEAU_GETPARAM_HAS_PAGEFLIP 16 47 struct drm_nouveau_getparam { 48 __u64 param; 49 __u64 value; 50 }; 51 52 struct drm_nouveau_channel_alloc { 53 __u32 fb_ctxdma_handle; 54 __u32 tt_ctxdma_handle; 55 56 __s32 channel; 57 __u32 pushbuf_domains; 58 59 /* Notifier memory */ 60 __u32 notifier_handle; 61 62 /* DRM-enforced subchannel assignments */ 63 struct { 64 __u32 handle; 65 __u32 grclass; 66 } subchan[8]; 67 __u32 nr_subchan; 68 }; 69 70 struct drm_nouveau_channel_free { 71 __s32 channel; 72 }; 73 74 #define NOUVEAU_GEM_DOMAIN_CPU (1 << 0) 75 #define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1) 76 #define NOUVEAU_GEM_DOMAIN_GART (1 << 2) 77 #define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3) 78 #define NOUVEAU_GEM_DOMAIN_COHERENT (1 << 4) 79 /* The BO will never be shared via import or export. */ 80 #define NOUVEAU_GEM_DOMAIN_NO_SHARE (1 << 5) 81 82 #define NOUVEAU_GEM_TILE_COMP 0x00030000 /* nv50-only */ 83 #define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00 84 #define NOUVEAU_GEM_TILE_16BPP 0x00000001 85 #define NOUVEAU_GEM_TILE_32BPP 0x00000002 86 #define NOUVEAU_GEM_TILE_ZETA 0x00000004 87 #define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008 88 89 struct drm_nouveau_gem_info { 90 __u32 handle; 91 __u32 domain; 92 __u64 size; 93 __u64 offset; 94 __u64 map_handle; 95 __u32 tile_mode; 96 __u32 tile_flags; 97 }; 98 99 struct drm_nouveau_gem_new { 100 struct drm_nouveau_gem_info info; 101 __u32 channel_hint; 102 __u32 align; 103 }; 104 105 #define NOUVEAU_GEM_MAX_BUFFERS 1024 106 struct drm_nouveau_gem_pushbuf_bo_presumed { 107 __u32 valid; 108 __u32 domain; 109 __u64 offset; 110 }; 111 112 struct drm_nouveau_gem_pushbuf_bo { 113 __u64 user_priv; 114 __u32 handle; 115 __u32 read_domains; 116 __u32 write_domains; 117 __u32 valid_domains; 118 struct drm_nouveau_gem_pushbuf_bo_presumed presumed; 119 }; 120 121 #define NOUVEAU_GEM_RELOC_LOW (1 << 0) 122 #define NOUVEAU_GEM_RELOC_HIGH (1 << 1) 123 #define NOUVEAU_GEM_RELOC_OR (1 << 2) 124 #define NOUVEAU_GEM_MAX_RELOCS 1024 125 struct drm_nouveau_gem_pushbuf_reloc { 126 __u32 reloc_bo_index; 127 __u32 reloc_bo_offset; 128 __u32 bo_index; 129 __u32 flags; 130 __u32 data; 131 __u32 vor; 132 __u32 tor; 133 }; 134 135 #define NOUVEAU_GEM_MAX_PUSH 512 136 struct drm_nouveau_gem_pushbuf_push { 137 __u32 bo_index; 138 __u32 pad; 139 __u64 offset; 140 __u64 length; 141 }; 142 143 struct drm_nouveau_gem_pushbuf { 144 __u32 channel; 145 __u32 nr_buffers; 146 __u64 buffers; 147 __u32 nr_relocs; 148 __u32 nr_push; 149 __u64 relocs; 150 __u64 push; 151 __u32 suffix0; 152 __u32 suffix1; 153 #define NOUVEAU_GEM_PUSHBUF_SYNC (1ULL << 0) 154 __u64 vram_available; 155 __u64 gart_available; 156 }; 157 158 #define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001 159 #define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004 160 struct drm_nouveau_gem_cpu_prep { 161 __u32 handle; 162 __u32 flags; 163 }; 164 165 struct drm_nouveau_gem_cpu_fini { 166 __u32 handle; 167 }; 168 169 /** 170 * struct drm_nouveau_sync - sync object 171 * 172 * This structure serves as synchronization mechanism for (potentially) 173 * asynchronous operations such as EXEC or VM_BIND. 174 */ 175 struct drm_nouveau_sync { 176 /** 177 * @flags: the flags for a sync object 178 * 179 * The first 8 bits are used to determine the type of the sync object. 180 */ 181 __u32 flags; 182 #define DRM_NOUVEAU_SYNC_SYNCOBJ 0x0 183 #define DRM_NOUVEAU_SYNC_TIMELINE_SYNCOBJ 0x1 184 #define DRM_NOUVEAU_SYNC_TYPE_MASK 0xf 185 /** 186 * @handle: the handle of the sync object 187 */ 188 __u32 handle; 189 /** 190 * @timeline_value: 191 * 192 * The timeline point of the sync object in case the syncobj is of 193 * type DRM_NOUVEAU_SYNC_TIMELINE_SYNCOBJ. 194 */ 195 __u64 timeline_value; 196 }; 197 198 /** 199 * struct drm_nouveau_vm_init - GPU VA space init structure 200 * 201 * Used to initialize the GPU's VA space for a user client, telling the kernel 202 * which portion of the VA space is managed by the UMD and kernel respectively. 203 * 204 * For the UMD to use the VM_BIND uAPI, this must be called before any BOs or 205 * channels are created; if called afterwards DRM_IOCTL_NOUVEAU_VM_INIT fails 206 * with -ENOSYS. 207 */ 208 struct drm_nouveau_vm_init { 209 /** 210 * @kernel_managed_addr: start address of the kernel managed VA space 211 * region 212 */ 213 __u64 kernel_managed_addr; 214 /** 215 * @kernel_managed_size: size of the kernel managed VA space region in 216 * bytes 217 */ 218 __u64 kernel_managed_size; 219 }; 220 221 /** 222 * struct drm_nouveau_vm_bind_op - VM_BIND operation 223 * 224 * This structure represents a single VM_BIND operation. UMDs should pass 225 * an array of this structure via struct drm_nouveau_vm_bind's &op_ptr field. 226 */ 227 struct drm_nouveau_vm_bind_op { 228 /** 229 * @op: the operation type 230 */ 231 __u32 op; 232 /** 233 * @DRM_NOUVEAU_VM_BIND_OP_MAP: 234 * 235 * Map a GEM object to the GPU's VA space. Optionally, the 236 * &DRM_NOUVEAU_VM_BIND_SPARSE flag can be passed to instruct the kernel to 237 * create sparse mappings for the given range. 238 */ 239 #define DRM_NOUVEAU_VM_BIND_OP_MAP 0x0 240 /** 241 * @DRM_NOUVEAU_VM_BIND_OP_UNMAP: 242 * 243 * Unmap an existing mapping in the GPU's VA space. If the region the mapping 244 * is located in is a sparse region, new sparse mappings are created where the 245 * unmapped (memory backed) mapping was mapped previously. To remove a sparse 246 * region the &DRM_NOUVEAU_VM_BIND_SPARSE must be set. 247 */ 248 #define DRM_NOUVEAU_VM_BIND_OP_UNMAP 0x1 249 /** 250 * @flags: the flags for a &drm_nouveau_vm_bind_op 251 */ 252 __u32 flags; 253 /** 254 * @DRM_NOUVEAU_VM_BIND_SPARSE: 255 * 256 * Indicates that an allocated VA space region should be sparse. 257 */ 258 #define DRM_NOUVEAU_VM_BIND_SPARSE (1 << 8) 259 /** 260 * @handle: the handle of the DRM GEM object to map 261 */ 262 __u32 handle; 263 /** 264 * @pad: 32 bit padding, should be 0 265 */ 266 __u32 pad; 267 /** 268 * @addr: 269 * 270 * the address the VA space region or (memory backed) mapping should be mapped to 271 */ 272 __u64 addr; 273 /** 274 * @bo_offset: the offset within the BO backing the mapping 275 */ 276 __u64 bo_offset; 277 /** 278 * @range: the size of the requested mapping in bytes 279 */ 280 __u64 range; 281 }; 282 283 /** 284 * struct drm_nouveau_vm_bind - structure for DRM_IOCTL_NOUVEAU_VM_BIND 285 */ 286 struct drm_nouveau_vm_bind { 287 /** 288 * @op_count: the number of &drm_nouveau_vm_bind_op 289 */ 290 __u32 op_count; 291 /** 292 * @flags: the flags for a &drm_nouveau_vm_bind ioctl 293 */ 294 __u32 flags; 295 /** 296 * @DRM_NOUVEAU_VM_BIND_RUN_ASYNC: 297 * 298 * Indicates that the given VM_BIND operation should be executed asynchronously 299 * by the kernel. 300 * 301 * If this flag is not supplied the kernel executes the associated operations 302 * synchronously and doesn't accept any &drm_nouveau_sync objects. 303 */ 304 #define DRM_NOUVEAU_VM_BIND_RUN_ASYNC 0x1 305 /** 306 * @wait_count: the number of wait &drm_nouveau_syncs 307 */ 308 __u32 wait_count; 309 /** 310 * @sig_count: the number of &drm_nouveau_syncs to signal when finished 311 */ 312 __u32 sig_count; 313 /** 314 * @wait_ptr: pointer to &drm_nouveau_syncs to wait for 315 */ 316 __u64 wait_ptr; 317 /** 318 * @sig_ptr: pointer to &drm_nouveau_syncs to signal when finished 319 */ 320 __u64 sig_ptr; 321 /** 322 * @op_ptr: pointer to the &drm_nouveau_vm_bind_ops to execute 323 */ 324 __u64 op_ptr; 325 }; 326 327 /** 328 * struct drm_nouveau_exec_push - EXEC push operation 329 * 330 * This structure represents a single EXEC push operation. UMDs should pass an 331 * array of this structure via struct drm_nouveau_exec's &push_ptr field. 332 */ 333 struct drm_nouveau_exec_push { 334 /** 335 * @va: the virtual address of the push buffer mapping 336 */ 337 __u64 va; 338 /** 339 * @va_len: the length of the push buffer mapping 340 */ 341 __u64 va_len; 342 }; 343 344 /** 345 * struct drm_nouveau_exec - structure for DRM_IOCTL_NOUVEAU_EXEC 346 */ 347 struct drm_nouveau_exec { 348 /** 349 * @channel: the channel to execute the push buffer in 350 */ 351 __u32 channel; 352 /** 353 * @push_count: the number of &drm_nouveau_exec_push ops 354 */ 355 __u32 push_count; 356 /** 357 * @wait_count: the number of wait &drm_nouveau_syncs 358 */ 359 __u32 wait_count; 360 /** 361 * @sig_count: the number of &drm_nouveau_syncs to signal when finished 362 */ 363 __u32 sig_count; 364 /** 365 * @wait_ptr: pointer to &drm_nouveau_syncs to wait for 366 */ 367 __u64 wait_ptr; 368 /** 369 * @sig_ptr: pointer to &drm_nouveau_syncs to signal when finished 370 */ 371 __u64 sig_ptr; 372 /** 373 * @push_ptr: pointer to &drm_nouveau_exec_push ops 374 */ 375 __u64 push_ptr; 376 }; 377 378 #define DRM_NOUVEAU_GETPARAM 0x00 379 #define DRM_NOUVEAU_SETPARAM 0x01 /* deprecated */ 380 #define DRM_NOUVEAU_CHANNEL_ALLOC 0x02 381 #define DRM_NOUVEAU_CHANNEL_FREE 0x03 382 #define DRM_NOUVEAU_GROBJ_ALLOC 0x04 /* deprecated */ 383 #define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05 /* deprecated */ 384 #define DRM_NOUVEAU_GPUOBJ_FREE 0x06 /* deprecated */ 385 #define DRM_NOUVEAU_NVIF 0x07 386 #define DRM_NOUVEAU_SVM_INIT 0x08 387 #define DRM_NOUVEAU_SVM_BIND 0x09 388 #define DRM_NOUVEAU_VM_INIT 0x10 389 #define DRM_NOUVEAU_VM_BIND 0x11 390 #define DRM_NOUVEAU_EXEC 0x12 391 #define DRM_NOUVEAU_GEM_NEW 0x40 392 #define DRM_NOUVEAU_GEM_PUSHBUF 0x41 393 #define DRM_NOUVEAU_GEM_CPU_PREP 0x42 394 #define DRM_NOUVEAU_GEM_CPU_FINI 0x43 395 #define DRM_NOUVEAU_GEM_INFO 0x44 396 397 struct drm_nouveau_svm_init { 398 __u64 unmanaged_addr; 399 __u64 unmanaged_size; 400 }; 401 402 struct drm_nouveau_svm_bind { 403 __u64 header; 404 __u64 va_start; 405 __u64 va_end; 406 __u64 npages; 407 __u64 stride; 408 __u64 result; 409 __u64 reserved0; 410 __u64 reserved1; 411 }; 412 413 #define NOUVEAU_SVM_BIND_COMMAND_SHIFT 0 414 #define NOUVEAU_SVM_BIND_COMMAND_BITS 8 415 #define NOUVEAU_SVM_BIND_COMMAND_MASK ((1 << 8) - 1) 416 #define NOUVEAU_SVM_BIND_PRIORITY_SHIFT 8 417 #define NOUVEAU_SVM_BIND_PRIORITY_BITS 8 418 #define NOUVEAU_SVM_BIND_PRIORITY_MASK ((1 << 8) - 1) 419 #define NOUVEAU_SVM_BIND_TARGET_SHIFT 16 420 #define NOUVEAU_SVM_BIND_TARGET_BITS 32 421 #define NOUVEAU_SVM_BIND_TARGET_MASK 0xffffffff 422 423 /* 424 * Below is use to validate ioctl argument, userspace can also use it to make 425 * sure that no bit are set beyond known fields for a given kernel version. 426 */ 427 #define NOUVEAU_SVM_BIND_VALID_BITS 48 428 #define NOUVEAU_SVM_BIND_VALID_MASK ((1ULL << NOUVEAU_SVM_BIND_VALID_BITS) - 1) 429 430 431 /* 432 * NOUVEAU_BIND_COMMAND__MIGRATE: synchronous migrate to target memory. 433 * result: number of page successfuly migrate to the target memory. 434 */ 435 #define NOUVEAU_SVM_BIND_COMMAND__MIGRATE 0 436 437 /* 438 * NOUVEAU_SVM_BIND_HEADER_TARGET__GPU_VRAM: target the GPU VRAM memory. 439 */ 440 #define NOUVEAU_SVM_BIND_TARGET__GPU_VRAM (1UL << 31) 441 442 443 #define DRM_IOCTL_NOUVEAU_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GETPARAM, struct drm_nouveau_getparam) 444 #define DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_ALLOC, struct drm_nouveau_channel_alloc) 445 #define DRM_IOCTL_NOUVEAU_CHANNEL_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_FREE, struct drm_nouveau_channel_free) 446 447 #define DRM_IOCTL_NOUVEAU_SVM_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_INIT, struct drm_nouveau_svm_init) 448 #define DRM_IOCTL_NOUVEAU_SVM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_BIND, struct drm_nouveau_svm_bind) 449 450 #define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new) 451 #define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf) 452 #define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep) 453 #define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini) 454 #define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info) 455 456 #define DRM_IOCTL_NOUVEAU_VM_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_VM_INIT, struct drm_nouveau_vm_init) 457 #define DRM_IOCTL_NOUVEAU_VM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_VM_BIND, struct drm_nouveau_vm_bind) 458 #define DRM_IOCTL_NOUVEAU_EXEC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_EXEC, struct drm_nouveau_exec) 459 #if defined(__cplusplus) 460 } 461 #endif 462 463 #endif /* __NOUVEAU_DRM_H__ */ 464