1 /* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef __NOUVEAU_DRM_H__ 26 #define __NOUVEAU_DRM_H__ 27 28 #define DRM_NOUVEAU_EVENT_NVIF 0x80000000 29 30 #include <drm/drm.h> 31 32 #define NOUVEAU_GEM_DOMAIN_CPU (1 << 0) 33 #define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1) 34 #define NOUVEAU_GEM_DOMAIN_GART (1 << 2) 35 #define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3) 36 #define NOUVEAU_GEM_DOMAIN_COHERENT (1 << 4) 37 38 #define NOUVEAU_GEM_TILE_COMP 0x00030000 /* nv50-only */ 39 #define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00 40 #define NOUVEAU_GEM_TILE_16BPP 0x00000001 41 #define NOUVEAU_GEM_TILE_32BPP 0x00000002 42 #define NOUVEAU_GEM_TILE_ZETA 0x00000004 43 #define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008 44 45 struct drm_nouveau_gem_info { 46 __u32 handle; 47 __u32 domain; 48 __u64 size; 49 __u64 offset; 50 __u64 map_handle; 51 __u32 tile_mode; 52 __u32 tile_flags; 53 }; 54 55 struct drm_nouveau_gem_new { 56 struct drm_nouveau_gem_info info; 57 __u32 channel_hint; 58 __u32 align; 59 }; 60 61 #define NOUVEAU_GEM_MAX_BUFFERS 1024 62 struct drm_nouveau_gem_pushbuf_bo_presumed { 63 __u32 valid; 64 __u32 domain; 65 __u64 offset; 66 }; 67 68 struct drm_nouveau_gem_pushbuf_bo { 69 __u64 user_priv; 70 __u32 handle; 71 __u32 read_domains; 72 __u32 write_domains; 73 __u32 valid_domains; 74 struct drm_nouveau_gem_pushbuf_bo_presumed presumed; 75 }; 76 77 #define NOUVEAU_GEM_RELOC_LOW (1 << 0) 78 #define NOUVEAU_GEM_RELOC_HIGH (1 << 1) 79 #define NOUVEAU_GEM_RELOC_OR (1 << 2) 80 #define NOUVEAU_GEM_MAX_RELOCS 1024 81 struct drm_nouveau_gem_pushbuf_reloc { 82 __u32 reloc_bo_index; 83 __u32 reloc_bo_offset; 84 __u32 bo_index; 85 __u32 flags; 86 __u32 data; 87 __u32 vor; 88 __u32 tor; 89 }; 90 91 #define NOUVEAU_GEM_MAX_PUSH 512 92 struct drm_nouveau_gem_pushbuf_push { 93 __u32 bo_index; 94 __u32 pad; 95 __u64 offset; 96 __u64 length; 97 }; 98 99 struct drm_nouveau_gem_pushbuf { 100 __u32 channel; 101 __u32 nr_buffers; 102 __u64 buffers; 103 __u32 nr_relocs; 104 __u32 nr_push; 105 __u64 relocs; 106 __u64 push; 107 __u32 suffix0; 108 __u32 suffix1; 109 __u64 vram_available; 110 __u64 gart_available; 111 }; 112 113 #define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001 114 #define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004 115 struct drm_nouveau_gem_cpu_prep { 116 __u32 handle; 117 __u32 flags; 118 }; 119 120 struct drm_nouveau_gem_cpu_fini { 121 __u32 handle; 122 }; 123 124 #define DRM_NOUVEAU_GETPARAM 0x00 /* deprecated */ 125 #define DRM_NOUVEAU_SETPARAM 0x01 /* deprecated */ 126 #define DRM_NOUVEAU_CHANNEL_ALLOC 0x02 /* deprecated */ 127 #define DRM_NOUVEAU_CHANNEL_FREE 0x03 /* deprecated */ 128 #define DRM_NOUVEAU_GROBJ_ALLOC 0x04 /* deprecated */ 129 #define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05 /* deprecated */ 130 #define DRM_NOUVEAU_GPUOBJ_FREE 0x06 /* deprecated */ 131 #define DRM_NOUVEAU_NVIF 0x07 132 #define DRM_NOUVEAU_GEM_NEW 0x40 133 #define DRM_NOUVEAU_GEM_PUSHBUF 0x41 134 #define DRM_NOUVEAU_GEM_CPU_PREP 0x42 135 #define DRM_NOUVEAU_GEM_CPU_FINI 0x43 136 #define DRM_NOUVEAU_GEM_INFO 0x44 137 138 #define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new) 139 #define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf) 140 #define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep) 141 #define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini) 142 #define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info) 143 144 #endif /* __NOUVEAU_DRM_H__ */ 145