xref: /openbmc/linux/include/uapi/drm/nouveau_drm.h (revision 6548d543)
1 /*
2  * Copyright 2005 Stephane Marchesin.
3  * All Rights Reserved.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice (including the next
13  * paragraph) shall be included in all copies or substantial portions of the
14  * Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  */
24 
25 #ifndef __NOUVEAU_DRM_H__
26 #define __NOUVEAU_DRM_H__
27 
28 #define DRM_NOUVEAU_EVENT_NVIF                                       0x80000000
29 
30 #include "drm.h"
31 
32 #if defined(__cplusplus)
33 extern "C" {
34 #endif
35 
36 #define NOUVEAU_GETPARAM_PCI_VENDOR      3
37 #define NOUVEAU_GETPARAM_PCI_DEVICE      4
38 #define NOUVEAU_GETPARAM_BUS_TYPE        5
39 #define NOUVEAU_GETPARAM_FB_SIZE         8
40 #define NOUVEAU_GETPARAM_AGP_SIZE        9
41 #define NOUVEAU_GETPARAM_CHIPSET_ID      11
42 #define NOUVEAU_GETPARAM_VM_VRAM_BASE    12
43 #define NOUVEAU_GETPARAM_GRAPH_UNITS     13
44 #define NOUVEAU_GETPARAM_PTIMER_TIME     14
45 #define NOUVEAU_GETPARAM_HAS_BO_USAGE    15
46 #define NOUVEAU_GETPARAM_HAS_PAGEFLIP    16
47 
48 /*
49  * NOUVEAU_GETPARAM_EXEC_PUSH_MAX - query max pushes through getparam
50  *
51  * Query the maximum amount of IBs that can be pushed through a single
52  * &drm_nouveau_exec structure and hence a single &DRM_IOCTL_NOUVEAU_EXEC
53  * ioctl().
54  */
55 #define NOUVEAU_GETPARAM_EXEC_PUSH_MAX   17
56 
57 /*
58  * NOUVEAU_GETPARAM_VRAM_BAR_SIZE - query bar size
59  *
60  * Query the VRAM BAR size.
61  */
62 #define NOUVEAU_GETPARAM_VRAM_BAR_SIZE 18
63 
64 /*
65  * NOUVEAU_GETPARAM_VRAM_USED
66  *
67  * Get remaining VRAM size.
68  */
69 #define NOUVEAU_GETPARAM_VRAM_USED 19
70 
71 /*
72  * NOUVEAU_GETPARAM_HAS_VMA_TILEMODE
73  *
74  * Query whether tile mode and PTE kind are accepted with VM allocs or not.
75  */
76 #define NOUVEAU_GETPARAM_HAS_VMA_TILEMODE 20
77 
78 struct drm_nouveau_getparam {
79 	__u64 param;
80 	__u64 value;
81 };
82 
83 struct drm_nouveau_channel_alloc {
84 	__u32     fb_ctxdma_handle;
85 	__u32     tt_ctxdma_handle;
86 
87 	__s32     channel;
88 	__u32     pushbuf_domains;
89 
90 	/* Notifier memory */
91 	__u32     notifier_handle;
92 
93 	/* DRM-enforced subchannel assignments */
94 	struct {
95 		__u32 handle;
96 		__u32 grclass;
97 	} subchan[8];
98 	__u32 nr_subchan;
99 };
100 
101 struct drm_nouveau_channel_free {
102 	__s32 channel;
103 };
104 
105 #define NOUVEAU_GEM_DOMAIN_CPU       (1 << 0)
106 #define NOUVEAU_GEM_DOMAIN_VRAM      (1 << 1)
107 #define NOUVEAU_GEM_DOMAIN_GART      (1 << 2)
108 #define NOUVEAU_GEM_DOMAIN_MAPPABLE  (1 << 3)
109 #define NOUVEAU_GEM_DOMAIN_COHERENT  (1 << 4)
110 /* The BO will never be shared via import or export. */
111 #define NOUVEAU_GEM_DOMAIN_NO_SHARE  (1 << 5)
112 
113 #define NOUVEAU_GEM_TILE_COMP        0x00030000 /* nv50-only */
114 #define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00
115 #define NOUVEAU_GEM_TILE_16BPP       0x00000001
116 #define NOUVEAU_GEM_TILE_32BPP       0x00000002
117 #define NOUVEAU_GEM_TILE_ZETA        0x00000004
118 #define NOUVEAU_GEM_TILE_NONCONTIG   0x00000008
119 
120 struct drm_nouveau_gem_info {
121 	__u32 handle;
122 	__u32 domain;
123 	__u64 size;
124 	__u64 offset;
125 	__u64 map_handle;
126 	__u32 tile_mode;
127 	__u32 tile_flags;
128 };
129 
130 struct drm_nouveau_gem_new {
131 	struct drm_nouveau_gem_info info;
132 	__u32 channel_hint;
133 	__u32 align;
134 };
135 
136 #define NOUVEAU_GEM_MAX_BUFFERS 1024
137 struct drm_nouveau_gem_pushbuf_bo_presumed {
138 	__u32 valid;
139 	__u32 domain;
140 	__u64 offset;
141 };
142 
143 struct drm_nouveau_gem_pushbuf_bo {
144 	__u64 user_priv;
145 	__u32 handle;
146 	__u32 read_domains;
147 	__u32 write_domains;
148 	__u32 valid_domains;
149 	struct drm_nouveau_gem_pushbuf_bo_presumed presumed;
150 };
151 
152 #define NOUVEAU_GEM_RELOC_LOW  (1 << 0)
153 #define NOUVEAU_GEM_RELOC_HIGH (1 << 1)
154 #define NOUVEAU_GEM_RELOC_OR   (1 << 2)
155 #define NOUVEAU_GEM_MAX_RELOCS 1024
156 struct drm_nouveau_gem_pushbuf_reloc {
157 	__u32 reloc_bo_index;
158 	__u32 reloc_bo_offset;
159 	__u32 bo_index;
160 	__u32 flags;
161 	__u32 data;
162 	__u32 vor;
163 	__u32 tor;
164 };
165 
166 #define NOUVEAU_GEM_MAX_PUSH 512
167 struct drm_nouveau_gem_pushbuf_push {
168 	__u32 bo_index;
169 	__u32 pad;
170 	__u64 offset;
171 	__u64 length;
172 #define NOUVEAU_GEM_PUSHBUF_NO_PREFETCH (1 << 23)
173 };
174 
175 struct drm_nouveau_gem_pushbuf {
176 	__u32 channel;
177 	__u32 nr_buffers;
178 	__u64 buffers;
179 	__u32 nr_relocs;
180 	__u32 nr_push;
181 	__u64 relocs;
182 	__u64 push;
183 	__u32 suffix0;
184 	__u32 suffix1;
185 #define NOUVEAU_GEM_PUSHBUF_SYNC                                    (1ULL << 0)
186 	__u64 vram_available;
187 	__u64 gart_available;
188 };
189 
190 #define NOUVEAU_GEM_CPU_PREP_NOWAIT                                  0x00000001
191 #define NOUVEAU_GEM_CPU_PREP_WRITE                                   0x00000004
192 struct drm_nouveau_gem_cpu_prep {
193 	__u32 handle;
194 	__u32 flags;
195 };
196 
197 struct drm_nouveau_gem_cpu_fini {
198 	__u32 handle;
199 };
200 
201 /**
202  * struct drm_nouveau_sync - sync object
203  *
204  * This structure serves as synchronization mechanism for (potentially)
205  * asynchronous operations such as EXEC or VM_BIND.
206  */
207 struct drm_nouveau_sync {
208 	/**
209 	 * @flags: the flags for a sync object
210 	 *
211 	 * The first 8 bits are used to determine the type of the sync object.
212 	 */
213 	__u32 flags;
214 #define DRM_NOUVEAU_SYNC_SYNCOBJ 0x0
215 #define DRM_NOUVEAU_SYNC_TIMELINE_SYNCOBJ 0x1
216 #define DRM_NOUVEAU_SYNC_TYPE_MASK 0xf
217 	/**
218 	 * @handle: the handle of the sync object
219 	 */
220 	__u32 handle;
221 	/**
222 	 * @timeline_value:
223 	 *
224 	 * The timeline point of the sync object in case the syncobj is of
225 	 * type DRM_NOUVEAU_SYNC_TIMELINE_SYNCOBJ.
226 	 */
227 	__u64 timeline_value;
228 };
229 
230 /**
231  * struct drm_nouveau_vm_init - GPU VA space init structure
232  *
233  * Used to initialize the GPU's VA space for a user client, telling the kernel
234  * which portion of the VA space is managed by the UMD and kernel respectively.
235  *
236  * For the UMD to use the VM_BIND uAPI, this must be called before any BOs or
237  * channels are created; if called afterwards DRM_IOCTL_NOUVEAU_VM_INIT fails
238  * with -ENOSYS.
239  */
240 struct drm_nouveau_vm_init {
241 	/**
242 	 * @kernel_managed_addr: start address of the kernel managed VA space
243 	 * region
244 	 */
245 	__u64 kernel_managed_addr;
246 	/**
247 	 * @kernel_managed_size: size of the kernel managed VA space region in
248 	 * bytes
249 	 */
250 	__u64 kernel_managed_size;
251 };
252 
253 /**
254  * struct drm_nouveau_vm_bind_op - VM_BIND operation
255  *
256  * This structure represents a single VM_BIND operation. UMDs should pass
257  * an array of this structure via struct drm_nouveau_vm_bind's &op_ptr field.
258  */
259 struct drm_nouveau_vm_bind_op {
260 	/**
261 	 * @op: the operation type
262 	 */
263 	__u32 op;
264 /**
265  * @DRM_NOUVEAU_VM_BIND_OP_MAP:
266  *
267  * Map a GEM object to the GPU's VA space. Optionally, the
268  * &DRM_NOUVEAU_VM_BIND_SPARSE flag can be passed to instruct the kernel to
269  * create sparse mappings for the given range.
270  */
271 #define DRM_NOUVEAU_VM_BIND_OP_MAP 0x0
272 /**
273  * @DRM_NOUVEAU_VM_BIND_OP_UNMAP:
274  *
275  * Unmap an existing mapping in the GPU's VA space. If the region the mapping
276  * is located in is a sparse region, new sparse mappings are created where the
277  * unmapped (memory backed) mapping was mapped previously. To remove a sparse
278  * region the &DRM_NOUVEAU_VM_BIND_SPARSE must be set.
279  */
280 #define DRM_NOUVEAU_VM_BIND_OP_UNMAP 0x1
281 	/**
282 	 * @flags: the flags for a &drm_nouveau_vm_bind_op
283 	 */
284 	__u32 flags;
285 /**
286  * @DRM_NOUVEAU_VM_BIND_SPARSE:
287  *
288  * Indicates that an allocated VA space region should be sparse.
289  */
290 #define DRM_NOUVEAU_VM_BIND_SPARSE (1 << 8)
291 	/**
292 	 * @handle: the handle of the DRM GEM object to map
293 	 */
294 	__u32 handle;
295 	/**
296 	 * @pad: 32 bit padding, should be 0
297 	 */
298 	__u32 pad;
299 	/**
300 	 * @addr:
301 	 *
302 	 * the address the VA space region or (memory backed) mapping should be mapped to
303 	 */
304 	__u64 addr;
305 	/**
306 	 * @bo_offset: the offset within the BO backing the mapping
307 	 */
308 	__u64 bo_offset;
309 	/**
310 	 * @range: the size of the requested mapping in bytes
311 	 */
312 	__u64 range;
313 };
314 
315 /**
316  * struct drm_nouveau_vm_bind - structure for DRM_IOCTL_NOUVEAU_VM_BIND
317  */
318 struct drm_nouveau_vm_bind {
319 	/**
320 	 * @op_count: the number of &drm_nouveau_vm_bind_op
321 	 */
322 	__u32 op_count;
323 	/**
324 	 * @flags: the flags for a &drm_nouveau_vm_bind ioctl
325 	 */
326 	__u32 flags;
327 /**
328  * @DRM_NOUVEAU_VM_BIND_RUN_ASYNC:
329  *
330  * Indicates that the given VM_BIND operation should be executed asynchronously
331  * by the kernel.
332  *
333  * If this flag is not supplied the kernel executes the associated operations
334  * synchronously and doesn't accept any &drm_nouveau_sync objects.
335  */
336 #define DRM_NOUVEAU_VM_BIND_RUN_ASYNC 0x1
337 	/**
338 	 * @wait_count: the number of wait &drm_nouveau_syncs
339 	 */
340 	__u32 wait_count;
341 	/**
342 	 * @sig_count: the number of &drm_nouveau_syncs to signal when finished
343 	 */
344 	__u32 sig_count;
345 	/**
346 	 * @wait_ptr: pointer to &drm_nouveau_syncs to wait for
347 	 */
348 	__u64 wait_ptr;
349 	/**
350 	 * @sig_ptr: pointer to &drm_nouveau_syncs to signal when finished
351 	 */
352 	__u64 sig_ptr;
353 	/**
354 	 * @op_ptr: pointer to the &drm_nouveau_vm_bind_ops to execute
355 	 */
356 	__u64 op_ptr;
357 };
358 
359 /**
360  * struct drm_nouveau_exec_push - EXEC push operation
361  *
362  * This structure represents a single EXEC push operation. UMDs should pass an
363  * array of this structure via struct drm_nouveau_exec's &push_ptr field.
364  */
365 struct drm_nouveau_exec_push {
366 	/**
367 	 * @va: the virtual address of the push buffer mapping
368 	 */
369 	__u64 va;
370 	/**
371 	 * @va_len: the length of the push buffer mapping
372 	 */
373 	__u32 va_len;
374 	/**
375 	 * @flags: the flags for this push buffer mapping
376 	 */
377 	__u32 flags;
378 #define DRM_NOUVEAU_EXEC_PUSH_NO_PREFETCH 0x1
379 };
380 
381 /**
382  * struct drm_nouveau_exec - structure for DRM_IOCTL_NOUVEAU_EXEC
383  */
384 struct drm_nouveau_exec {
385 	/**
386 	 * @channel: the channel to execute the push buffer in
387 	 */
388 	__u32 channel;
389 	/**
390 	 * @push_count: the number of &drm_nouveau_exec_push ops
391 	 */
392 	__u32 push_count;
393 	/**
394 	 * @wait_count: the number of wait &drm_nouveau_syncs
395 	 */
396 	__u32 wait_count;
397 	/**
398 	 * @sig_count: the number of &drm_nouveau_syncs to signal when finished
399 	 */
400 	__u32 sig_count;
401 	/**
402 	 * @wait_ptr: pointer to &drm_nouveau_syncs to wait for
403 	 */
404 	__u64 wait_ptr;
405 	/**
406 	 * @sig_ptr: pointer to &drm_nouveau_syncs to signal when finished
407 	 */
408 	__u64 sig_ptr;
409 	/**
410 	 * @push_ptr: pointer to &drm_nouveau_exec_push ops
411 	 */
412 	__u64 push_ptr;
413 };
414 
415 #define DRM_NOUVEAU_GETPARAM           0x00
416 #define DRM_NOUVEAU_SETPARAM           0x01 /* deprecated */
417 #define DRM_NOUVEAU_CHANNEL_ALLOC      0x02
418 #define DRM_NOUVEAU_CHANNEL_FREE       0x03
419 #define DRM_NOUVEAU_GROBJ_ALLOC        0x04 /* deprecated */
420 #define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC  0x05 /* deprecated */
421 #define DRM_NOUVEAU_GPUOBJ_FREE        0x06 /* deprecated */
422 #define DRM_NOUVEAU_NVIF               0x07
423 #define DRM_NOUVEAU_SVM_INIT           0x08
424 #define DRM_NOUVEAU_SVM_BIND           0x09
425 #define DRM_NOUVEAU_VM_INIT            0x10
426 #define DRM_NOUVEAU_VM_BIND            0x11
427 #define DRM_NOUVEAU_EXEC               0x12
428 #define DRM_NOUVEAU_GEM_NEW            0x40
429 #define DRM_NOUVEAU_GEM_PUSHBUF        0x41
430 #define DRM_NOUVEAU_GEM_CPU_PREP       0x42
431 #define DRM_NOUVEAU_GEM_CPU_FINI       0x43
432 #define DRM_NOUVEAU_GEM_INFO           0x44
433 
434 struct drm_nouveau_svm_init {
435 	__u64 unmanaged_addr;
436 	__u64 unmanaged_size;
437 };
438 
439 struct drm_nouveau_svm_bind {
440 	__u64 header;
441 	__u64 va_start;
442 	__u64 va_end;
443 	__u64 npages;
444 	__u64 stride;
445 	__u64 result;
446 	__u64 reserved0;
447 	__u64 reserved1;
448 };
449 
450 #define NOUVEAU_SVM_BIND_COMMAND_SHIFT          0
451 #define NOUVEAU_SVM_BIND_COMMAND_BITS           8
452 #define NOUVEAU_SVM_BIND_COMMAND_MASK           ((1 << 8) - 1)
453 #define NOUVEAU_SVM_BIND_PRIORITY_SHIFT         8
454 #define NOUVEAU_SVM_BIND_PRIORITY_BITS          8
455 #define NOUVEAU_SVM_BIND_PRIORITY_MASK          ((1 << 8) - 1)
456 #define NOUVEAU_SVM_BIND_TARGET_SHIFT           16
457 #define NOUVEAU_SVM_BIND_TARGET_BITS            32
458 #define NOUVEAU_SVM_BIND_TARGET_MASK            0xffffffff
459 
460 /*
461  * Below is use to validate ioctl argument, userspace can also use it to make
462  * sure that no bit are set beyond known fields for a given kernel version.
463  */
464 #define NOUVEAU_SVM_BIND_VALID_BITS     48
465 #define NOUVEAU_SVM_BIND_VALID_MASK     ((1ULL << NOUVEAU_SVM_BIND_VALID_BITS) - 1)
466 
467 
468 /*
469  * NOUVEAU_BIND_COMMAND__MIGRATE: synchronous migrate to target memory.
470  * result: number of page successfuly migrate to the target memory.
471  */
472 #define NOUVEAU_SVM_BIND_COMMAND__MIGRATE               0
473 
474 /*
475  * NOUVEAU_SVM_BIND_HEADER_TARGET__GPU_VRAM: target the GPU VRAM memory.
476  */
477 #define NOUVEAU_SVM_BIND_TARGET__GPU_VRAM               (1UL << 31)
478 
479 
480 #define DRM_IOCTL_NOUVEAU_GETPARAM           DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GETPARAM, struct drm_nouveau_getparam)
481 #define DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC      DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_ALLOC, struct drm_nouveau_channel_alloc)
482 #define DRM_IOCTL_NOUVEAU_CHANNEL_FREE       DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_FREE, struct drm_nouveau_channel_free)
483 
484 #define DRM_IOCTL_NOUVEAU_SVM_INIT           DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_INIT, struct drm_nouveau_svm_init)
485 #define DRM_IOCTL_NOUVEAU_SVM_BIND           DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_BIND, struct drm_nouveau_svm_bind)
486 
487 #define DRM_IOCTL_NOUVEAU_GEM_NEW            DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new)
488 #define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF        DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf)
489 #define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP       DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep)
490 #define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI       DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini)
491 #define DRM_IOCTL_NOUVEAU_GEM_INFO           DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info)
492 
493 #define DRM_IOCTL_NOUVEAU_VM_INIT            DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_VM_INIT, struct drm_nouveau_vm_init)
494 #define DRM_IOCTL_NOUVEAU_VM_BIND            DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_VM_BIND, struct drm_nouveau_vm_bind)
495 #define DRM_IOCTL_NOUVEAU_EXEC               DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_EXEC, struct drm_nouveau_exec)
496 #if defined(__cplusplus)
497 }
498 #endif
499 
500 #endif /* __NOUVEAU_DRM_H__ */
501