1 /* 2 * Copyright (C) 2013 Red Hat 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #ifndef __MSM_DRM_H__ 19 #define __MSM_DRM_H__ 20 21 #include "drm.h" 22 23 #if defined(__cplusplus) 24 extern "C" { 25 #endif 26 27 /* Please note that modifications to all structs defined here are 28 * subject to backwards-compatibility constraints: 29 * 1) Do not use pointers, use __u64 instead for 32 bit / 64 bit 30 * user/kernel compatibility 31 * 2) Keep fields aligned to their size 32 * 3) Because of how drm_ioctl() works, we can add new fields at 33 * the end of an ioctl if some care is taken: drm_ioctl() will 34 * zero out the new fields at the tail of the ioctl, so a zero 35 * value should have a backwards compatible meaning. And for 36 * output params, userspace won't see the newly added output 37 * fields.. so that has to be somehow ok. 38 */ 39 40 #define MSM_PIPE_NONE 0x00 41 #define MSM_PIPE_2D0 0x01 42 #define MSM_PIPE_2D1 0x02 43 #define MSM_PIPE_3D0 0x10 44 45 /* timeouts are specified in clock-monotonic absolute times (to simplify 46 * restarting interrupted ioctls). The following struct is logically the 47 * same as 'struct timespec' but 32/64b ABI safe. 48 */ 49 struct drm_msm_timespec { 50 __s64 tv_sec; /* seconds */ 51 __s64 tv_nsec; /* nanoseconds */ 52 }; 53 54 #define MSM_PARAM_GPU_ID 0x01 55 #define MSM_PARAM_GMEM_SIZE 0x02 56 #define MSM_PARAM_CHIP_ID 0x03 57 #define MSM_PARAM_MAX_FREQ 0x04 58 #define MSM_PARAM_TIMESTAMP 0x05 59 60 struct drm_msm_param { 61 __u32 pipe; /* in, MSM_PIPE_x */ 62 __u32 param; /* in, MSM_PARAM_x */ 63 __u64 value; /* out (get_param) or in (set_param) */ 64 }; 65 66 /* 67 * GEM buffers: 68 */ 69 70 #define MSM_BO_SCANOUT 0x00000001 /* scanout capable */ 71 #define MSM_BO_GPU_READONLY 0x00000002 72 #define MSM_BO_CACHE_MASK 0x000f0000 73 /* cache modes */ 74 #define MSM_BO_CACHED 0x00010000 75 #define MSM_BO_WC 0x00020000 76 #define MSM_BO_UNCACHED 0x00040000 77 78 #define MSM_BO_FLAGS (MSM_BO_SCANOUT | \ 79 MSM_BO_GPU_READONLY | \ 80 MSM_BO_CACHED | \ 81 MSM_BO_WC | \ 82 MSM_BO_UNCACHED) 83 84 struct drm_msm_gem_new { 85 __u64 size; /* in */ 86 __u32 flags; /* in, mask of MSM_BO_x */ 87 __u32 handle; /* out */ 88 }; 89 90 struct drm_msm_gem_info { 91 __u32 handle; /* in */ 92 __u32 pad; 93 __u64 offset; /* out, offset to pass to mmap() */ 94 }; 95 96 #define MSM_PREP_READ 0x01 97 #define MSM_PREP_WRITE 0x02 98 #define MSM_PREP_NOSYNC 0x04 99 100 #define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC) 101 102 struct drm_msm_gem_cpu_prep { 103 __u32 handle; /* in */ 104 __u32 op; /* in, mask of MSM_PREP_x */ 105 struct drm_msm_timespec timeout; /* in */ 106 }; 107 108 struct drm_msm_gem_cpu_fini { 109 __u32 handle; /* in */ 110 }; 111 112 /* 113 * Cmdstream Submission: 114 */ 115 116 /* The value written into the cmdstream is logically: 117 * 118 * ((relocbuf->gpuaddr + reloc_offset) << shift) | or 119 * 120 * When we have GPU's w/ >32bit ptrs, it should be possible to deal 121 * with this by emit'ing two reloc entries with appropriate shift 122 * values. Or a new MSM_SUBMIT_CMD_x type would also be an option. 123 * 124 * NOTE that reloc's must be sorted by order of increasing submit_offset, 125 * otherwise EINVAL. 126 */ 127 struct drm_msm_gem_submit_reloc { 128 __u32 submit_offset; /* in, offset from submit_bo */ 129 __u32 or; /* in, value OR'd with result */ 130 __s32 shift; /* in, amount of left shift (can be negative) */ 131 __u32 reloc_idx; /* in, index of reloc_bo buffer */ 132 __u64 reloc_offset; /* in, offset from start of reloc_bo */ 133 }; 134 135 /* submit-types: 136 * BUF - this cmd buffer is executed normally. 137 * IB_TARGET_BUF - this cmd buffer is an IB target. Reloc's are 138 * processed normally, but the kernel does not setup an IB to 139 * this buffer in the first-level ringbuffer 140 * CTX_RESTORE_BUF - only executed if there has been a GPU context 141 * switch since the last SUBMIT ioctl 142 */ 143 #define MSM_SUBMIT_CMD_BUF 0x0001 144 #define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002 145 #define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003 146 struct drm_msm_gem_submit_cmd { 147 __u32 type; /* in, one of MSM_SUBMIT_CMD_x */ 148 __u32 submit_idx; /* in, index of submit_bo cmdstream buffer */ 149 __u32 submit_offset; /* in, offset into submit_bo */ 150 __u32 size; /* in, cmdstream size */ 151 __u32 pad; 152 __u32 nr_relocs; /* in, number of submit_reloc's */ 153 __u64 __user relocs; /* in, ptr to array of submit_reloc's */ 154 }; 155 156 /* Each buffer referenced elsewhere in the cmdstream submit (ie. the 157 * cmdstream buffer(s) themselves or reloc entries) has one (and only 158 * one) entry in the submit->bos[] table. 159 * 160 * As a optimization, the current buffer (gpu virtual address) can be 161 * passed back through the 'presumed' field. If on a subsequent reloc, 162 * userspace passes back a 'presumed' address that is still valid, 163 * then patching the cmdstream for this entry is skipped. This can 164 * avoid kernel needing to map/access the cmdstream bo in the common 165 * case. 166 */ 167 #define MSM_SUBMIT_BO_READ 0x0001 168 #define MSM_SUBMIT_BO_WRITE 0x0002 169 170 #define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE) 171 172 struct drm_msm_gem_submit_bo { 173 __u32 flags; /* in, mask of MSM_SUBMIT_BO_x */ 174 __u32 handle; /* in, GEM handle */ 175 __u64 presumed; /* in/out, presumed buffer address */ 176 }; 177 178 /* Each cmdstream submit consists of a table of buffers involved, and 179 * one or more cmdstream buffers. This allows for conditional execution 180 * (context-restore), and IB buffers needed for per tile/bin draw cmds. 181 */ 182 struct drm_msm_gem_submit { 183 __u32 pipe; /* in, MSM_PIPE_x */ 184 __u32 fence; /* out */ 185 __u32 nr_bos; /* in, number of submit_bo's */ 186 __u32 nr_cmds; /* in, number of submit_cmd's */ 187 __u64 __user bos; /* in, ptr to array of submit_bo's */ 188 __u64 __user cmds; /* in, ptr to array of submit_cmd's */ 189 }; 190 191 /* The normal way to synchronize with the GPU is just to CPU_PREP on 192 * a buffer if you need to access it from the CPU (other cmdstream 193 * submission from same or other contexts, PAGE_FLIP ioctl, etc, all 194 * handle the required synchronization under the hood). This ioctl 195 * mainly just exists as a way to implement the gallium pipe_fence 196 * APIs without requiring a dummy bo to synchronize on. 197 */ 198 struct drm_msm_wait_fence { 199 __u32 fence; /* in */ 200 __u32 pad; 201 struct drm_msm_timespec timeout; /* in */ 202 }; 203 204 /* madvise provides a way to tell the kernel in case a buffers contents 205 * can be discarded under memory pressure, which is useful for userspace 206 * bo cache where we want to optimistically hold on to buffer allocate 207 * and potential mmap, but allow the pages to be discarded under memory 208 * pressure. 209 * 210 * Typical usage would involve madvise(DONTNEED) when buffer enters BO 211 * cache, and madvise(WILLNEED) if trying to recycle buffer from BO cache. 212 * In the WILLNEED case, 'retained' indicates to userspace whether the 213 * backing pages still exist. 214 */ 215 #define MSM_MADV_WILLNEED 0 /* backing pages are needed, status returned in 'retained' */ 216 #define MSM_MADV_DONTNEED 1 /* backing pages not needed */ 217 #define __MSM_MADV_PURGED 2 /* internal state */ 218 219 struct drm_msm_gem_madvise { 220 __u32 handle; /* in, GEM handle */ 221 __u32 madv; /* in, MSM_MADV_x */ 222 __u32 retained; /* out, whether backing store still exists */ 223 }; 224 225 #define DRM_MSM_GET_PARAM 0x00 226 /* placeholder: 227 #define DRM_MSM_SET_PARAM 0x01 228 */ 229 #define DRM_MSM_GEM_NEW 0x02 230 #define DRM_MSM_GEM_INFO 0x03 231 #define DRM_MSM_GEM_CPU_PREP 0x04 232 #define DRM_MSM_GEM_CPU_FINI 0x05 233 #define DRM_MSM_GEM_SUBMIT 0x06 234 #define DRM_MSM_WAIT_FENCE 0x07 235 #define DRM_MSM_GEM_MADVISE 0x08 236 #define DRM_MSM_NUM_IOCTLS 0x09 237 238 #define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param) 239 #define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new) 240 #define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info) 241 #define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep) 242 #define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini) 243 #define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit) 244 #define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence) 245 #define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise) 246 247 #if defined(__cplusplus) 248 } 249 #endif 250 251 #endif /* __MSM_DRM_H__ */ 252