1 /* 2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 * 25 */ 26 27 #ifndef _UAPI_I915_DRM_H_ 28 #define _UAPI_I915_DRM_H_ 29 30 #include <drm/drm.h> 31 32 /* Please note that modifications to all structs defined here are 33 * subject to backwards-compatibility constraints. 34 */ 35 36 /** 37 * DOC: uevents generated by i915 on it's device node 38 * 39 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch 40 * event from the gpu l3 cache. Additional information supplied is ROW, 41 * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep 42 * track of these events and if a specific cache-line seems to have a 43 * persistent error remap it with the l3 remapping tool supplied in 44 * intel-gpu-tools. The value supplied with the event is always 1. 45 * 46 * I915_ERROR_UEVENT - Generated upon error detection, currently only via 47 * hangcheck. The error detection event is a good indicator of when things 48 * began to go badly. The value supplied with the event is a 1 upon error 49 * detection, and a 0 upon reset completion, signifying no more error 50 * exists. NOTE: Disabling hangcheck or reset via module parameter will 51 * cause the related events to not be seen. 52 * 53 * I915_RESET_UEVENT - Event is generated just before an attempt to reset the 54 * the GPU. The value supplied with the event is always 1. NOTE: Disable 55 * reset via module parameter will cause this event to not be seen. 56 */ 57 #define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR" 58 #define I915_ERROR_UEVENT "ERROR" 59 #define I915_RESET_UEVENT "RESET" 60 61 /* Each region is a minimum of 16k, and there are at most 255 of them. 62 */ 63 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use 64 * of chars for next/prev indices */ 65 #define I915_LOG_MIN_TEX_REGION_SIZE 14 66 67 typedef struct _drm_i915_init { 68 enum { 69 I915_INIT_DMA = 0x01, 70 I915_CLEANUP_DMA = 0x02, 71 I915_RESUME_DMA = 0x03 72 } func; 73 unsigned int mmio_offset; 74 int sarea_priv_offset; 75 unsigned int ring_start; 76 unsigned int ring_end; 77 unsigned int ring_size; 78 unsigned int front_offset; 79 unsigned int back_offset; 80 unsigned int depth_offset; 81 unsigned int w; 82 unsigned int h; 83 unsigned int pitch; 84 unsigned int pitch_bits; 85 unsigned int back_pitch; 86 unsigned int depth_pitch; 87 unsigned int cpp; 88 unsigned int chipset; 89 } drm_i915_init_t; 90 91 typedef struct _drm_i915_sarea { 92 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 93 int last_upload; /* last time texture was uploaded */ 94 int last_enqueue; /* last time a buffer was enqueued */ 95 int last_dispatch; /* age of the most recently dispatched buffer */ 96 int ctxOwner; /* last context to upload state */ 97 int texAge; 98 int pf_enabled; /* is pageflipping allowed? */ 99 int pf_active; 100 int pf_current_page; /* which buffer is being displayed? */ 101 int perf_boxes; /* performance boxes to be displayed */ 102 int width, height; /* screen size in pixels */ 103 104 drm_handle_t front_handle; 105 int front_offset; 106 int front_size; 107 108 drm_handle_t back_handle; 109 int back_offset; 110 int back_size; 111 112 drm_handle_t depth_handle; 113 int depth_offset; 114 int depth_size; 115 116 drm_handle_t tex_handle; 117 int tex_offset; 118 int tex_size; 119 int log_tex_granularity; 120 int pitch; 121 int rotation; /* 0, 90, 180 or 270 */ 122 int rotated_offset; 123 int rotated_size; 124 int rotated_pitch; 125 int virtualX, virtualY; 126 127 unsigned int front_tiled; 128 unsigned int back_tiled; 129 unsigned int depth_tiled; 130 unsigned int rotated_tiled; 131 unsigned int rotated2_tiled; 132 133 int pipeA_x; 134 int pipeA_y; 135 int pipeA_w; 136 int pipeA_h; 137 int pipeB_x; 138 int pipeB_y; 139 int pipeB_w; 140 int pipeB_h; 141 142 /* fill out some space for old userspace triple buffer */ 143 drm_handle_t unused_handle; 144 __u32 unused1, unused2, unused3; 145 146 /* buffer object handles for static buffers. May change 147 * over the lifetime of the client. 148 */ 149 __u32 front_bo_handle; 150 __u32 back_bo_handle; 151 __u32 unused_bo_handle; 152 __u32 depth_bo_handle; 153 154 } drm_i915_sarea_t; 155 156 /* due to userspace building against these headers we need some compat here */ 157 #define planeA_x pipeA_x 158 #define planeA_y pipeA_y 159 #define planeA_w pipeA_w 160 #define planeA_h pipeA_h 161 #define planeB_x pipeB_x 162 #define planeB_y pipeB_y 163 #define planeB_w pipeB_w 164 #define planeB_h pipeB_h 165 166 /* Flags for perf_boxes 167 */ 168 #define I915_BOX_RING_EMPTY 0x1 169 #define I915_BOX_FLIP 0x2 170 #define I915_BOX_WAIT 0x4 171 #define I915_BOX_TEXTURE_LOAD 0x8 172 #define I915_BOX_LOST_CONTEXT 0x10 173 174 /* I915 specific ioctls 175 * The device specific ioctl range is 0x40 to 0x79. 176 */ 177 #define DRM_I915_INIT 0x00 178 #define DRM_I915_FLUSH 0x01 179 #define DRM_I915_FLIP 0x02 180 #define DRM_I915_BATCHBUFFER 0x03 181 #define DRM_I915_IRQ_EMIT 0x04 182 #define DRM_I915_IRQ_WAIT 0x05 183 #define DRM_I915_GETPARAM 0x06 184 #define DRM_I915_SETPARAM 0x07 185 #define DRM_I915_ALLOC 0x08 186 #define DRM_I915_FREE 0x09 187 #define DRM_I915_INIT_HEAP 0x0a 188 #define DRM_I915_CMDBUFFER 0x0b 189 #define DRM_I915_DESTROY_HEAP 0x0c 190 #define DRM_I915_SET_VBLANK_PIPE 0x0d 191 #define DRM_I915_GET_VBLANK_PIPE 0x0e 192 #define DRM_I915_VBLANK_SWAP 0x0f 193 #define DRM_I915_HWS_ADDR 0x11 194 #define DRM_I915_GEM_INIT 0x13 195 #define DRM_I915_GEM_EXECBUFFER 0x14 196 #define DRM_I915_GEM_PIN 0x15 197 #define DRM_I915_GEM_UNPIN 0x16 198 #define DRM_I915_GEM_BUSY 0x17 199 #define DRM_I915_GEM_THROTTLE 0x18 200 #define DRM_I915_GEM_ENTERVT 0x19 201 #define DRM_I915_GEM_LEAVEVT 0x1a 202 #define DRM_I915_GEM_CREATE 0x1b 203 #define DRM_I915_GEM_PREAD 0x1c 204 #define DRM_I915_GEM_PWRITE 0x1d 205 #define DRM_I915_GEM_MMAP 0x1e 206 #define DRM_I915_GEM_SET_DOMAIN 0x1f 207 #define DRM_I915_GEM_SW_FINISH 0x20 208 #define DRM_I915_GEM_SET_TILING 0x21 209 #define DRM_I915_GEM_GET_TILING 0x22 210 #define DRM_I915_GEM_GET_APERTURE 0x23 211 #define DRM_I915_GEM_MMAP_GTT 0x24 212 #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 213 #define DRM_I915_GEM_MADVISE 0x26 214 #define DRM_I915_OVERLAY_PUT_IMAGE 0x27 215 #define DRM_I915_OVERLAY_ATTRS 0x28 216 #define DRM_I915_GEM_EXECBUFFER2 0x29 217 #define DRM_I915_GET_SPRITE_COLORKEY 0x2a 218 #define DRM_I915_SET_SPRITE_COLORKEY 0x2b 219 #define DRM_I915_GEM_WAIT 0x2c 220 #define DRM_I915_GEM_CONTEXT_CREATE 0x2d 221 #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e 222 #define DRM_I915_GEM_SET_CACHING 0x2f 223 #define DRM_I915_GEM_GET_CACHING 0x30 224 #define DRM_I915_REG_READ 0x31 225 #define DRM_I915_GET_RESET_STATS 0x32 226 #define DRM_I915_GEM_USERPTR 0x33 227 #define DRM_I915_GEM_CONTEXT_GETPARAM 0x34 228 #define DRM_I915_GEM_CONTEXT_SETPARAM 0x35 229 230 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 231 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 232 #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) 233 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 234 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 235 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 236 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 237 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 238 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 239 #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 240 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 241 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 242 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 243 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 244 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 245 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 246 #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) 247 #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 248 #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 249 #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 250 #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 251 #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 252 #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 253 #define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) 254 #define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) 255 #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 256 #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 257 #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 258 #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 259 #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 260 #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 261 #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 262 #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 263 #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 264 #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 265 #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 266 #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 267 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 268 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 269 #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 270 #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) 271 #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 272 #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 273 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 274 #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) 275 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) 276 #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) 277 #define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) 278 #define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats) 279 #define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr) 280 #define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param) 281 #define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param) 282 283 /* Allow drivers to submit batchbuffers directly to hardware, relying 284 * on the security mechanisms provided by hardware. 285 */ 286 typedef struct drm_i915_batchbuffer { 287 int start; /* agp offset */ 288 int used; /* nr bytes in use */ 289 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 290 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 291 int num_cliprects; /* mulitpass with multiple cliprects? */ 292 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 293 } drm_i915_batchbuffer_t; 294 295 /* As above, but pass a pointer to userspace buffer which can be 296 * validated by the kernel prior to sending to hardware. 297 */ 298 typedef struct _drm_i915_cmdbuffer { 299 char __user *buf; /* pointer to userspace command buffer */ 300 int sz; /* nr bytes in buf */ 301 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 302 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 303 int num_cliprects; /* mulitpass with multiple cliprects? */ 304 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 305 } drm_i915_cmdbuffer_t; 306 307 /* Userspace can request & wait on irq's: 308 */ 309 typedef struct drm_i915_irq_emit { 310 int __user *irq_seq; 311 } drm_i915_irq_emit_t; 312 313 typedef struct drm_i915_irq_wait { 314 int irq_seq; 315 } drm_i915_irq_wait_t; 316 317 /* Ioctl to query kernel params: 318 */ 319 #define I915_PARAM_IRQ_ACTIVE 1 320 #define I915_PARAM_ALLOW_BATCHBUFFER 2 321 #define I915_PARAM_LAST_DISPATCH 3 322 #define I915_PARAM_CHIPSET_ID 4 323 #define I915_PARAM_HAS_GEM 5 324 #define I915_PARAM_NUM_FENCES_AVAIL 6 325 #define I915_PARAM_HAS_OVERLAY 7 326 #define I915_PARAM_HAS_PAGEFLIPPING 8 327 #define I915_PARAM_HAS_EXECBUF2 9 328 #define I915_PARAM_HAS_BSD 10 329 #define I915_PARAM_HAS_BLT 11 330 #define I915_PARAM_HAS_RELAXED_FENCING 12 331 #define I915_PARAM_HAS_COHERENT_RINGS 13 332 #define I915_PARAM_HAS_EXEC_CONSTANTS 14 333 #define I915_PARAM_HAS_RELAXED_DELTA 15 334 #define I915_PARAM_HAS_GEN7_SOL_RESET 16 335 #define I915_PARAM_HAS_LLC 17 336 #define I915_PARAM_HAS_ALIASING_PPGTT 18 337 #define I915_PARAM_HAS_WAIT_TIMEOUT 19 338 #define I915_PARAM_HAS_SEMAPHORES 20 339 #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 340 #define I915_PARAM_HAS_VEBOX 22 341 #define I915_PARAM_HAS_SECURE_BATCHES 23 342 #define I915_PARAM_HAS_PINNED_BATCHES 24 343 #define I915_PARAM_HAS_EXEC_NO_RELOC 25 344 #define I915_PARAM_HAS_EXEC_HANDLE_LUT 26 345 #define I915_PARAM_HAS_WT 27 346 #define I915_PARAM_CMD_PARSER_VERSION 28 347 #define I915_PARAM_HAS_COHERENT_PHYS_GTT 29 348 #define I915_PARAM_MMAP_VERSION 30 349 #define I915_PARAM_HAS_BSD2 31 350 351 typedef struct drm_i915_getparam { 352 int param; 353 int __user *value; 354 } drm_i915_getparam_t; 355 356 /* Ioctl to set kernel params: 357 */ 358 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 359 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 360 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 361 #define I915_SETPARAM_NUM_USED_FENCES 4 362 363 typedef struct drm_i915_setparam { 364 int param; 365 int value; 366 } drm_i915_setparam_t; 367 368 /* A memory manager for regions of shared memory: 369 */ 370 #define I915_MEM_REGION_AGP 1 371 372 typedef struct drm_i915_mem_alloc { 373 int region; 374 int alignment; 375 int size; 376 int __user *region_offset; /* offset from start of fb or agp */ 377 } drm_i915_mem_alloc_t; 378 379 typedef struct drm_i915_mem_free { 380 int region; 381 int region_offset; 382 } drm_i915_mem_free_t; 383 384 typedef struct drm_i915_mem_init_heap { 385 int region; 386 int size; 387 int start; 388 } drm_i915_mem_init_heap_t; 389 390 /* Allow memory manager to be torn down and re-initialized (eg on 391 * rotate): 392 */ 393 typedef struct drm_i915_mem_destroy_heap { 394 int region; 395 } drm_i915_mem_destroy_heap_t; 396 397 /* Allow X server to configure which pipes to monitor for vblank signals 398 */ 399 #define DRM_I915_VBLANK_PIPE_A 1 400 #define DRM_I915_VBLANK_PIPE_B 2 401 402 typedef struct drm_i915_vblank_pipe { 403 int pipe; 404 } drm_i915_vblank_pipe_t; 405 406 /* Schedule buffer swap at given vertical blank: 407 */ 408 typedef struct drm_i915_vblank_swap { 409 drm_drawable_t drawable; 410 enum drm_vblank_seq_type seqtype; 411 unsigned int sequence; 412 } drm_i915_vblank_swap_t; 413 414 typedef struct drm_i915_hws_addr { 415 __u64 addr; 416 } drm_i915_hws_addr_t; 417 418 struct drm_i915_gem_init { 419 /** 420 * Beginning offset in the GTT to be managed by the DRM memory 421 * manager. 422 */ 423 __u64 gtt_start; 424 /** 425 * Ending offset in the GTT to be managed by the DRM memory 426 * manager. 427 */ 428 __u64 gtt_end; 429 }; 430 431 struct drm_i915_gem_create { 432 /** 433 * Requested size for the object. 434 * 435 * The (page-aligned) allocated size for the object will be returned. 436 */ 437 __u64 size; 438 /** 439 * Returned handle for the object. 440 * 441 * Object handles are nonzero. 442 */ 443 __u32 handle; 444 __u32 pad; 445 }; 446 447 struct drm_i915_gem_pread { 448 /** Handle for the object being read. */ 449 __u32 handle; 450 __u32 pad; 451 /** Offset into the object to read from */ 452 __u64 offset; 453 /** Length of data to read */ 454 __u64 size; 455 /** 456 * Pointer to write the data into. 457 * 458 * This is a fixed-size type for 32/64 compatibility. 459 */ 460 __u64 data_ptr; 461 }; 462 463 struct drm_i915_gem_pwrite { 464 /** Handle for the object being written to. */ 465 __u32 handle; 466 __u32 pad; 467 /** Offset into the object to write to */ 468 __u64 offset; 469 /** Length of data to write */ 470 __u64 size; 471 /** 472 * Pointer to read the data from. 473 * 474 * This is a fixed-size type for 32/64 compatibility. 475 */ 476 __u64 data_ptr; 477 }; 478 479 struct drm_i915_gem_mmap { 480 /** Handle for the object being mapped. */ 481 __u32 handle; 482 __u32 pad; 483 /** Offset in the object to map. */ 484 __u64 offset; 485 /** 486 * Length of data to map. 487 * 488 * The value will be page-aligned. 489 */ 490 __u64 size; 491 /** 492 * Returned pointer the data was mapped at. 493 * 494 * This is a fixed-size type for 32/64 compatibility. 495 */ 496 __u64 addr_ptr; 497 498 /** 499 * Flags for extended behaviour. 500 * 501 * Added in version 2. 502 */ 503 __u64 flags; 504 #define I915_MMAP_WC 0x1 505 }; 506 507 struct drm_i915_gem_mmap_gtt { 508 /** Handle for the object being mapped. */ 509 __u32 handle; 510 __u32 pad; 511 /** 512 * Fake offset to use for subsequent mmap call 513 * 514 * This is a fixed-size type for 32/64 compatibility. 515 */ 516 __u64 offset; 517 }; 518 519 struct drm_i915_gem_set_domain { 520 /** Handle for the object */ 521 __u32 handle; 522 523 /** New read domains */ 524 __u32 read_domains; 525 526 /** New write domain */ 527 __u32 write_domain; 528 }; 529 530 struct drm_i915_gem_sw_finish { 531 /** Handle for the object */ 532 __u32 handle; 533 }; 534 535 struct drm_i915_gem_relocation_entry { 536 /** 537 * Handle of the buffer being pointed to by this relocation entry. 538 * 539 * It's appealing to make this be an index into the mm_validate_entry 540 * list to refer to the buffer, but this allows the driver to create 541 * a relocation list for state buffers and not re-write it per 542 * exec using the buffer. 543 */ 544 __u32 target_handle; 545 546 /** 547 * Value to be added to the offset of the target buffer to make up 548 * the relocation entry. 549 */ 550 __u32 delta; 551 552 /** Offset in the buffer the relocation entry will be written into */ 553 __u64 offset; 554 555 /** 556 * Offset value of the target buffer that the relocation entry was last 557 * written as. 558 * 559 * If the buffer has the same offset as last time, we can skip syncing 560 * and writing the relocation. This value is written back out by 561 * the execbuffer ioctl when the relocation is written. 562 */ 563 __u64 presumed_offset; 564 565 /** 566 * Target memory domains read by this operation. 567 */ 568 __u32 read_domains; 569 570 /** 571 * Target memory domains written by this operation. 572 * 573 * Note that only one domain may be written by the whole 574 * execbuffer operation, so that where there are conflicts, 575 * the application will get -EINVAL back. 576 */ 577 __u32 write_domain; 578 }; 579 580 /** @{ 581 * Intel memory domains 582 * 583 * Most of these just align with the various caches in 584 * the system and are used to flush and invalidate as 585 * objects end up cached in different domains. 586 */ 587 /** CPU cache */ 588 #define I915_GEM_DOMAIN_CPU 0x00000001 589 /** Render cache, used by 2D and 3D drawing */ 590 #define I915_GEM_DOMAIN_RENDER 0x00000002 591 /** Sampler cache, used by texture engine */ 592 #define I915_GEM_DOMAIN_SAMPLER 0x00000004 593 /** Command queue, used to load batch buffers */ 594 #define I915_GEM_DOMAIN_COMMAND 0x00000008 595 /** Instruction cache, used by shader programs */ 596 #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 597 /** Vertex address cache */ 598 #define I915_GEM_DOMAIN_VERTEX 0x00000020 599 /** GTT domain - aperture and scanout */ 600 #define I915_GEM_DOMAIN_GTT 0x00000040 601 /** @} */ 602 603 struct drm_i915_gem_exec_object { 604 /** 605 * User's handle for a buffer to be bound into the GTT for this 606 * operation. 607 */ 608 __u32 handle; 609 610 /** Number of relocations to be performed on this buffer */ 611 __u32 relocation_count; 612 /** 613 * Pointer to array of struct drm_i915_gem_relocation_entry containing 614 * the relocations to be performed in this buffer. 615 */ 616 __u64 relocs_ptr; 617 618 /** Required alignment in graphics aperture */ 619 __u64 alignment; 620 621 /** 622 * Returned value of the updated offset of the object, for future 623 * presumed_offset writes. 624 */ 625 __u64 offset; 626 }; 627 628 struct drm_i915_gem_execbuffer { 629 /** 630 * List of buffers to be validated with their relocations to be 631 * performend on them. 632 * 633 * This is a pointer to an array of struct drm_i915_gem_validate_entry. 634 * 635 * These buffers must be listed in an order such that all relocations 636 * a buffer is performing refer to buffers that have already appeared 637 * in the validate list. 638 */ 639 __u64 buffers_ptr; 640 __u32 buffer_count; 641 642 /** Offset in the batchbuffer to start execution from. */ 643 __u32 batch_start_offset; 644 /** Bytes used in batchbuffer from batch_start_offset */ 645 __u32 batch_len; 646 __u32 DR1; 647 __u32 DR4; 648 __u32 num_cliprects; 649 /** This is a struct drm_clip_rect *cliprects */ 650 __u64 cliprects_ptr; 651 }; 652 653 struct drm_i915_gem_exec_object2 { 654 /** 655 * User's handle for a buffer to be bound into the GTT for this 656 * operation. 657 */ 658 __u32 handle; 659 660 /** Number of relocations to be performed on this buffer */ 661 __u32 relocation_count; 662 /** 663 * Pointer to array of struct drm_i915_gem_relocation_entry containing 664 * the relocations to be performed in this buffer. 665 */ 666 __u64 relocs_ptr; 667 668 /** Required alignment in graphics aperture */ 669 __u64 alignment; 670 671 /** 672 * Returned value of the updated offset of the object, for future 673 * presumed_offset writes. 674 */ 675 __u64 offset; 676 677 #define EXEC_OBJECT_NEEDS_FENCE (1<<0) 678 #define EXEC_OBJECT_NEEDS_GTT (1<<1) 679 #define EXEC_OBJECT_WRITE (1<<2) 680 #define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_WRITE<<1) 681 __u64 flags; 682 683 __u64 rsvd1; 684 __u64 rsvd2; 685 }; 686 687 struct drm_i915_gem_execbuffer2 { 688 /** 689 * List of gem_exec_object2 structs 690 */ 691 __u64 buffers_ptr; 692 __u32 buffer_count; 693 694 /** Offset in the batchbuffer to start execution from. */ 695 __u32 batch_start_offset; 696 /** Bytes used in batchbuffer from batch_start_offset */ 697 __u32 batch_len; 698 __u32 DR1; 699 __u32 DR4; 700 __u32 num_cliprects; 701 /** This is a struct drm_clip_rect *cliprects */ 702 __u64 cliprects_ptr; 703 #define I915_EXEC_RING_MASK (7<<0) 704 #define I915_EXEC_DEFAULT (0<<0) 705 #define I915_EXEC_RENDER (1<<0) 706 #define I915_EXEC_BSD (2<<0) 707 #define I915_EXEC_BLT (3<<0) 708 #define I915_EXEC_VEBOX (4<<0) 709 710 /* Used for switching the constants addressing mode on gen4+ RENDER ring. 711 * Gen6+ only supports relative addressing to dynamic state (default) and 712 * absolute addressing. 713 * 714 * These flags are ignored for the BSD and BLT rings. 715 */ 716 #define I915_EXEC_CONSTANTS_MASK (3<<6) 717 #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ 718 #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) 719 #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ 720 __u64 flags; 721 __u64 rsvd1; /* now used for context info */ 722 __u64 rsvd2; 723 }; 724 725 /** Resets the SO write offset registers for transform feedback on gen7. */ 726 #define I915_EXEC_GEN7_SOL_RESET (1<<8) 727 728 /** Request a privileged ("secure") batch buffer. Note only available for 729 * DRM_ROOT_ONLY | DRM_MASTER processes. 730 */ 731 #define I915_EXEC_SECURE (1<<9) 732 733 /** Inform the kernel that the batch is and will always be pinned. This 734 * negates the requirement for a workaround to be performed to avoid 735 * an incoherent CS (such as can be found on 830/845). If this flag is 736 * not passed, the kernel will endeavour to make sure the batch is 737 * coherent with the CS before execution. If this flag is passed, 738 * userspace assumes the responsibility for ensuring the same. 739 */ 740 #define I915_EXEC_IS_PINNED (1<<10) 741 742 /** Provide a hint to the kernel that the command stream and auxiliary 743 * state buffers already holds the correct presumed addresses and so the 744 * relocation process may be skipped if no buffers need to be moved in 745 * preparation for the execbuffer. 746 */ 747 #define I915_EXEC_NO_RELOC (1<<11) 748 749 /** Use the reloc.handle as an index into the exec object array rather 750 * than as the per-file handle. 751 */ 752 #define I915_EXEC_HANDLE_LUT (1<<12) 753 754 /** Used for switching BSD rings on the platforms with two BSD rings */ 755 #define I915_EXEC_BSD_MASK (3<<13) 756 #define I915_EXEC_BSD_DEFAULT (0<<13) /* default ping-pong mode */ 757 #define I915_EXEC_BSD_RING1 (1<<13) 758 #define I915_EXEC_BSD_RING2 (2<<13) 759 760 #define __I915_EXEC_UNKNOWN_FLAGS -(1<<15) 761 762 #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) 763 #define i915_execbuffer2_set_context_id(eb2, context) \ 764 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK 765 #define i915_execbuffer2_get_context_id(eb2) \ 766 ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) 767 768 struct drm_i915_gem_pin { 769 /** Handle of the buffer to be pinned. */ 770 __u32 handle; 771 __u32 pad; 772 773 /** alignment required within the aperture */ 774 __u64 alignment; 775 776 /** Returned GTT offset of the buffer. */ 777 __u64 offset; 778 }; 779 780 struct drm_i915_gem_unpin { 781 /** Handle of the buffer to be unpinned. */ 782 __u32 handle; 783 __u32 pad; 784 }; 785 786 struct drm_i915_gem_busy { 787 /** Handle of the buffer to check for busy */ 788 __u32 handle; 789 790 /** Return busy status (1 if busy, 0 if idle). 791 * The high word is used to indicate on which rings the object 792 * currently resides: 793 * 16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc) 794 */ 795 __u32 busy; 796 }; 797 798 /** 799 * I915_CACHING_NONE 800 * 801 * GPU access is not coherent with cpu caches. Default for machines without an 802 * LLC. 803 */ 804 #define I915_CACHING_NONE 0 805 /** 806 * I915_CACHING_CACHED 807 * 808 * GPU access is coherent with cpu caches and furthermore the data is cached in 809 * last-level caches shared between cpu cores and the gpu GT. Default on 810 * machines with HAS_LLC. 811 */ 812 #define I915_CACHING_CACHED 1 813 /** 814 * I915_CACHING_DISPLAY 815 * 816 * Special GPU caching mode which is coherent with the scanout engines. 817 * Transparently falls back to I915_CACHING_NONE on platforms where no special 818 * cache mode (like write-through or gfdt flushing) is available. The kernel 819 * automatically sets this mode when using a buffer as a scanout target. 820 * Userspace can manually set this mode to avoid a costly stall and clflush in 821 * the hotpath of drawing the first frame. 822 */ 823 #define I915_CACHING_DISPLAY 2 824 825 struct drm_i915_gem_caching { 826 /** 827 * Handle of the buffer to set/get the caching level of. */ 828 __u32 handle; 829 830 /** 831 * Cacheing level to apply or return value 832 * 833 * bits0-15 are for generic caching control (i.e. the above defined 834 * values). bits16-31 are reserved for platform-specific variations 835 * (e.g. l3$ caching on gen7). */ 836 __u32 caching; 837 }; 838 839 #define I915_TILING_NONE 0 840 #define I915_TILING_X 1 841 #define I915_TILING_Y 2 842 843 #define I915_BIT_6_SWIZZLE_NONE 0 844 #define I915_BIT_6_SWIZZLE_9 1 845 #define I915_BIT_6_SWIZZLE_9_10 2 846 #define I915_BIT_6_SWIZZLE_9_11 3 847 #define I915_BIT_6_SWIZZLE_9_10_11 4 848 /* Not seen by userland */ 849 #define I915_BIT_6_SWIZZLE_UNKNOWN 5 850 /* Seen by userland. */ 851 #define I915_BIT_6_SWIZZLE_9_17 6 852 #define I915_BIT_6_SWIZZLE_9_10_17 7 853 854 struct drm_i915_gem_set_tiling { 855 /** Handle of the buffer to have its tiling state updated */ 856 __u32 handle; 857 858 /** 859 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 860 * I915_TILING_Y). 861 * 862 * This value is to be set on request, and will be updated by the 863 * kernel on successful return with the actual chosen tiling layout. 864 * 865 * The tiling mode may be demoted to I915_TILING_NONE when the system 866 * has bit 6 swizzling that can't be managed correctly by GEM. 867 * 868 * Buffer contents become undefined when changing tiling_mode. 869 */ 870 __u32 tiling_mode; 871 872 /** 873 * Stride in bytes for the object when in I915_TILING_X or 874 * I915_TILING_Y. 875 */ 876 __u32 stride; 877 878 /** 879 * Returned address bit 6 swizzling required for CPU access through 880 * mmap mapping. 881 */ 882 __u32 swizzle_mode; 883 }; 884 885 struct drm_i915_gem_get_tiling { 886 /** Handle of the buffer to get tiling state for. */ 887 __u32 handle; 888 889 /** 890 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 891 * I915_TILING_Y). 892 */ 893 __u32 tiling_mode; 894 895 /** 896 * Returned address bit 6 swizzling required for CPU access through 897 * mmap mapping. 898 */ 899 __u32 swizzle_mode; 900 901 /** 902 * Returned address bit 6 swizzling required for CPU access through 903 * mmap mapping whilst bound. 904 */ 905 __u32 phys_swizzle_mode; 906 }; 907 908 struct drm_i915_gem_get_aperture { 909 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ 910 __u64 aper_size; 911 912 /** 913 * Available space in the aperture used by i915_gem_execbuffer, in 914 * bytes 915 */ 916 __u64 aper_available_size; 917 }; 918 919 struct drm_i915_get_pipe_from_crtc_id { 920 /** ID of CRTC being requested **/ 921 __u32 crtc_id; 922 923 /** pipe of requested CRTC **/ 924 __u32 pipe; 925 }; 926 927 #define I915_MADV_WILLNEED 0 928 #define I915_MADV_DONTNEED 1 929 #define __I915_MADV_PURGED 2 /* internal state */ 930 931 struct drm_i915_gem_madvise { 932 /** Handle of the buffer to change the backing store advice */ 933 __u32 handle; 934 935 /* Advice: either the buffer will be needed again in the near future, 936 * or wont be and could be discarded under memory pressure. 937 */ 938 __u32 madv; 939 940 /** Whether the backing store still exists. */ 941 __u32 retained; 942 }; 943 944 /* flags */ 945 #define I915_OVERLAY_TYPE_MASK 0xff 946 #define I915_OVERLAY_YUV_PLANAR 0x01 947 #define I915_OVERLAY_YUV_PACKED 0x02 948 #define I915_OVERLAY_RGB 0x03 949 950 #define I915_OVERLAY_DEPTH_MASK 0xff00 951 #define I915_OVERLAY_RGB24 0x1000 952 #define I915_OVERLAY_RGB16 0x2000 953 #define I915_OVERLAY_RGB15 0x3000 954 #define I915_OVERLAY_YUV422 0x0100 955 #define I915_OVERLAY_YUV411 0x0200 956 #define I915_OVERLAY_YUV420 0x0300 957 #define I915_OVERLAY_YUV410 0x0400 958 959 #define I915_OVERLAY_SWAP_MASK 0xff0000 960 #define I915_OVERLAY_NO_SWAP 0x000000 961 #define I915_OVERLAY_UV_SWAP 0x010000 962 #define I915_OVERLAY_Y_SWAP 0x020000 963 #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 964 965 #define I915_OVERLAY_FLAGS_MASK 0xff000000 966 #define I915_OVERLAY_ENABLE 0x01000000 967 968 struct drm_intel_overlay_put_image { 969 /* various flags and src format description */ 970 __u32 flags; 971 /* source picture description */ 972 __u32 bo_handle; 973 /* stride values and offsets are in bytes, buffer relative */ 974 __u16 stride_Y; /* stride for packed formats */ 975 __u16 stride_UV; 976 __u32 offset_Y; /* offset for packet formats */ 977 __u32 offset_U; 978 __u32 offset_V; 979 /* in pixels */ 980 __u16 src_width; 981 __u16 src_height; 982 /* to compensate the scaling factors for partially covered surfaces */ 983 __u16 src_scan_width; 984 __u16 src_scan_height; 985 /* output crtc description */ 986 __u32 crtc_id; 987 __u16 dst_x; 988 __u16 dst_y; 989 __u16 dst_width; 990 __u16 dst_height; 991 }; 992 993 /* flags */ 994 #define I915_OVERLAY_UPDATE_ATTRS (1<<0) 995 #define I915_OVERLAY_UPDATE_GAMMA (1<<1) 996 struct drm_intel_overlay_attrs { 997 __u32 flags; 998 __u32 color_key; 999 __s32 brightness; 1000 __u32 contrast; 1001 __u32 saturation; 1002 __u32 gamma0; 1003 __u32 gamma1; 1004 __u32 gamma2; 1005 __u32 gamma3; 1006 __u32 gamma4; 1007 __u32 gamma5; 1008 }; 1009 1010 /* 1011 * Intel sprite handling 1012 * 1013 * Color keying works with a min/mask/max tuple. Both source and destination 1014 * color keying is allowed. 1015 * 1016 * Source keying: 1017 * Sprite pixels within the min & max values, masked against the color channels 1018 * specified in the mask field, will be transparent. All other pixels will 1019 * be displayed on top of the primary plane. For RGB surfaces, only the min 1020 * and mask fields will be used; ranged compares are not allowed. 1021 * 1022 * Destination keying: 1023 * Primary plane pixels that match the min value, masked against the color 1024 * channels specified in the mask field, will be replaced by corresponding 1025 * pixels from the sprite plane. 1026 * 1027 * Note that source & destination keying are exclusive; only one can be 1028 * active on a given plane. 1029 */ 1030 1031 #define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */ 1032 #define I915_SET_COLORKEY_DESTINATION (1<<1) 1033 #define I915_SET_COLORKEY_SOURCE (1<<2) 1034 struct drm_intel_sprite_colorkey { 1035 __u32 plane_id; 1036 __u32 min_value; 1037 __u32 channel_mask; 1038 __u32 max_value; 1039 __u32 flags; 1040 }; 1041 1042 struct drm_i915_gem_wait { 1043 /** Handle of BO we shall wait on */ 1044 __u32 bo_handle; 1045 __u32 flags; 1046 /** Number of nanoseconds to wait, Returns time remaining. */ 1047 __s64 timeout_ns; 1048 }; 1049 1050 struct drm_i915_gem_context_create { 1051 /* output: id of new context*/ 1052 __u32 ctx_id; 1053 __u32 pad; 1054 }; 1055 1056 struct drm_i915_gem_context_destroy { 1057 __u32 ctx_id; 1058 __u32 pad; 1059 }; 1060 1061 struct drm_i915_reg_read { 1062 __u64 offset; 1063 __u64 val; /* Return value */ 1064 }; 1065 1066 struct drm_i915_reset_stats { 1067 __u32 ctx_id; 1068 __u32 flags; 1069 1070 /* All resets since boot/module reload, for all contexts */ 1071 __u32 reset_count; 1072 1073 /* Number of batches lost when active in GPU, for this context */ 1074 __u32 batch_active; 1075 1076 /* Number of batches lost pending for execution, for this context */ 1077 __u32 batch_pending; 1078 1079 __u32 pad; 1080 }; 1081 1082 struct drm_i915_gem_userptr { 1083 __u64 user_ptr; 1084 __u64 user_size; 1085 __u32 flags; 1086 #define I915_USERPTR_READ_ONLY 0x1 1087 #define I915_USERPTR_UNSYNCHRONIZED 0x80000000 1088 /** 1089 * Returned handle for the object. 1090 * 1091 * Object handles are nonzero. 1092 */ 1093 __u32 handle; 1094 }; 1095 1096 struct drm_i915_gem_context_param { 1097 __u32 ctx_id; 1098 __u32 size; 1099 __u64 param; 1100 #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1 1101 __u64 value; 1102 }; 1103 1104 #endif /* _UAPI_I915_DRM_H_ */ 1105