1 /* 2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 * 25 */ 26 27 #ifndef _UAPI_I915_DRM_H_ 28 #define _UAPI_I915_DRM_H_ 29 30 #include <drm/drm.h> 31 32 /* Please note that modifications to all structs defined here are 33 * subject to backwards-compatibility constraints. 34 */ 35 36 37 /* Each region is a minimum of 16k, and there are at most 255 of them. 38 */ 39 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use 40 * of chars for next/prev indices */ 41 #define I915_LOG_MIN_TEX_REGION_SIZE 14 42 43 typedef struct _drm_i915_init { 44 enum { 45 I915_INIT_DMA = 0x01, 46 I915_CLEANUP_DMA = 0x02, 47 I915_RESUME_DMA = 0x03 48 } func; 49 unsigned int mmio_offset; 50 int sarea_priv_offset; 51 unsigned int ring_start; 52 unsigned int ring_end; 53 unsigned int ring_size; 54 unsigned int front_offset; 55 unsigned int back_offset; 56 unsigned int depth_offset; 57 unsigned int w; 58 unsigned int h; 59 unsigned int pitch; 60 unsigned int pitch_bits; 61 unsigned int back_pitch; 62 unsigned int depth_pitch; 63 unsigned int cpp; 64 unsigned int chipset; 65 } drm_i915_init_t; 66 67 typedef struct _drm_i915_sarea { 68 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 69 int last_upload; /* last time texture was uploaded */ 70 int last_enqueue; /* last time a buffer was enqueued */ 71 int last_dispatch; /* age of the most recently dispatched buffer */ 72 int ctxOwner; /* last context to upload state */ 73 int texAge; 74 int pf_enabled; /* is pageflipping allowed? */ 75 int pf_active; 76 int pf_current_page; /* which buffer is being displayed? */ 77 int perf_boxes; /* performance boxes to be displayed */ 78 int width, height; /* screen size in pixels */ 79 80 drm_handle_t front_handle; 81 int front_offset; 82 int front_size; 83 84 drm_handle_t back_handle; 85 int back_offset; 86 int back_size; 87 88 drm_handle_t depth_handle; 89 int depth_offset; 90 int depth_size; 91 92 drm_handle_t tex_handle; 93 int tex_offset; 94 int tex_size; 95 int log_tex_granularity; 96 int pitch; 97 int rotation; /* 0, 90, 180 or 270 */ 98 int rotated_offset; 99 int rotated_size; 100 int rotated_pitch; 101 int virtualX, virtualY; 102 103 unsigned int front_tiled; 104 unsigned int back_tiled; 105 unsigned int depth_tiled; 106 unsigned int rotated_tiled; 107 unsigned int rotated2_tiled; 108 109 int pipeA_x; 110 int pipeA_y; 111 int pipeA_w; 112 int pipeA_h; 113 int pipeB_x; 114 int pipeB_y; 115 int pipeB_w; 116 int pipeB_h; 117 118 /* fill out some space for old userspace triple buffer */ 119 drm_handle_t unused_handle; 120 __u32 unused1, unused2, unused3; 121 122 /* buffer object handles for static buffers. May change 123 * over the lifetime of the client. 124 */ 125 __u32 front_bo_handle; 126 __u32 back_bo_handle; 127 __u32 unused_bo_handle; 128 __u32 depth_bo_handle; 129 130 } drm_i915_sarea_t; 131 132 /* due to userspace building against these headers we need some compat here */ 133 #define planeA_x pipeA_x 134 #define planeA_y pipeA_y 135 #define planeA_w pipeA_w 136 #define planeA_h pipeA_h 137 #define planeB_x pipeB_x 138 #define planeB_y pipeB_y 139 #define planeB_w pipeB_w 140 #define planeB_h pipeB_h 141 142 /* Flags for perf_boxes 143 */ 144 #define I915_BOX_RING_EMPTY 0x1 145 #define I915_BOX_FLIP 0x2 146 #define I915_BOX_WAIT 0x4 147 #define I915_BOX_TEXTURE_LOAD 0x8 148 #define I915_BOX_LOST_CONTEXT 0x10 149 150 /* I915 specific ioctls 151 * The device specific ioctl range is 0x40 to 0x79. 152 */ 153 #define DRM_I915_INIT 0x00 154 #define DRM_I915_FLUSH 0x01 155 #define DRM_I915_FLIP 0x02 156 #define DRM_I915_BATCHBUFFER 0x03 157 #define DRM_I915_IRQ_EMIT 0x04 158 #define DRM_I915_IRQ_WAIT 0x05 159 #define DRM_I915_GETPARAM 0x06 160 #define DRM_I915_SETPARAM 0x07 161 #define DRM_I915_ALLOC 0x08 162 #define DRM_I915_FREE 0x09 163 #define DRM_I915_INIT_HEAP 0x0a 164 #define DRM_I915_CMDBUFFER 0x0b 165 #define DRM_I915_DESTROY_HEAP 0x0c 166 #define DRM_I915_SET_VBLANK_PIPE 0x0d 167 #define DRM_I915_GET_VBLANK_PIPE 0x0e 168 #define DRM_I915_VBLANK_SWAP 0x0f 169 #define DRM_I915_HWS_ADDR 0x11 170 #define DRM_I915_GEM_INIT 0x13 171 #define DRM_I915_GEM_EXECBUFFER 0x14 172 #define DRM_I915_GEM_PIN 0x15 173 #define DRM_I915_GEM_UNPIN 0x16 174 #define DRM_I915_GEM_BUSY 0x17 175 #define DRM_I915_GEM_THROTTLE 0x18 176 #define DRM_I915_GEM_ENTERVT 0x19 177 #define DRM_I915_GEM_LEAVEVT 0x1a 178 #define DRM_I915_GEM_CREATE 0x1b 179 #define DRM_I915_GEM_PREAD 0x1c 180 #define DRM_I915_GEM_PWRITE 0x1d 181 #define DRM_I915_GEM_MMAP 0x1e 182 #define DRM_I915_GEM_SET_DOMAIN 0x1f 183 #define DRM_I915_GEM_SW_FINISH 0x20 184 #define DRM_I915_GEM_SET_TILING 0x21 185 #define DRM_I915_GEM_GET_TILING 0x22 186 #define DRM_I915_GEM_GET_APERTURE 0x23 187 #define DRM_I915_GEM_MMAP_GTT 0x24 188 #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 189 #define DRM_I915_GEM_MADVISE 0x26 190 #define DRM_I915_OVERLAY_PUT_IMAGE 0x27 191 #define DRM_I915_OVERLAY_ATTRS 0x28 192 #define DRM_I915_GEM_EXECBUFFER2 0x29 193 #define DRM_I915_GET_SPRITE_COLORKEY 0x2a 194 #define DRM_I915_SET_SPRITE_COLORKEY 0x2b 195 #define DRM_I915_GEM_WAIT 0x2c 196 #define DRM_I915_GEM_CONTEXT_CREATE 0x2d 197 #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e 198 #define DRM_I915_GEM_SET_CACHING 0x2f 199 #define DRM_I915_GEM_GET_CACHING 0x30 200 #define DRM_I915_REG_READ 0x31 201 202 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 203 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 204 #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) 205 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 206 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 207 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 208 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 209 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 210 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 211 #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 212 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 213 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 214 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 215 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 216 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 217 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 218 #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) 219 #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 220 #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 221 #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 222 #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 223 #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 224 #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 225 #define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) 226 #define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) 227 #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 228 #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 229 #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 230 #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 231 #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 232 #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 233 #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 234 #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 235 #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 236 #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 237 #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 238 #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 239 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 240 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 241 #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 242 #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) 243 #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 244 #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 245 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 246 #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) 247 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) 248 #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) 249 #define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) 250 251 /* Allow drivers to submit batchbuffers directly to hardware, relying 252 * on the security mechanisms provided by hardware. 253 */ 254 typedef struct drm_i915_batchbuffer { 255 int start; /* agp offset */ 256 int used; /* nr bytes in use */ 257 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 258 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 259 int num_cliprects; /* mulitpass with multiple cliprects? */ 260 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 261 } drm_i915_batchbuffer_t; 262 263 /* As above, but pass a pointer to userspace buffer which can be 264 * validated by the kernel prior to sending to hardware. 265 */ 266 typedef struct _drm_i915_cmdbuffer { 267 char __user *buf; /* pointer to userspace command buffer */ 268 int sz; /* nr bytes in buf */ 269 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 270 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 271 int num_cliprects; /* mulitpass with multiple cliprects? */ 272 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 273 } drm_i915_cmdbuffer_t; 274 275 /* Userspace can request & wait on irq's: 276 */ 277 typedef struct drm_i915_irq_emit { 278 int __user *irq_seq; 279 } drm_i915_irq_emit_t; 280 281 typedef struct drm_i915_irq_wait { 282 int irq_seq; 283 } drm_i915_irq_wait_t; 284 285 /* Ioctl to query kernel params: 286 */ 287 #define I915_PARAM_IRQ_ACTIVE 1 288 #define I915_PARAM_ALLOW_BATCHBUFFER 2 289 #define I915_PARAM_LAST_DISPATCH 3 290 #define I915_PARAM_CHIPSET_ID 4 291 #define I915_PARAM_HAS_GEM 5 292 #define I915_PARAM_NUM_FENCES_AVAIL 6 293 #define I915_PARAM_HAS_OVERLAY 7 294 #define I915_PARAM_HAS_PAGEFLIPPING 8 295 #define I915_PARAM_HAS_EXECBUF2 9 296 #define I915_PARAM_HAS_BSD 10 297 #define I915_PARAM_HAS_BLT 11 298 #define I915_PARAM_HAS_RELAXED_FENCING 12 299 #define I915_PARAM_HAS_COHERENT_RINGS 13 300 #define I915_PARAM_HAS_EXEC_CONSTANTS 14 301 #define I915_PARAM_HAS_RELAXED_DELTA 15 302 #define I915_PARAM_HAS_GEN7_SOL_RESET 16 303 #define I915_PARAM_HAS_LLC 17 304 #define I915_PARAM_HAS_ALIASING_PPGTT 18 305 #define I915_PARAM_HAS_WAIT_TIMEOUT 19 306 #define I915_PARAM_HAS_SEMAPHORES 20 307 #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 308 #define I915_PARAM_RSVD_FOR_FUTURE_USE 22 309 #define I915_PARAM_HAS_SECURE_BATCHES 23 310 #define I915_PARAM_HAS_PINNED_BATCHES 24 311 312 typedef struct drm_i915_getparam { 313 int param; 314 int __user *value; 315 } drm_i915_getparam_t; 316 317 /* Ioctl to set kernel params: 318 */ 319 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 320 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 321 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 322 #define I915_SETPARAM_NUM_USED_FENCES 4 323 324 typedef struct drm_i915_setparam { 325 int param; 326 int value; 327 } drm_i915_setparam_t; 328 329 /* A memory manager for regions of shared memory: 330 */ 331 #define I915_MEM_REGION_AGP 1 332 333 typedef struct drm_i915_mem_alloc { 334 int region; 335 int alignment; 336 int size; 337 int __user *region_offset; /* offset from start of fb or agp */ 338 } drm_i915_mem_alloc_t; 339 340 typedef struct drm_i915_mem_free { 341 int region; 342 int region_offset; 343 } drm_i915_mem_free_t; 344 345 typedef struct drm_i915_mem_init_heap { 346 int region; 347 int size; 348 int start; 349 } drm_i915_mem_init_heap_t; 350 351 /* Allow memory manager to be torn down and re-initialized (eg on 352 * rotate): 353 */ 354 typedef struct drm_i915_mem_destroy_heap { 355 int region; 356 } drm_i915_mem_destroy_heap_t; 357 358 /* Allow X server to configure which pipes to monitor for vblank signals 359 */ 360 #define DRM_I915_VBLANK_PIPE_A 1 361 #define DRM_I915_VBLANK_PIPE_B 2 362 363 typedef struct drm_i915_vblank_pipe { 364 int pipe; 365 } drm_i915_vblank_pipe_t; 366 367 /* Schedule buffer swap at given vertical blank: 368 */ 369 typedef struct drm_i915_vblank_swap { 370 drm_drawable_t drawable; 371 enum drm_vblank_seq_type seqtype; 372 unsigned int sequence; 373 } drm_i915_vblank_swap_t; 374 375 typedef struct drm_i915_hws_addr { 376 __u64 addr; 377 } drm_i915_hws_addr_t; 378 379 struct drm_i915_gem_init { 380 /** 381 * Beginning offset in the GTT to be managed by the DRM memory 382 * manager. 383 */ 384 __u64 gtt_start; 385 /** 386 * Ending offset in the GTT to be managed by the DRM memory 387 * manager. 388 */ 389 __u64 gtt_end; 390 }; 391 392 struct drm_i915_gem_create { 393 /** 394 * Requested size for the object. 395 * 396 * The (page-aligned) allocated size for the object will be returned. 397 */ 398 __u64 size; 399 /** 400 * Returned handle for the object. 401 * 402 * Object handles are nonzero. 403 */ 404 __u32 handle; 405 __u32 pad; 406 }; 407 408 struct drm_i915_gem_pread { 409 /** Handle for the object being read. */ 410 __u32 handle; 411 __u32 pad; 412 /** Offset into the object to read from */ 413 __u64 offset; 414 /** Length of data to read */ 415 __u64 size; 416 /** 417 * Pointer to write the data into. 418 * 419 * This is a fixed-size type for 32/64 compatibility. 420 */ 421 __u64 data_ptr; 422 }; 423 424 struct drm_i915_gem_pwrite { 425 /** Handle for the object being written to. */ 426 __u32 handle; 427 __u32 pad; 428 /** Offset into the object to write to */ 429 __u64 offset; 430 /** Length of data to write */ 431 __u64 size; 432 /** 433 * Pointer to read the data from. 434 * 435 * This is a fixed-size type for 32/64 compatibility. 436 */ 437 __u64 data_ptr; 438 }; 439 440 struct drm_i915_gem_mmap { 441 /** Handle for the object being mapped. */ 442 __u32 handle; 443 __u32 pad; 444 /** Offset in the object to map. */ 445 __u64 offset; 446 /** 447 * Length of data to map. 448 * 449 * The value will be page-aligned. 450 */ 451 __u64 size; 452 /** 453 * Returned pointer the data was mapped at. 454 * 455 * This is a fixed-size type for 32/64 compatibility. 456 */ 457 __u64 addr_ptr; 458 }; 459 460 struct drm_i915_gem_mmap_gtt { 461 /** Handle for the object being mapped. */ 462 __u32 handle; 463 __u32 pad; 464 /** 465 * Fake offset to use for subsequent mmap call 466 * 467 * This is a fixed-size type for 32/64 compatibility. 468 */ 469 __u64 offset; 470 }; 471 472 struct drm_i915_gem_set_domain { 473 /** Handle for the object */ 474 __u32 handle; 475 476 /** New read domains */ 477 __u32 read_domains; 478 479 /** New write domain */ 480 __u32 write_domain; 481 }; 482 483 struct drm_i915_gem_sw_finish { 484 /** Handle for the object */ 485 __u32 handle; 486 }; 487 488 struct drm_i915_gem_relocation_entry { 489 /** 490 * Handle of the buffer being pointed to by this relocation entry. 491 * 492 * It's appealing to make this be an index into the mm_validate_entry 493 * list to refer to the buffer, but this allows the driver to create 494 * a relocation list for state buffers and not re-write it per 495 * exec using the buffer. 496 */ 497 __u32 target_handle; 498 499 /** 500 * Value to be added to the offset of the target buffer to make up 501 * the relocation entry. 502 */ 503 __u32 delta; 504 505 /** Offset in the buffer the relocation entry will be written into */ 506 __u64 offset; 507 508 /** 509 * Offset value of the target buffer that the relocation entry was last 510 * written as. 511 * 512 * If the buffer has the same offset as last time, we can skip syncing 513 * and writing the relocation. This value is written back out by 514 * the execbuffer ioctl when the relocation is written. 515 */ 516 __u64 presumed_offset; 517 518 /** 519 * Target memory domains read by this operation. 520 */ 521 __u32 read_domains; 522 523 /** 524 * Target memory domains written by this operation. 525 * 526 * Note that only one domain may be written by the whole 527 * execbuffer operation, so that where there are conflicts, 528 * the application will get -EINVAL back. 529 */ 530 __u32 write_domain; 531 }; 532 533 /** @{ 534 * Intel memory domains 535 * 536 * Most of these just align with the various caches in 537 * the system and are used to flush and invalidate as 538 * objects end up cached in different domains. 539 */ 540 /** CPU cache */ 541 #define I915_GEM_DOMAIN_CPU 0x00000001 542 /** Render cache, used by 2D and 3D drawing */ 543 #define I915_GEM_DOMAIN_RENDER 0x00000002 544 /** Sampler cache, used by texture engine */ 545 #define I915_GEM_DOMAIN_SAMPLER 0x00000004 546 /** Command queue, used to load batch buffers */ 547 #define I915_GEM_DOMAIN_COMMAND 0x00000008 548 /** Instruction cache, used by shader programs */ 549 #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 550 /** Vertex address cache */ 551 #define I915_GEM_DOMAIN_VERTEX 0x00000020 552 /** GTT domain - aperture and scanout */ 553 #define I915_GEM_DOMAIN_GTT 0x00000040 554 /** @} */ 555 556 struct drm_i915_gem_exec_object { 557 /** 558 * User's handle for a buffer to be bound into the GTT for this 559 * operation. 560 */ 561 __u32 handle; 562 563 /** Number of relocations to be performed on this buffer */ 564 __u32 relocation_count; 565 /** 566 * Pointer to array of struct drm_i915_gem_relocation_entry containing 567 * the relocations to be performed in this buffer. 568 */ 569 __u64 relocs_ptr; 570 571 /** Required alignment in graphics aperture */ 572 __u64 alignment; 573 574 /** 575 * Returned value of the updated offset of the object, for future 576 * presumed_offset writes. 577 */ 578 __u64 offset; 579 }; 580 581 struct drm_i915_gem_execbuffer { 582 /** 583 * List of buffers to be validated with their relocations to be 584 * performend on them. 585 * 586 * This is a pointer to an array of struct drm_i915_gem_validate_entry. 587 * 588 * These buffers must be listed in an order such that all relocations 589 * a buffer is performing refer to buffers that have already appeared 590 * in the validate list. 591 */ 592 __u64 buffers_ptr; 593 __u32 buffer_count; 594 595 /** Offset in the batchbuffer to start execution from. */ 596 __u32 batch_start_offset; 597 /** Bytes used in batchbuffer from batch_start_offset */ 598 __u32 batch_len; 599 __u32 DR1; 600 __u32 DR4; 601 __u32 num_cliprects; 602 /** This is a struct drm_clip_rect *cliprects */ 603 __u64 cliprects_ptr; 604 }; 605 606 struct drm_i915_gem_exec_object2 { 607 /** 608 * User's handle for a buffer to be bound into the GTT for this 609 * operation. 610 */ 611 __u32 handle; 612 613 /** Number of relocations to be performed on this buffer */ 614 __u32 relocation_count; 615 /** 616 * Pointer to array of struct drm_i915_gem_relocation_entry containing 617 * the relocations to be performed in this buffer. 618 */ 619 __u64 relocs_ptr; 620 621 /** Required alignment in graphics aperture */ 622 __u64 alignment; 623 624 /** 625 * Returned value of the updated offset of the object, for future 626 * presumed_offset writes. 627 */ 628 __u64 offset; 629 630 #define EXEC_OBJECT_NEEDS_FENCE (1<<0) 631 __u64 flags; 632 __u64 rsvd1; 633 __u64 rsvd2; 634 }; 635 636 struct drm_i915_gem_execbuffer2 { 637 /** 638 * List of gem_exec_object2 structs 639 */ 640 __u64 buffers_ptr; 641 __u32 buffer_count; 642 643 /** Offset in the batchbuffer to start execution from. */ 644 __u32 batch_start_offset; 645 /** Bytes used in batchbuffer from batch_start_offset */ 646 __u32 batch_len; 647 __u32 DR1; 648 __u32 DR4; 649 __u32 num_cliprects; 650 /** This is a struct drm_clip_rect *cliprects */ 651 __u64 cliprects_ptr; 652 #define I915_EXEC_RING_MASK (7<<0) 653 #define I915_EXEC_DEFAULT (0<<0) 654 #define I915_EXEC_RENDER (1<<0) 655 #define I915_EXEC_BSD (2<<0) 656 #define I915_EXEC_BLT (3<<0) 657 658 /* Used for switching the constants addressing mode on gen4+ RENDER ring. 659 * Gen6+ only supports relative addressing to dynamic state (default) and 660 * absolute addressing. 661 * 662 * These flags are ignored for the BSD and BLT rings. 663 */ 664 #define I915_EXEC_CONSTANTS_MASK (3<<6) 665 #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ 666 #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) 667 #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ 668 __u64 flags; 669 __u64 rsvd1; /* now used for context info */ 670 __u64 rsvd2; 671 }; 672 673 /** Resets the SO write offset registers for transform feedback on gen7. */ 674 #define I915_EXEC_GEN7_SOL_RESET (1<<8) 675 676 /** Request a privileged ("secure") batch buffer. Note only available for 677 * DRM_ROOT_ONLY | DRM_MASTER processes. 678 */ 679 #define I915_EXEC_SECURE (1<<9) 680 681 /** Inform the kernel that the batch is and will always be pinned. This 682 * negates the requirement for a workaround to be performed to avoid 683 * an incoherent CS (such as can be found on 830/845). If this flag is 684 * not passed, the kernel will endeavour to make sure the batch is 685 * coherent with the CS before execution. If this flag is passed, 686 * userspace assumes the responsibility for ensuring the same. 687 */ 688 #define I915_EXEC_IS_PINNED (1<<10) 689 690 #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) 691 #define i915_execbuffer2_set_context_id(eb2, context) \ 692 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK 693 #define i915_execbuffer2_get_context_id(eb2) \ 694 ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) 695 696 struct drm_i915_gem_pin { 697 /** Handle of the buffer to be pinned. */ 698 __u32 handle; 699 __u32 pad; 700 701 /** alignment required within the aperture */ 702 __u64 alignment; 703 704 /** Returned GTT offset of the buffer. */ 705 __u64 offset; 706 }; 707 708 struct drm_i915_gem_unpin { 709 /** Handle of the buffer to be unpinned. */ 710 __u32 handle; 711 __u32 pad; 712 }; 713 714 struct drm_i915_gem_busy { 715 /** Handle of the buffer to check for busy */ 716 __u32 handle; 717 718 /** Return busy status (1 if busy, 0 if idle). 719 * The high word is used to indicate on which rings the object 720 * currently resides: 721 * 16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc) 722 */ 723 __u32 busy; 724 }; 725 726 #define I915_CACHING_NONE 0 727 #define I915_CACHING_CACHED 1 728 729 struct drm_i915_gem_caching { 730 /** 731 * Handle of the buffer to set/get the caching level of. */ 732 __u32 handle; 733 734 /** 735 * Cacheing level to apply or return value 736 * 737 * bits0-15 are for generic caching control (i.e. the above defined 738 * values). bits16-31 are reserved for platform-specific variations 739 * (e.g. l3$ caching on gen7). */ 740 __u32 caching; 741 }; 742 743 #define I915_TILING_NONE 0 744 #define I915_TILING_X 1 745 #define I915_TILING_Y 2 746 747 #define I915_BIT_6_SWIZZLE_NONE 0 748 #define I915_BIT_6_SWIZZLE_9 1 749 #define I915_BIT_6_SWIZZLE_9_10 2 750 #define I915_BIT_6_SWIZZLE_9_11 3 751 #define I915_BIT_6_SWIZZLE_9_10_11 4 752 /* Not seen by userland */ 753 #define I915_BIT_6_SWIZZLE_UNKNOWN 5 754 /* Seen by userland. */ 755 #define I915_BIT_6_SWIZZLE_9_17 6 756 #define I915_BIT_6_SWIZZLE_9_10_17 7 757 758 struct drm_i915_gem_set_tiling { 759 /** Handle of the buffer to have its tiling state updated */ 760 __u32 handle; 761 762 /** 763 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 764 * I915_TILING_Y). 765 * 766 * This value is to be set on request, and will be updated by the 767 * kernel on successful return with the actual chosen tiling layout. 768 * 769 * The tiling mode may be demoted to I915_TILING_NONE when the system 770 * has bit 6 swizzling that can't be managed correctly by GEM. 771 * 772 * Buffer contents become undefined when changing tiling_mode. 773 */ 774 __u32 tiling_mode; 775 776 /** 777 * Stride in bytes for the object when in I915_TILING_X or 778 * I915_TILING_Y. 779 */ 780 __u32 stride; 781 782 /** 783 * Returned address bit 6 swizzling required for CPU access through 784 * mmap mapping. 785 */ 786 __u32 swizzle_mode; 787 }; 788 789 struct drm_i915_gem_get_tiling { 790 /** Handle of the buffer to get tiling state for. */ 791 __u32 handle; 792 793 /** 794 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 795 * I915_TILING_Y). 796 */ 797 __u32 tiling_mode; 798 799 /** 800 * Returned address bit 6 swizzling required for CPU access through 801 * mmap mapping. 802 */ 803 __u32 swizzle_mode; 804 }; 805 806 struct drm_i915_gem_get_aperture { 807 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ 808 __u64 aper_size; 809 810 /** 811 * Available space in the aperture used by i915_gem_execbuffer, in 812 * bytes 813 */ 814 __u64 aper_available_size; 815 }; 816 817 struct drm_i915_get_pipe_from_crtc_id { 818 /** ID of CRTC being requested **/ 819 __u32 crtc_id; 820 821 /** pipe of requested CRTC **/ 822 __u32 pipe; 823 }; 824 825 #define I915_MADV_WILLNEED 0 826 #define I915_MADV_DONTNEED 1 827 #define __I915_MADV_PURGED 2 /* internal state */ 828 829 struct drm_i915_gem_madvise { 830 /** Handle of the buffer to change the backing store advice */ 831 __u32 handle; 832 833 /* Advice: either the buffer will be needed again in the near future, 834 * or wont be and could be discarded under memory pressure. 835 */ 836 __u32 madv; 837 838 /** Whether the backing store still exists. */ 839 __u32 retained; 840 }; 841 842 /* flags */ 843 #define I915_OVERLAY_TYPE_MASK 0xff 844 #define I915_OVERLAY_YUV_PLANAR 0x01 845 #define I915_OVERLAY_YUV_PACKED 0x02 846 #define I915_OVERLAY_RGB 0x03 847 848 #define I915_OVERLAY_DEPTH_MASK 0xff00 849 #define I915_OVERLAY_RGB24 0x1000 850 #define I915_OVERLAY_RGB16 0x2000 851 #define I915_OVERLAY_RGB15 0x3000 852 #define I915_OVERLAY_YUV422 0x0100 853 #define I915_OVERLAY_YUV411 0x0200 854 #define I915_OVERLAY_YUV420 0x0300 855 #define I915_OVERLAY_YUV410 0x0400 856 857 #define I915_OVERLAY_SWAP_MASK 0xff0000 858 #define I915_OVERLAY_NO_SWAP 0x000000 859 #define I915_OVERLAY_UV_SWAP 0x010000 860 #define I915_OVERLAY_Y_SWAP 0x020000 861 #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 862 863 #define I915_OVERLAY_FLAGS_MASK 0xff000000 864 #define I915_OVERLAY_ENABLE 0x01000000 865 866 struct drm_intel_overlay_put_image { 867 /* various flags and src format description */ 868 __u32 flags; 869 /* source picture description */ 870 __u32 bo_handle; 871 /* stride values and offsets are in bytes, buffer relative */ 872 __u16 stride_Y; /* stride for packed formats */ 873 __u16 stride_UV; 874 __u32 offset_Y; /* offset for packet formats */ 875 __u32 offset_U; 876 __u32 offset_V; 877 /* in pixels */ 878 __u16 src_width; 879 __u16 src_height; 880 /* to compensate the scaling factors for partially covered surfaces */ 881 __u16 src_scan_width; 882 __u16 src_scan_height; 883 /* output crtc description */ 884 __u32 crtc_id; 885 __u16 dst_x; 886 __u16 dst_y; 887 __u16 dst_width; 888 __u16 dst_height; 889 }; 890 891 /* flags */ 892 #define I915_OVERLAY_UPDATE_ATTRS (1<<0) 893 #define I915_OVERLAY_UPDATE_GAMMA (1<<1) 894 struct drm_intel_overlay_attrs { 895 __u32 flags; 896 __u32 color_key; 897 __s32 brightness; 898 __u32 contrast; 899 __u32 saturation; 900 __u32 gamma0; 901 __u32 gamma1; 902 __u32 gamma2; 903 __u32 gamma3; 904 __u32 gamma4; 905 __u32 gamma5; 906 }; 907 908 /* 909 * Intel sprite handling 910 * 911 * Color keying works with a min/mask/max tuple. Both source and destination 912 * color keying is allowed. 913 * 914 * Source keying: 915 * Sprite pixels within the min & max values, masked against the color channels 916 * specified in the mask field, will be transparent. All other pixels will 917 * be displayed on top of the primary plane. For RGB surfaces, only the min 918 * and mask fields will be used; ranged compares are not allowed. 919 * 920 * Destination keying: 921 * Primary plane pixels that match the min value, masked against the color 922 * channels specified in the mask field, will be replaced by corresponding 923 * pixels from the sprite plane. 924 * 925 * Note that source & destination keying are exclusive; only one can be 926 * active on a given plane. 927 */ 928 929 #define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */ 930 #define I915_SET_COLORKEY_DESTINATION (1<<1) 931 #define I915_SET_COLORKEY_SOURCE (1<<2) 932 struct drm_intel_sprite_colorkey { 933 __u32 plane_id; 934 __u32 min_value; 935 __u32 channel_mask; 936 __u32 max_value; 937 __u32 flags; 938 }; 939 940 struct drm_i915_gem_wait { 941 /** Handle of BO we shall wait on */ 942 __u32 bo_handle; 943 __u32 flags; 944 /** Number of nanoseconds to wait, Returns time remaining. */ 945 __s64 timeout_ns; 946 }; 947 948 struct drm_i915_gem_context_create { 949 /* output: id of new context*/ 950 __u32 ctx_id; 951 __u32 pad; 952 }; 953 954 struct drm_i915_gem_context_destroy { 955 __u32 ctx_id; 956 __u32 pad; 957 }; 958 959 struct drm_i915_reg_read { 960 __u64 offset; 961 __u64 val; /* Return value */ 962 }; 963 #endif /* _UAPI_I915_DRM_H_ */ 964