1 /* 2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 * 25 */ 26 27 #ifndef _UAPI_I915_DRM_H_ 28 #define _UAPI_I915_DRM_H_ 29 30 #include <drm/drm.h> 31 32 /* Please note that modifications to all structs defined here are 33 * subject to backwards-compatibility constraints. 34 */ 35 36 /** 37 * DOC: uevents generated by i915 on it's device node 38 * 39 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch 40 * event from the gpu l3 cache. Additional information supplied is ROW, 41 * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep 42 * track of these events and if a specific cache-line seems to have a 43 * persistent error remap it with the l3 remapping tool supplied in 44 * intel-gpu-tools. The value supplied with the event is always 1. 45 * 46 * I915_ERROR_UEVENT - Generated upon error detection, currently only via 47 * hangcheck. The error detection event is a good indicator of when things 48 * began to go badly. The value supplied with the event is a 1 upon error 49 * detection, and a 0 upon reset completion, signifying no more error 50 * exists. NOTE: Disabling hangcheck or reset via module parameter will 51 * cause the related events to not be seen. 52 * 53 * I915_RESET_UEVENT - Event is generated just before an attempt to reset the 54 * the GPU. The value supplied with the event is always 1. NOTE: Disable 55 * reset via module parameter will cause this event to not be seen. 56 */ 57 #define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR" 58 #define I915_ERROR_UEVENT "ERROR" 59 #define I915_RESET_UEVENT "RESET" 60 61 /* Each region is a minimum of 16k, and there are at most 255 of them. 62 */ 63 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use 64 * of chars for next/prev indices */ 65 #define I915_LOG_MIN_TEX_REGION_SIZE 14 66 67 typedef struct _drm_i915_init { 68 enum { 69 I915_INIT_DMA = 0x01, 70 I915_CLEANUP_DMA = 0x02, 71 I915_RESUME_DMA = 0x03 72 } func; 73 unsigned int mmio_offset; 74 int sarea_priv_offset; 75 unsigned int ring_start; 76 unsigned int ring_end; 77 unsigned int ring_size; 78 unsigned int front_offset; 79 unsigned int back_offset; 80 unsigned int depth_offset; 81 unsigned int w; 82 unsigned int h; 83 unsigned int pitch; 84 unsigned int pitch_bits; 85 unsigned int back_pitch; 86 unsigned int depth_pitch; 87 unsigned int cpp; 88 unsigned int chipset; 89 } drm_i915_init_t; 90 91 typedef struct _drm_i915_sarea { 92 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 93 int last_upload; /* last time texture was uploaded */ 94 int last_enqueue; /* last time a buffer was enqueued */ 95 int last_dispatch; /* age of the most recently dispatched buffer */ 96 int ctxOwner; /* last context to upload state */ 97 int texAge; 98 int pf_enabled; /* is pageflipping allowed? */ 99 int pf_active; 100 int pf_current_page; /* which buffer is being displayed? */ 101 int perf_boxes; /* performance boxes to be displayed */ 102 int width, height; /* screen size in pixels */ 103 104 drm_handle_t front_handle; 105 int front_offset; 106 int front_size; 107 108 drm_handle_t back_handle; 109 int back_offset; 110 int back_size; 111 112 drm_handle_t depth_handle; 113 int depth_offset; 114 int depth_size; 115 116 drm_handle_t tex_handle; 117 int tex_offset; 118 int tex_size; 119 int log_tex_granularity; 120 int pitch; 121 int rotation; /* 0, 90, 180 or 270 */ 122 int rotated_offset; 123 int rotated_size; 124 int rotated_pitch; 125 int virtualX, virtualY; 126 127 unsigned int front_tiled; 128 unsigned int back_tiled; 129 unsigned int depth_tiled; 130 unsigned int rotated_tiled; 131 unsigned int rotated2_tiled; 132 133 int pipeA_x; 134 int pipeA_y; 135 int pipeA_w; 136 int pipeA_h; 137 int pipeB_x; 138 int pipeB_y; 139 int pipeB_w; 140 int pipeB_h; 141 142 /* fill out some space for old userspace triple buffer */ 143 drm_handle_t unused_handle; 144 __u32 unused1, unused2, unused3; 145 146 /* buffer object handles for static buffers. May change 147 * over the lifetime of the client. 148 */ 149 __u32 front_bo_handle; 150 __u32 back_bo_handle; 151 __u32 unused_bo_handle; 152 __u32 depth_bo_handle; 153 154 } drm_i915_sarea_t; 155 156 /* due to userspace building against these headers we need some compat here */ 157 #define planeA_x pipeA_x 158 #define planeA_y pipeA_y 159 #define planeA_w pipeA_w 160 #define planeA_h pipeA_h 161 #define planeB_x pipeB_x 162 #define planeB_y pipeB_y 163 #define planeB_w pipeB_w 164 #define planeB_h pipeB_h 165 166 /* Flags for perf_boxes 167 */ 168 #define I915_BOX_RING_EMPTY 0x1 169 #define I915_BOX_FLIP 0x2 170 #define I915_BOX_WAIT 0x4 171 #define I915_BOX_TEXTURE_LOAD 0x8 172 #define I915_BOX_LOST_CONTEXT 0x10 173 174 /* I915 specific ioctls 175 * The device specific ioctl range is 0x40 to 0x79. 176 */ 177 #define DRM_I915_INIT 0x00 178 #define DRM_I915_FLUSH 0x01 179 #define DRM_I915_FLIP 0x02 180 #define DRM_I915_BATCHBUFFER 0x03 181 #define DRM_I915_IRQ_EMIT 0x04 182 #define DRM_I915_IRQ_WAIT 0x05 183 #define DRM_I915_GETPARAM 0x06 184 #define DRM_I915_SETPARAM 0x07 185 #define DRM_I915_ALLOC 0x08 186 #define DRM_I915_FREE 0x09 187 #define DRM_I915_INIT_HEAP 0x0a 188 #define DRM_I915_CMDBUFFER 0x0b 189 #define DRM_I915_DESTROY_HEAP 0x0c 190 #define DRM_I915_SET_VBLANK_PIPE 0x0d 191 #define DRM_I915_GET_VBLANK_PIPE 0x0e 192 #define DRM_I915_VBLANK_SWAP 0x0f 193 #define DRM_I915_HWS_ADDR 0x11 194 #define DRM_I915_GEM_INIT 0x13 195 #define DRM_I915_GEM_EXECBUFFER 0x14 196 #define DRM_I915_GEM_PIN 0x15 197 #define DRM_I915_GEM_UNPIN 0x16 198 #define DRM_I915_GEM_BUSY 0x17 199 #define DRM_I915_GEM_THROTTLE 0x18 200 #define DRM_I915_GEM_ENTERVT 0x19 201 #define DRM_I915_GEM_LEAVEVT 0x1a 202 #define DRM_I915_GEM_CREATE 0x1b 203 #define DRM_I915_GEM_PREAD 0x1c 204 #define DRM_I915_GEM_PWRITE 0x1d 205 #define DRM_I915_GEM_MMAP 0x1e 206 #define DRM_I915_GEM_SET_DOMAIN 0x1f 207 #define DRM_I915_GEM_SW_FINISH 0x20 208 #define DRM_I915_GEM_SET_TILING 0x21 209 #define DRM_I915_GEM_GET_TILING 0x22 210 #define DRM_I915_GEM_GET_APERTURE 0x23 211 #define DRM_I915_GEM_MMAP_GTT 0x24 212 #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 213 #define DRM_I915_GEM_MADVISE 0x26 214 #define DRM_I915_OVERLAY_PUT_IMAGE 0x27 215 #define DRM_I915_OVERLAY_ATTRS 0x28 216 #define DRM_I915_GEM_EXECBUFFER2 0x29 217 #define DRM_I915_GET_SPRITE_COLORKEY 0x2a 218 #define DRM_I915_SET_SPRITE_COLORKEY 0x2b 219 #define DRM_I915_GEM_WAIT 0x2c 220 #define DRM_I915_GEM_CONTEXT_CREATE 0x2d 221 #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e 222 #define DRM_I915_GEM_SET_CACHING 0x2f 223 #define DRM_I915_GEM_GET_CACHING 0x30 224 #define DRM_I915_REG_READ 0x31 225 226 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 227 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 228 #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) 229 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 230 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 231 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 232 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 233 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 234 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 235 #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 236 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 237 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 238 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 239 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 240 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 241 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 242 #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) 243 #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 244 #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 245 #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 246 #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 247 #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 248 #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 249 #define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) 250 #define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) 251 #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 252 #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 253 #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 254 #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 255 #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 256 #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 257 #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 258 #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 259 #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 260 #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 261 #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 262 #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 263 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 264 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 265 #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 266 #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) 267 #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 268 #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 269 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 270 #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) 271 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) 272 #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) 273 #define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) 274 275 /* Allow drivers to submit batchbuffers directly to hardware, relying 276 * on the security mechanisms provided by hardware. 277 */ 278 typedef struct drm_i915_batchbuffer { 279 int start; /* agp offset */ 280 int used; /* nr bytes in use */ 281 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 282 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 283 int num_cliprects; /* mulitpass with multiple cliprects? */ 284 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 285 } drm_i915_batchbuffer_t; 286 287 /* As above, but pass a pointer to userspace buffer which can be 288 * validated by the kernel prior to sending to hardware. 289 */ 290 typedef struct _drm_i915_cmdbuffer { 291 char __user *buf; /* pointer to userspace command buffer */ 292 int sz; /* nr bytes in buf */ 293 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 294 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 295 int num_cliprects; /* mulitpass with multiple cliprects? */ 296 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 297 } drm_i915_cmdbuffer_t; 298 299 /* Userspace can request & wait on irq's: 300 */ 301 typedef struct drm_i915_irq_emit { 302 int __user *irq_seq; 303 } drm_i915_irq_emit_t; 304 305 typedef struct drm_i915_irq_wait { 306 int irq_seq; 307 } drm_i915_irq_wait_t; 308 309 /* Ioctl to query kernel params: 310 */ 311 #define I915_PARAM_IRQ_ACTIVE 1 312 #define I915_PARAM_ALLOW_BATCHBUFFER 2 313 #define I915_PARAM_LAST_DISPATCH 3 314 #define I915_PARAM_CHIPSET_ID 4 315 #define I915_PARAM_HAS_GEM 5 316 #define I915_PARAM_NUM_FENCES_AVAIL 6 317 #define I915_PARAM_HAS_OVERLAY 7 318 #define I915_PARAM_HAS_PAGEFLIPPING 8 319 #define I915_PARAM_HAS_EXECBUF2 9 320 #define I915_PARAM_HAS_BSD 10 321 #define I915_PARAM_HAS_BLT 11 322 #define I915_PARAM_HAS_RELAXED_FENCING 12 323 #define I915_PARAM_HAS_COHERENT_RINGS 13 324 #define I915_PARAM_HAS_EXEC_CONSTANTS 14 325 #define I915_PARAM_HAS_RELAXED_DELTA 15 326 #define I915_PARAM_HAS_GEN7_SOL_RESET 16 327 #define I915_PARAM_HAS_LLC 17 328 #define I915_PARAM_HAS_ALIASING_PPGTT 18 329 #define I915_PARAM_HAS_WAIT_TIMEOUT 19 330 #define I915_PARAM_HAS_SEMAPHORES 20 331 #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 332 #define I915_PARAM_HAS_VEBOX 22 333 #define I915_PARAM_HAS_SECURE_BATCHES 23 334 #define I915_PARAM_HAS_PINNED_BATCHES 24 335 #define I915_PARAM_HAS_EXEC_NO_RELOC 25 336 #define I915_PARAM_HAS_EXEC_HANDLE_LUT 26 337 #define I915_PARAM_HAS_WT 27 338 339 typedef struct drm_i915_getparam { 340 int param; 341 int __user *value; 342 } drm_i915_getparam_t; 343 344 /* Ioctl to set kernel params: 345 */ 346 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 347 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 348 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 349 #define I915_SETPARAM_NUM_USED_FENCES 4 350 351 typedef struct drm_i915_setparam { 352 int param; 353 int value; 354 } drm_i915_setparam_t; 355 356 /* A memory manager for regions of shared memory: 357 */ 358 #define I915_MEM_REGION_AGP 1 359 360 typedef struct drm_i915_mem_alloc { 361 int region; 362 int alignment; 363 int size; 364 int __user *region_offset; /* offset from start of fb or agp */ 365 } drm_i915_mem_alloc_t; 366 367 typedef struct drm_i915_mem_free { 368 int region; 369 int region_offset; 370 } drm_i915_mem_free_t; 371 372 typedef struct drm_i915_mem_init_heap { 373 int region; 374 int size; 375 int start; 376 } drm_i915_mem_init_heap_t; 377 378 /* Allow memory manager to be torn down and re-initialized (eg on 379 * rotate): 380 */ 381 typedef struct drm_i915_mem_destroy_heap { 382 int region; 383 } drm_i915_mem_destroy_heap_t; 384 385 /* Allow X server to configure which pipes to monitor for vblank signals 386 */ 387 #define DRM_I915_VBLANK_PIPE_A 1 388 #define DRM_I915_VBLANK_PIPE_B 2 389 390 typedef struct drm_i915_vblank_pipe { 391 int pipe; 392 } drm_i915_vblank_pipe_t; 393 394 /* Schedule buffer swap at given vertical blank: 395 */ 396 typedef struct drm_i915_vblank_swap { 397 drm_drawable_t drawable; 398 enum drm_vblank_seq_type seqtype; 399 unsigned int sequence; 400 } drm_i915_vblank_swap_t; 401 402 typedef struct drm_i915_hws_addr { 403 __u64 addr; 404 } drm_i915_hws_addr_t; 405 406 struct drm_i915_gem_init { 407 /** 408 * Beginning offset in the GTT to be managed by the DRM memory 409 * manager. 410 */ 411 __u64 gtt_start; 412 /** 413 * Ending offset in the GTT to be managed by the DRM memory 414 * manager. 415 */ 416 __u64 gtt_end; 417 }; 418 419 struct drm_i915_gem_create { 420 /** 421 * Requested size for the object. 422 * 423 * The (page-aligned) allocated size for the object will be returned. 424 */ 425 __u64 size; 426 /** 427 * Returned handle for the object. 428 * 429 * Object handles are nonzero. 430 */ 431 __u32 handle; 432 __u32 pad; 433 }; 434 435 struct drm_i915_gem_pread { 436 /** Handle for the object being read. */ 437 __u32 handle; 438 __u32 pad; 439 /** Offset into the object to read from */ 440 __u64 offset; 441 /** Length of data to read */ 442 __u64 size; 443 /** 444 * Pointer to write the data into. 445 * 446 * This is a fixed-size type for 32/64 compatibility. 447 */ 448 __u64 data_ptr; 449 }; 450 451 struct drm_i915_gem_pwrite { 452 /** Handle for the object being written to. */ 453 __u32 handle; 454 __u32 pad; 455 /** Offset into the object to write to */ 456 __u64 offset; 457 /** Length of data to write */ 458 __u64 size; 459 /** 460 * Pointer to read the data from. 461 * 462 * This is a fixed-size type for 32/64 compatibility. 463 */ 464 __u64 data_ptr; 465 }; 466 467 struct drm_i915_gem_mmap { 468 /** Handle for the object being mapped. */ 469 __u32 handle; 470 __u32 pad; 471 /** Offset in the object to map. */ 472 __u64 offset; 473 /** 474 * Length of data to map. 475 * 476 * The value will be page-aligned. 477 */ 478 __u64 size; 479 /** 480 * Returned pointer the data was mapped at. 481 * 482 * This is a fixed-size type for 32/64 compatibility. 483 */ 484 __u64 addr_ptr; 485 }; 486 487 struct drm_i915_gem_mmap_gtt { 488 /** Handle for the object being mapped. */ 489 __u32 handle; 490 __u32 pad; 491 /** 492 * Fake offset to use for subsequent mmap call 493 * 494 * This is a fixed-size type for 32/64 compatibility. 495 */ 496 __u64 offset; 497 }; 498 499 struct drm_i915_gem_set_domain { 500 /** Handle for the object */ 501 __u32 handle; 502 503 /** New read domains */ 504 __u32 read_domains; 505 506 /** New write domain */ 507 __u32 write_domain; 508 }; 509 510 struct drm_i915_gem_sw_finish { 511 /** Handle for the object */ 512 __u32 handle; 513 }; 514 515 struct drm_i915_gem_relocation_entry { 516 /** 517 * Handle of the buffer being pointed to by this relocation entry. 518 * 519 * It's appealing to make this be an index into the mm_validate_entry 520 * list to refer to the buffer, but this allows the driver to create 521 * a relocation list for state buffers and not re-write it per 522 * exec using the buffer. 523 */ 524 __u32 target_handle; 525 526 /** 527 * Value to be added to the offset of the target buffer to make up 528 * the relocation entry. 529 */ 530 __u32 delta; 531 532 /** Offset in the buffer the relocation entry will be written into */ 533 __u64 offset; 534 535 /** 536 * Offset value of the target buffer that the relocation entry was last 537 * written as. 538 * 539 * If the buffer has the same offset as last time, we can skip syncing 540 * and writing the relocation. This value is written back out by 541 * the execbuffer ioctl when the relocation is written. 542 */ 543 __u64 presumed_offset; 544 545 /** 546 * Target memory domains read by this operation. 547 */ 548 __u32 read_domains; 549 550 /** 551 * Target memory domains written by this operation. 552 * 553 * Note that only one domain may be written by the whole 554 * execbuffer operation, so that where there are conflicts, 555 * the application will get -EINVAL back. 556 */ 557 __u32 write_domain; 558 }; 559 560 /** @{ 561 * Intel memory domains 562 * 563 * Most of these just align with the various caches in 564 * the system and are used to flush and invalidate as 565 * objects end up cached in different domains. 566 */ 567 /** CPU cache */ 568 #define I915_GEM_DOMAIN_CPU 0x00000001 569 /** Render cache, used by 2D and 3D drawing */ 570 #define I915_GEM_DOMAIN_RENDER 0x00000002 571 /** Sampler cache, used by texture engine */ 572 #define I915_GEM_DOMAIN_SAMPLER 0x00000004 573 /** Command queue, used to load batch buffers */ 574 #define I915_GEM_DOMAIN_COMMAND 0x00000008 575 /** Instruction cache, used by shader programs */ 576 #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 577 /** Vertex address cache */ 578 #define I915_GEM_DOMAIN_VERTEX 0x00000020 579 /** GTT domain - aperture and scanout */ 580 #define I915_GEM_DOMAIN_GTT 0x00000040 581 /** @} */ 582 583 struct drm_i915_gem_exec_object { 584 /** 585 * User's handle for a buffer to be bound into the GTT for this 586 * operation. 587 */ 588 __u32 handle; 589 590 /** Number of relocations to be performed on this buffer */ 591 __u32 relocation_count; 592 /** 593 * Pointer to array of struct drm_i915_gem_relocation_entry containing 594 * the relocations to be performed in this buffer. 595 */ 596 __u64 relocs_ptr; 597 598 /** Required alignment in graphics aperture */ 599 __u64 alignment; 600 601 /** 602 * Returned value of the updated offset of the object, for future 603 * presumed_offset writes. 604 */ 605 __u64 offset; 606 }; 607 608 struct drm_i915_gem_execbuffer { 609 /** 610 * List of buffers to be validated with their relocations to be 611 * performend on them. 612 * 613 * This is a pointer to an array of struct drm_i915_gem_validate_entry. 614 * 615 * These buffers must be listed in an order such that all relocations 616 * a buffer is performing refer to buffers that have already appeared 617 * in the validate list. 618 */ 619 __u64 buffers_ptr; 620 __u32 buffer_count; 621 622 /** Offset in the batchbuffer to start execution from. */ 623 __u32 batch_start_offset; 624 /** Bytes used in batchbuffer from batch_start_offset */ 625 __u32 batch_len; 626 __u32 DR1; 627 __u32 DR4; 628 __u32 num_cliprects; 629 /** This is a struct drm_clip_rect *cliprects */ 630 __u64 cliprects_ptr; 631 }; 632 633 struct drm_i915_gem_exec_object2 { 634 /** 635 * User's handle for a buffer to be bound into the GTT for this 636 * operation. 637 */ 638 __u32 handle; 639 640 /** Number of relocations to be performed on this buffer */ 641 __u32 relocation_count; 642 /** 643 * Pointer to array of struct drm_i915_gem_relocation_entry containing 644 * the relocations to be performed in this buffer. 645 */ 646 __u64 relocs_ptr; 647 648 /** Required alignment in graphics aperture */ 649 __u64 alignment; 650 651 /** 652 * Returned value of the updated offset of the object, for future 653 * presumed_offset writes. 654 */ 655 __u64 offset; 656 657 #define EXEC_OBJECT_NEEDS_FENCE (1<<0) 658 #define EXEC_OBJECT_NEEDS_GTT (1<<1) 659 #define EXEC_OBJECT_WRITE (1<<2) 660 #define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_WRITE<<1) 661 __u64 flags; 662 663 __u64 rsvd1; 664 __u64 rsvd2; 665 }; 666 667 struct drm_i915_gem_execbuffer2 { 668 /** 669 * List of gem_exec_object2 structs 670 */ 671 __u64 buffers_ptr; 672 __u32 buffer_count; 673 674 /** Offset in the batchbuffer to start execution from. */ 675 __u32 batch_start_offset; 676 /** Bytes used in batchbuffer from batch_start_offset */ 677 __u32 batch_len; 678 __u32 DR1; 679 __u32 DR4; 680 __u32 num_cliprects; 681 /** This is a struct drm_clip_rect *cliprects */ 682 __u64 cliprects_ptr; 683 #define I915_EXEC_RING_MASK (7<<0) 684 #define I915_EXEC_DEFAULT (0<<0) 685 #define I915_EXEC_RENDER (1<<0) 686 #define I915_EXEC_BSD (2<<0) 687 #define I915_EXEC_BLT (3<<0) 688 #define I915_EXEC_VEBOX (4<<0) 689 690 /* Used for switching the constants addressing mode on gen4+ RENDER ring. 691 * Gen6+ only supports relative addressing to dynamic state (default) and 692 * absolute addressing. 693 * 694 * These flags are ignored for the BSD and BLT rings. 695 */ 696 #define I915_EXEC_CONSTANTS_MASK (3<<6) 697 #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ 698 #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) 699 #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ 700 __u64 flags; 701 __u64 rsvd1; /* now used for context info */ 702 __u64 rsvd2; 703 }; 704 705 /** Resets the SO write offset registers for transform feedback on gen7. */ 706 #define I915_EXEC_GEN7_SOL_RESET (1<<8) 707 708 /** Request a privileged ("secure") batch buffer. Note only available for 709 * DRM_ROOT_ONLY | DRM_MASTER processes. 710 */ 711 #define I915_EXEC_SECURE (1<<9) 712 713 /** Inform the kernel that the batch is and will always be pinned. This 714 * negates the requirement for a workaround to be performed to avoid 715 * an incoherent CS (such as can be found on 830/845). If this flag is 716 * not passed, the kernel will endeavour to make sure the batch is 717 * coherent with the CS before execution. If this flag is passed, 718 * userspace assumes the responsibility for ensuring the same. 719 */ 720 #define I915_EXEC_IS_PINNED (1<<10) 721 722 /** Provide a hint to the kernel that the command stream and auxilliary 723 * state buffers already holds the correct presumed addresses and so the 724 * relocation process may be skipped if no buffers need to be moved in 725 * preparation for the execbuffer. 726 */ 727 #define I915_EXEC_NO_RELOC (1<<11) 728 729 /** Use the reloc.handle as an index into the exec object array rather 730 * than as the per-file handle. 731 */ 732 #define I915_EXEC_HANDLE_LUT (1<<12) 733 734 #define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_HANDLE_LUT<<1) 735 736 #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) 737 #define i915_execbuffer2_set_context_id(eb2, context) \ 738 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK 739 #define i915_execbuffer2_get_context_id(eb2) \ 740 ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) 741 742 struct drm_i915_gem_pin { 743 /** Handle of the buffer to be pinned. */ 744 __u32 handle; 745 __u32 pad; 746 747 /** alignment required within the aperture */ 748 __u64 alignment; 749 750 /** Returned GTT offset of the buffer. */ 751 __u64 offset; 752 }; 753 754 struct drm_i915_gem_unpin { 755 /** Handle of the buffer to be unpinned. */ 756 __u32 handle; 757 __u32 pad; 758 }; 759 760 struct drm_i915_gem_busy { 761 /** Handle of the buffer to check for busy */ 762 __u32 handle; 763 764 /** Return busy status (1 if busy, 0 if idle). 765 * The high word is used to indicate on which rings the object 766 * currently resides: 767 * 16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc) 768 */ 769 __u32 busy; 770 }; 771 772 /** 773 * I915_CACHING_NONE 774 * 775 * GPU access is not coherent with cpu caches. Default for machines without an 776 * LLC. 777 */ 778 #define I915_CACHING_NONE 0 779 /** 780 * I915_CACHING_CACHED 781 * 782 * GPU access is coherent with cpu caches and furthermore the data is cached in 783 * last-level caches shared between cpu cores and the gpu GT. Default on 784 * machines with HAS_LLC. 785 */ 786 #define I915_CACHING_CACHED 1 787 /** 788 * I915_CACHING_DISPLAY 789 * 790 * Special GPU caching mode which is coherent with the scanout engines. 791 * Transparently falls back to I915_CACHING_NONE on platforms where no special 792 * cache mode (like write-through or gfdt flushing) is available. The kernel 793 * automatically sets this mode when using a buffer as a scanout target. 794 * Userspace can manually set this mode to avoid a costly stall and clflush in 795 * the hotpath of drawing the first frame. 796 */ 797 #define I915_CACHING_DISPLAY 2 798 799 struct drm_i915_gem_caching { 800 /** 801 * Handle of the buffer to set/get the caching level of. */ 802 __u32 handle; 803 804 /** 805 * Cacheing level to apply or return value 806 * 807 * bits0-15 are for generic caching control (i.e. the above defined 808 * values). bits16-31 are reserved for platform-specific variations 809 * (e.g. l3$ caching on gen7). */ 810 __u32 caching; 811 }; 812 813 #define I915_TILING_NONE 0 814 #define I915_TILING_X 1 815 #define I915_TILING_Y 2 816 817 #define I915_BIT_6_SWIZZLE_NONE 0 818 #define I915_BIT_6_SWIZZLE_9 1 819 #define I915_BIT_6_SWIZZLE_9_10 2 820 #define I915_BIT_6_SWIZZLE_9_11 3 821 #define I915_BIT_6_SWIZZLE_9_10_11 4 822 /* Not seen by userland */ 823 #define I915_BIT_6_SWIZZLE_UNKNOWN 5 824 /* Seen by userland. */ 825 #define I915_BIT_6_SWIZZLE_9_17 6 826 #define I915_BIT_6_SWIZZLE_9_10_17 7 827 828 struct drm_i915_gem_set_tiling { 829 /** Handle of the buffer to have its tiling state updated */ 830 __u32 handle; 831 832 /** 833 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 834 * I915_TILING_Y). 835 * 836 * This value is to be set on request, and will be updated by the 837 * kernel on successful return with the actual chosen tiling layout. 838 * 839 * The tiling mode may be demoted to I915_TILING_NONE when the system 840 * has bit 6 swizzling that can't be managed correctly by GEM. 841 * 842 * Buffer contents become undefined when changing tiling_mode. 843 */ 844 __u32 tiling_mode; 845 846 /** 847 * Stride in bytes for the object when in I915_TILING_X or 848 * I915_TILING_Y. 849 */ 850 __u32 stride; 851 852 /** 853 * Returned address bit 6 swizzling required for CPU access through 854 * mmap mapping. 855 */ 856 __u32 swizzle_mode; 857 }; 858 859 struct drm_i915_gem_get_tiling { 860 /** Handle of the buffer to get tiling state for. */ 861 __u32 handle; 862 863 /** 864 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 865 * I915_TILING_Y). 866 */ 867 __u32 tiling_mode; 868 869 /** 870 * Returned address bit 6 swizzling required for CPU access through 871 * mmap mapping. 872 */ 873 __u32 swizzle_mode; 874 }; 875 876 struct drm_i915_gem_get_aperture { 877 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ 878 __u64 aper_size; 879 880 /** 881 * Available space in the aperture used by i915_gem_execbuffer, in 882 * bytes 883 */ 884 __u64 aper_available_size; 885 }; 886 887 struct drm_i915_get_pipe_from_crtc_id { 888 /** ID of CRTC being requested **/ 889 __u32 crtc_id; 890 891 /** pipe of requested CRTC **/ 892 __u32 pipe; 893 }; 894 895 #define I915_MADV_WILLNEED 0 896 #define I915_MADV_DONTNEED 1 897 #define __I915_MADV_PURGED 2 /* internal state */ 898 899 struct drm_i915_gem_madvise { 900 /** Handle of the buffer to change the backing store advice */ 901 __u32 handle; 902 903 /* Advice: either the buffer will be needed again in the near future, 904 * or wont be and could be discarded under memory pressure. 905 */ 906 __u32 madv; 907 908 /** Whether the backing store still exists. */ 909 __u32 retained; 910 }; 911 912 /* flags */ 913 #define I915_OVERLAY_TYPE_MASK 0xff 914 #define I915_OVERLAY_YUV_PLANAR 0x01 915 #define I915_OVERLAY_YUV_PACKED 0x02 916 #define I915_OVERLAY_RGB 0x03 917 918 #define I915_OVERLAY_DEPTH_MASK 0xff00 919 #define I915_OVERLAY_RGB24 0x1000 920 #define I915_OVERLAY_RGB16 0x2000 921 #define I915_OVERLAY_RGB15 0x3000 922 #define I915_OVERLAY_YUV422 0x0100 923 #define I915_OVERLAY_YUV411 0x0200 924 #define I915_OVERLAY_YUV420 0x0300 925 #define I915_OVERLAY_YUV410 0x0400 926 927 #define I915_OVERLAY_SWAP_MASK 0xff0000 928 #define I915_OVERLAY_NO_SWAP 0x000000 929 #define I915_OVERLAY_UV_SWAP 0x010000 930 #define I915_OVERLAY_Y_SWAP 0x020000 931 #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 932 933 #define I915_OVERLAY_FLAGS_MASK 0xff000000 934 #define I915_OVERLAY_ENABLE 0x01000000 935 936 struct drm_intel_overlay_put_image { 937 /* various flags and src format description */ 938 __u32 flags; 939 /* source picture description */ 940 __u32 bo_handle; 941 /* stride values and offsets are in bytes, buffer relative */ 942 __u16 stride_Y; /* stride for packed formats */ 943 __u16 stride_UV; 944 __u32 offset_Y; /* offset for packet formats */ 945 __u32 offset_U; 946 __u32 offset_V; 947 /* in pixels */ 948 __u16 src_width; 949 __u16 src_height; 950 /* to compensate the scaling factors for partially covered surfaces */ 951 __u16 src_scan_width; 952 __u16 src_scan_height; 953 /* output crtc description */ 954 __u32 crtc_id; 955 __u16 dst_x; 956 __u16 dst_y; 957 __u16 dst_width; 958 __u16 dst_height; 959 }; 960 961 /* flags */ 962 #define I915_OVERLAY_UPDATE_ATTRS (1<<0) 963 #define I915_OVERLAY_UPDATE_GAMMA (1<<1) 964 struct drm_intel_overlay_attrs { 965 __u32 flags; 966 __u32 color_key; 967 __s32 brightness; 968 __u32 contrast; 969 __u32 saturation; 970 __u32 gamma0; 971 __u32 gamma1; 972 __u32 gamma2; 973 __u32 gamma3; 974 __u32 gamma4; 975 __u32 gamma5; 976 }; 977 978 /* 979 * Intel sprite handling 980 * 981 * Color keying works with a min/mask/max tuple. Both source and destination 982 * color keying is allowed. 983 * 984 * Source keying: 985 * Sprite pixels within the min & max values, masked against the color channels 986 * specified in the mask field, will be transparent. All other pixels will 987 * be displayed on top of the primary plane. For RGB surfaces, only the min 988 * and mask fields will be used; ranged compares are not allowed. 989 * 990 * Destination keying: 991 * Primary plane pixels that match the min value, masked against the color 992 * channels specified in the mask field, will be replaced by corresponding 993 * pixels from the sprite plane. 994 * 995 * Note that source & destination keying are exclusive; only one can be 996 * active on a given plane. 997 */ 998 999 #define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */ 1000 #define I915_SET_COLORKEY_DESTINATION (1<<1) 1001 #define I915_SET_COLORKEY_SOURCE (1<<2) 1002 struct drm_intel_sprite_colorkey { 1003 __u32 plane_id; 1004 __u32 min_value; 1005 __u32 channel_mask; 1006 __u32 max_value; 1007 __u32 flags; 1008 }; 1009 1010 struct drm_i915_gem_wait { 1011 /** Handle of BO we shall wait on */ 1012 __u32 bo_handle; 1013 __u32 flags; 1014 /** Number of nanoseconds to wait, Returns time remaining. */ 1015 __s64 timeout_ns; 1016 }; 1017 1018 struct drm_i915_gem_context_create { 1019 /* output: id of new context*/ 1020 __u32 ctx_id; 1021 __u32 pad; 1022 }; 1023 1024 struct drm_i915_gem_context_destroy { 1025 __u32 ctx_id; 1026 __u32 pad; 1027 }; 1028 1029 struct drm_i915_reg_read { 1030 __u64 offset; 1031 __u64 val; /* Return value */ 1032 }; 1033 #endif /* _UAPI_I915_DRM_H_ */ 1034