1 /* 2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 * 25 */ 26 27 #ifndef _UAPI_I915_DRM_H_ 28 #define _UAPI_I915_DRM_H_ 29 30 #include <drm/drm.h> 31 32 /* Please note that modifications to all structs defined here are 33 * subject to backwards-compatibility constraints. 34 */ 35 36 /** 37 * DOC: uevents generated by i915 on it's device node 38 * 39 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch 40 * event from the gpu l3 cache. Additional information supplied is ROW, 41 * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep 42 * track of these events and if a specific cache-line seems to have a 43 * persistent error remap it with the l3 remapping tool supplied in 44 * intel-gpu-tools. The value supplied with the event is always 1. 45 * 46 * I915_ERROR_UEVENT - Generated upon error detection, currently only via 47 * hangcheck. The error detection event is a good indicator of when things 48 * began to go badly. The value supplied with the event is a 1 upon error 49 * detection, and a 0 upon reset completion, signifying no more error 50 * exists. NOTE: Disabling hangcheck or reset via module parameter will 51 * cause the related events to not be seen. 52 * 53 * I915_RESET_UEVENT - Event is generated just before an attempt to reset the 54 * the GPU. The value supplied with the event is always 1. NOTE: Disable 55 * reset via module parameter will cause this event to not be seen. 56 */ 57 #define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR" 58 #define I915_ERROR_UEVENT "ERROR" 59 #define I915_RESET_UEVENT "RESET" 60 61 /* Each region is a minimum of 16k, and there are at most 255 of them. 62 */ 63 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use 64 * of chars for next/prev indices */ 65 #define I915_LOG_MIN_TEX_REGION_SIZE 14 66 67 typedef struct _drm_i915_init { 68 enum { 69 I915_INIT_DMA = 0x01, 70 I915_CLEANUP_DMA = 0x02, 71 I915_RESUME_DMA = 0x03 72 } func; 73 unsigned int mmio_offset; 74 int sarea_priv_offset; 75 unsigned int ring_start; 76 unsigned int ring_end; 77 unsigned int ring_size; 78 unsigned int front_offset; 79 unsigned int back_offset; 80 unsigned int depth_offset; 81 unsigned int w; 82 unsigned int h; 83 unsigned int pitch; 84 unsigned int pitch_bits; 85 unsigned int back_pitch; 86 unsigned int depth_pitch; 87 unsigned int cpp; 88 unsigned int chipset; 89 } drm_i915_init_t; 90 91 typedef struct _drm_i915_sarea { 92 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 93 int last_upload; /* last time texture was uploaded */ 94 int last_enqueue; /* last time a buffer was enqueued */ 95 int last_dispatch; /* age of the most recently dispatched buffer */ 96 int ctxOwner; /* last context to upload state */ 97 int texAge; 98 int pf_enabled; /* is pageflipping allowed? */ 99 int pf_active; 100 int pf_current_page; /* which buffer is being displayed? */ 101 int perf_boxes; /* performance boxes to be displayed */ 102 int width, height; /* screen size in pixels */ 103 104 drm_handle_t front_handle; 105 int front_offset; 106 int front_size; 107 108 drm_handle_t back_handle; 109 int back_offset; 110 int back_size; 111 112 drm_handle_t depth_handle; 113 int depth_offset; 114 int depth_size; 115 116 drm_handle_t tex_handle; 117 int tex_offset; 118 int tex_size; 119 int log_tex_granularity; 120 int pitch; 121 int rotation; /* 0, 90, 180 or 270 */ 122 int rotated_offset; 123 int rotated_size; 124 int rotated_pitch; 125 int virtualX, virtualY; 126 127 unsigned int front_tiled; 128 unsigned int back_tiled; 129 unsigned int depth_tiled; 130 unsigned int rotated_tiled; 131 unsigned int rotated2_tiled; 132 133 int pipeA_x; 134 int pipeA_y; 135 int pipeA_w; 136 int pipeA_h; 137 int pipeB_x; 138 int pipeB_y; 139 int pipeB_w; 140 int pipeB_h; 141 142 /* fill out some space for old userspace triple buffer */ 143 drm_handle_t unused_handle; 144 __u32 unused1, unused2, unused3; 145 146 /* buffer object handles for static buffers. May change 147 * over the lifetime of the client. 148 */ 149 __u32 front_bo_handle; 150 __u32 back_bo_handle; 151 __u32 unused_bo_handle; 152 __u32 depth_bo_handle; 153 154 } drm_i915_sarea_t; 155 156 /* due to userspace building against these headers we need some compat here */ 157 #define planeA_x pipeA_x 158 #define planeA_y pipeA_y 159 #define planeA_w pipeA_w 160 #define planeA_h pipeA_h 161 #define planeB_x pipeB_x 162 #define planeB_y pipeB_y 163 #define planeB_w pipeB_w 164 #define planeB_h pipeB_h 165 166 /* Flags for perf_boxes 167 */ 168 #define I915_BOX_RING_EMPTY 0x1 169 #define I915_BOX_FLIP 0x2 170 #define I915_BOX_WAIT 0x4 171 #define I915_BOX_TEXTURE_LOAD 0x8 172 #define I915_BOX_LOST_CONTEXT 0x10 173 174 /* I915 specific ioctls 175 * The device specific ioctl range is 0x40 to 0x79. 176 */ 177 #define DRM_I915_INIT 0x00 178 #define DRM_I915_FLUSH 0x01 179 #define DRM_I915_FLIP 0x02 180 #define DRM_I915_BATCHBUFFER 0x03 181 #define DRM_I915_IRQ_EMIT 0x04 182 #define DRM_I915_IRQ_WAIT 0x05 183 #define DRM_I915_GETPARAM 0x06 184 #define DRM_I915_SETPARAM 0x07 185 #define DRM_I915_ALLOC 0x08 186 #define DRM_I915_FREE 0x09 187 #define DRM_I915_INIT_HEAP 0x0a 188 #define DRM_I915_CMDBUFFER 0x0b 189 #define DRM_I915_DESTROY_HEAP 0x0c 190 #define DRM_I915_SET_VBLANK_PIPE 0x0d 191 #define DRM_I915_GET_VBLANK_PIPE 0x0e 192 #define DRM_I915_VBLANK_SWAP 0x0f 193 #define DRM_I915_HWS_ADDR 0x11 194 #define DRM_I915_GEM_INIT 0x13 195 #define DRM_I915_GEM_EXECBUFFER 0x14 196 #define DRM_I915_GEM_PIN 0x15 197 #define DRM_I915_GEM_UNPIN 0x16 198 #define DRM_I915_GEM_BUSY 0x17 199 #define DRM_I915_GEM_THROTTLE 0x18 200 #define DRM_I915_GEM_ENTERVT 0x19 201 #define DRM_I915_GEM_LEAVEVT 0x1a 202 #define DRM_I915_GEM_CREATE 0x1b 203 #define DRM_I915_GEM_PREAD 0x1c 204 #define DRM_I915_GEM_PWRITE 0x1d 205 #define DRM_I915_GEM_MMAP 0x1e 206 #define DRM_I915_GEM_SET_DOMAIN 0x1f 207 #define DRM_I915_GEM_SW_FINISH 0x20 208 #define DRM_I915_GEM_SET_TILING 0x21 209 #define DRM_I915_GEM_GET_TILING 0x22 210 #define DRM_I915_GEM_GET_APERTURE 0x23 211 #define DRM_I915_GEM_MMAP_GTT 0x24 212 #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 213 #define DRM_I915_GEM_MADVISE 0x26 214 #define DRM_I915_OVERLAY_PUT_IMAGE 0x27 215 #define DRM_I915_OVERLAY_ATTRS 0x28 216 #define DRM_I915_GEM_EXECBUFFER2 0x29 217 #define DRM_I915_GET_SPRITE_COLORKEY 0x2a 218 #define DRM_I915_SET_SPRITE_COLORKEY 0x2b 219 #define DRM_I915_GEM_WAIT 0x2c 220 #define DRM_I915_GEM_CONTEXT_CREATE 0x2d 221 #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e 222 #define DRM_I915_GEM_SET_CACHING 0x2f 223 #define DRM_I915_GEM_GET_CACHING 0x30 224 #define DRM_I915_REG_READ 0x31 225 #define DRM_I915_GET_RESET_STATS 0x32 226 #define DRM_I915_GEM_USERPTR 0x33 227 228 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 229 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 230 #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) 231 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 232 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 233 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 234 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 235 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 236 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 237 #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 238 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 239 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 240 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 241 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 242 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 243 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 244 #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) 245 #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 246 #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 247 #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 248 #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 249 #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 250 #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 251 #define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) 252 #define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) 253 #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 254 #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 255 #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 256 #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 257 #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 258 #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 259 #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 260 #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 261 #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 262 #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 263 #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 264 #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 265 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 266 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 267 #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 268 #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) 269 #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 270 #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 271 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 272 #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) 273 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) 274 #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) 275 #define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) 276 #define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats) 277 #define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr) 278 279 /* Allow drivers to submit batchbuffers directly to hardware, relying 280 * on the security mechanisms provided by hardware. 281 */ 282 typedef struct drm_i915_batchbuffer { 283 int start; /* agp offset */ 284 int used; /* nr bytes in use */ 285 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 286 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 287 int num_cliprects; /* mulitpass with multiple cliprects? */ 288 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 289 } drm_i915_batchbuffer_t; 290 291 /* As above, but pass a pointer to userspace buffer which can be 292 * validated by the kernel prior to sending to hardware. 293 */ 294 typedef struct _drm_i915_cmdbuffer { 295 char __user *buf; /* pointer to userspace command buffer */ 296 int sz; /* nr bytes in buf */ 297 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 298 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 299 int num_cliprects; /* mulitpass with multiple cliprects? */ 300 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 301 } drm_i915_cmdbuffer_t; 302 303 /* Userspace can request & wait on irq's: 304 */ 305 typedef struct drm_i915_irq_emit { 306 int __user *irq_seq; 307 } drm_i915_irq_emit_t; 308 309 typedef struct drm_i915_irq_wait { 310 int irq_seq; 311 } drm_i915_irq_wait_t; 312 313 /* Ioctl to query kernel params: 314 */ 315 #define I915_PARAM_IRQ_ACTIVE 1 316 #define I915_PARAM_ALLOW_BATCHBUFFER 2 317 #define I915_PARAM_LAST_DISPATCH 3 318 #define I915_PARAM_CHIPSET_ID 4 319 #define I915_PARAM_HAS_GEM 5 320 #define I915_PARAM_NUM_FENCES_AVAIL 6 321 #define I915_PARAM_HAS_OVERLAY 7 322 #define I915_PARAM_HAS_PAGEFLIPPING 8 323 #define I915_PARAM_HAS_EXECBUF2 9 324 #define I915_PARAM_HAS_BSD 10 325 #define I915_PARAM_HAS_BLT 11 326 #define I915_PARAM_HAS_RELAXED_FENCING 12 327 #define I915_PARAM_HAS_COHERENT_RINGS 13 328 #define I915_PARAM_HAS_EXEC_CONSTANTS 14 329 #define I915_PARAM_HAS_RELAXED_DELTA 15 330 #define I915_PARAM_HAS_GEN7_SOL_RESET 16 331 #define I915_PARAM_HAS_LLC 17 332 #define I915_PARAM_HAS_ALIASING_PPGTT 18 333 #define I915_PARAM_HAS_WAIT_TIMEOUT 19 334 #define I915_PARAM_HAS_SEMAPHORES 20 335 #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 336 #define I915_PARAM_HAS_VEBOX 22 337 #define I915_PARAM_HAS_SECURE_BATCHES 23 338 #define I915_PARAM_HAS_PINNED_BATCHES 24 339 #define I915_PARAM_HAS_EXEC_NO_RELOC 25 340 #define I915_PARAM_HAS_EXEC_HANDLE_LUT 26 341 #define I915_PARAM_HAS_WT 27 342 #define I915_PARAM_CMD_PARSER_VERSION 28 343 344 typedef struct drm_i915_getparam { 345 int param; 346 int __user *value; 347 } drm_i915_getparam_t; 348 349 /* Ioctl to set kernel params: 350 */ 351 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 352 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 353 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 354 #define I915_SETPARAM_NUM_USED_FENCES 4 355 356 typedef struct drm_i915_setparam { 357 int param; 358 int value; 359 } drm_i915_setparam_t; 360 361 /* A memory manager for regions of shared memory: 362 */ 363 #define I915_MEM_REGION_AGP 1 364 365 typedef struct drm_i915_mem_alloc { 366 int region; 367 int alignment; 368 int size; 369 int __user *region_offset; /* offset from start of fb or agp */ 370 } drm_i915_mem_alloc_t; 371 372 typedef struct drm_i915_mem_free { 373 int region; 374 int region_offset; 375 } drm_i915_mem_free_t; 376 377 typedef struct drm_i915_mem_init_heap { 378 int region; 379 int size; 380 int start; 381 } drm_i915_mem_init_heap_t; 382 383 /* Allow memory manager to be torn down and re-initialized (eg on 384 * rotate): 385 */ 386 typedef struct drm_i915_mem_destroy_heap { 387 int region; 388 } drm_i915_mem_destroy_heap_t; 389 390 /* Allow X server to configure which pipes to monitor for vblank signals 391 */ 392 #define DRM_I915_VBLANK_PIPE_A 1 393 #define DRM_I915_VBLANK_PIPE_B 2 394 395 typedef struct drm_i915_vblank_pipe { 396 int pipe; 397 } drm_i915_vblank_pipe_t; 398 399 /* Schedule buffer swap at given vertical blank: 400 */ 401 typedef struct drm_i915_vblank_swap { 402 drm_drawable_t drawable; 403 enum drm_vblank_seq_type seqtype; 404 unsigned int sequence; 405 } drm_i915_vblank_swap_t; 406 407 typedef struct drm_i915_hws_addr { 408 __u64 addr; 409 } drm_i915_hws_addr_t; 410 411 struct drm_i915_gem_init { 412 /** 413 * Beginning offset in the GTT to be managed by the DRM memory 414 * manager. 415 */ 416 __u64 gtt_start; 417 /** 418 * Ending offset in the GTT to be managed by the DRM memory 419 * manager. 420 */ 421 __u64 gtt_end; 422 }; 423 424 struct drm_i915_gem_create { 425 /** 426 * Requested size for the object. 427 * 428 * The (page-aligned) allocated size for the object will be returned. 429 */ 430 __u64 size; 431 /** 432 * Returned handle for the object. 433 * 434 * Object handles are nonzero. 435 */ 436 __u32 handle; 437 __u32 pad; 438 }; 439 440 struct drm_i915_gem_pread { 441 /** Handle for the object being read. */ 442 __u32 handle; 443 __u32 pad; 444 /** Offset into the object to read from */ 445 __u64 offset; 446 /** Length of data to read */ 447 __u64 size; 448 /** 449 * Pointer to write the data into. 450 * 451 * This is a fixed-size type for 32/64 compatibility. 452 */ 453 __u64 data_ptr; 454 }; 455 456 struct drm_i915_gem_pwrite { 457 /** Handle for the object being written to. */ 458 __u32 handle; 459 __u32 pad; 460 /** Offset into the object to write to */ 461 __u64 offset; 462 /** Length of data to write */ 463 __u64 size; 464 /** 465 * Pointer to read the data from. 466 * 467 * This is a fixed-size type for 32/64 compatibility. 468 */ 469 __u64 data_ptr; 470 }; 471 472 struct drm_i915_gem_mmap { 473 /** Handle for the object being mapped. */ 474 __u32 handle; 475 __u32 pad; 476 /** Offset in the object to map. */ 477 __u64 offset; 478 /** 479 * Length of data to map. 480 * 481 * The value will be page-aligned. 482 */ 483 __u64 size; 484 /** 485 * Returned pointer the data was mapped at. 486 * 487 * This is a fixed-size type for 32/64 compatibility. 488 */ 489 __u64 addr_ptr; 490 }; 491 492 struct drm_i915_gem_mmap_gtt { 493 /** Handle for the object being mapped. */ 494 __u32 handle; 495 __u32 pad; 496 /** 497 * Fake offset to use for subsequent mmap call 498 * 499 * This is a fixed-size type for 32/64 compatibility. 500 */ 501 __u64 offset; 502 }; 503 504 struct drm_i915_gem_set_domain { 505 /** Handle for the object */ 506 __u32 handle; 507 508 /** New read domains */ 509 __u32 read_domains; 510 511 /** New write domain */ 512 __u32 write_domain; 513 }; 514 515 struct drm_i915_gem_sw_finish { 516 /** Handle for the object */ 517 __u32 handle; 518 }; 519 520 struct drm_i915_gem_relocation_entry { 521 /** 522 * Handle of the buffer being pointed to by this relocation entry. 523 * 524 * It's appealing to make this be an index into the mm_validate_entry 525 * list to refer to the buffer, but this allows the driver to create 526 * a relocation list for state buffers and not re-write it per 527 * exec using the buffer. 528 */ 529 __u32 target_handle; 530 531 /** 532 * Value to be added to the offset of the target buffer to make up 533 * the relocation entry. 534 */ 535 __u32 delta; 536 537 /** Offset in the buffer the relocation entry will be written into */ 538 __u64 offset; 539 540 /** 541 * Offset value of the target buffer that the relocation entry was last 542 * written as. 543 * 544 * If the buffer has the same offset as last time, we can skip syncing 545 * and writing the relocation. This value is written back out by 546 * the execbuffer ioctl when the relocation is written. 547 */ 548 __u64 presumed_offset; 549 550 /** 551 * Target memory domains read by this operation. 552 */ 553 __u32 read_domains; 554 555 /** 556 * Target memory domains written by this operation. 557 * 558 * Note that only one domain may be written by the whole 559 * execbuffer operation, so that where there are conflicts, 560 * the application will get -EINVAL back. 561 */ 562 __u32 write_domain; 563 }; 564 565 /** @{ 566 * Intel memory domains 567 * 568 * Most of these just align with the various caches in 569 * the system and are used to flush and invalidate as 570 * objects end up cached in different domains. 571 */ 572 /** CPU cache */ 573 #define I915_GEM_DOMAIN_CPU 0x00000001 574 /** Render cache, used by 2D and 3D drawing */ 575 #define I915_GEM_DOMAIN_RENDER 0x00000002 576 /** Sampler cache, used by texture engine */ 577 #define I915_GEM_DOMAIN_SAMPLER 0x00000004 578 /** Command queue, used to load batch buffers */ 579 #define I915_GEM_DOMAIN_COMMAND 0x00000008 580 /** Instruction cache, used by shader programs */ 581 #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 582 /** Vertex address cache */ 583 #define I915_GEM_DOMAIN_VERTEX 0x00000020 584 /** GTT domain - aperture and scanout */ 585 #define I915_GEM_DOMAIN_GTT 0x00000040 586 /** @} */ 587 588 struct drm_i915_gem_exec_object { 589 /** 590 * User's handle for a buffer to be bound into the GTT for this 591 * operation. 592 */ 593 __u32 handle; 594 595 /** Number of relocations to be performed on this buffer */ 596 __u32 relocation_count; 597 /** 598 * Pointer to array of struct drm_i915_gem_relocation_entry containing 599 * the relocations to be performed in this buffer. 600 */ 601 __u64 relocs_ptr; 602 603 /** Required alignment in graphics aperture */ 604 __u64 alignment; 605 606 /** 607 * Returned value of the updated offset of the object, for future 608 * presumed_offset writes. 609 */ 610 __u64 offset; 611 }; 612 613 struct drm_i915_gem_execbuffer { 614 /** 615 * List of buffers to be validated with their relocations to be 616 * performend on them. 617 * 618 * This is a pointer to an array of struct drm_i915_gem_validate_entry. 619 * 620 * These buffers must be listed in an order such that all relocations 621 * a buffer is performing refer to buffers that have already appeared 622 * in the validate list. 623 */ 624 __u64 buffers_ptr; 625 __u32 buffer_count; 626 627 /** Offset in the batchbuffer to start execution from. */ 628 __u32 batch_start_offset; 629 /** Bytes used in batchbuffer from batch_start_offset */ 630 __u32 batch_len; 631 __u32 DR1; 632 __u32 DR4; 633 __u32 num_cliprects; 634 /** This is a struct drm_clip_rect *cliprects */ 635 __u64 cliprects_ptr; 636 }; 637 638 struct drm_i915_gem_exec_object2 { 639 /** 640 * User's handle for a buffer to be bound into the GTT for this 641 * operation. 642 */ 643 __u32 handle; 644 645 /** Number of relocations to be performed on this buffer */ 646 __u32 relocation_count; 647 /** 648 * Pointer to array of struct drm_i915_gem_relocation_entry containing 649 * the relocations to be performed in this buffer. 650 */ 651 __u64 relocs_ptr; 652 653 /** Required alignment in graphics aperture */ 654 __u64 alignment; 655 656 /** 657 * Returned value of the updated offset of the object, for future 658 * presumed_offset writes. 659 */ 660 __u64 offset; 661 662 #define EXEC_OBJECT_NEEDS_FENCE (1<<0) 663 #define EXEC_OBJECT_NEEDS_GTT (1<<1) 664 #define EXEC_OBJECT_WRITE (1<<2) 665 #define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_WRITE<<1) 666 __u64 flags; 667 668 __u64 rsvd1; 669 __u64 rsvd2; 670 }; 671 672 struct drm_i915_gem_execbuffer2 { 673 /** 674 * List of gem_exec_object2 structs 675 */ 676 __u64 buffers_ptr; 677 __u32 buffer_count; 678 679 /** Offset in the batchbuffer to start execution from. */ 680 __u32 batch_start_offset; 681 /** Bytes used in batchbuffer from batch_start_offset */ 682 __u32 batch_len; 683 __u32 DR1; 684 __u32 DR4; 685 __u32 num_cliprects; 686 /** This is a struct drm_clip_rect *cliprects */ 687 __u64 cliprects_ptr; 688 #define I915_EXEC_RING_MASK (7<<0) 689 #define I915_EXEC_DEFAULT (0<<0) 690 #define I915_EXEC_RENDER (1<<0) 691 #define I915_EXEC_BSD (2<<0) 692 #define I915_EXEC_BLT (3<<0) 693 #define I915_EXEC_VEBOX (4<<0) 694 695 /* Used for switching the constants addressing mode on gen4+ RENDER ring. 696 * Gen6+ only supports relative addressing to dynamic state (default) and 697 * absolute addressing. 698 * 699 * These flags are ignored for the BSD and BLT rings. 700 */ 701 #define I915_EXEC_CONSTANTS_MASK (3<<6) 702 #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ 703 #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) 704 #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ 705 __u64 flags; 706 __u64 rsvd1; /* now used for context info */ 707 __u64 rsvd2; 708 }; 709 710 /** Resets the SO write offset registers for transform feedback on gen7. */ 711 #define I915_EXEC_GEN7_SOL_RESET (1<<8) 712 713 /** Request a privileged ("secure") batch buffer. Note only available for 714 * DRM_ROOT_ONLY | DRM_MASTER processes. 715 */ 716 #define I915_EXEC_SECURE (1<<9) 717 718 /** Inform the kernel that the batch is and will always be pinned. This 719 * negates the requirement for a workaround to be performed to avoid 720 * an incoherent CS (such as can be found on 830/845). If this flag is 721 * not passed, the kernel will endeavour to make sure the batch is 722 * coherent with the CS before execution. If this flag is passed, 723 * userspace assumes the responsibility for ensuring the same. 724 */ 725 #define I915_EXEC_IS_PINNED (1<<10) 726 727 /** Provide a hint to the kernel that the command stream and auxiliary 728 * state buffers already holds the correct presumed addresses and so the 729 * relocation process may be skipped if no buffers need to be moved in 730 * preparation for the execbuffer. 731 */ 732 #define I915_EXEC_NO_RELOC (1<<11) 733 734 /** Use the reloc.handle as an index into the exec object array rather 735 * than as the per-file handle. 736 */ 737 #define I915_EXEC_HANDLE_LUT (1<<12) 738 739 #define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_HANDLE_LUT<<1) 740 741 #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) 742 #define i915_execbuffer2_set_context_id(eb2, context) \ 743 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK 744 #define i915_execbuffer2_get_context_id(eb2) \ 745 ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) 746 747 struct drm_i915_gem_pin { 748 /** Handle of the buffer to be pinned. */ 749 __u32 handle; 750 __u32 pad; 751 752 /** alignment required within the aperture */ 753 __u64 alignment; 754 755 /** Returned GTT offset of the buffer. */ 756 __u64 offset; 757 }; 758 759 struct drm_i915_gem_unpin { 760 /** Handle of the buffer to be unpinned. */ 761 __u32 handle; 762 __u32 pad; 763 }; 764 765 struct drm_i915_gem_busy { 766 /** Handle of the buffer to check for busy */ 767 __u32 handle; 768 769 /** Return busy status (1 if busy, 0 if idle). 770 * The high word is used to indicate on which rings the object 771 * currently resides: 772 * 16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc) 773 */ 774 __u32 busy; 775 }; 776 777 /** 778 * I915_CACHING_NONE 779 * 780 * GPU access is not coherent with cpu caches. Default for machines without an 781 * LLC. 782 */ 783 #define I915_CACHING_NONE 0 784 /** 785 * I915_CACHING_CACHED 786 * 787 * GPU access is coherent with cpu caches and furthermore the data is cached in 788 * last-level caches shared between cpu cores and the gpu GT. Default on 789 * machines with HAS_LLC. 790 */ 791 #define I915_CACHING_CACHED 1 792 /** 793 * I915_CACHING_DISPLAY 794 * 795 * Special GPU caching mode which is coherent with the scanout engines. 796 * Transparently falls back to I915_CACHING_NONE on platforms where no special 797 * cache mode (like write-through or gfdt flushing) is available. The kernel 798 * automatically sets this mode when using a buffer as a scanout target. 799 * Userspace can manually set this mode to avoid a costly stall and clflush in 800 * the hotpath of drawing the first frame. 801 */ 802 #define I915_CACHING_DISPLAY 2 803 804 struct drm_i915_gem_caching { 805 /** 806 * Handle of the buffer to set/get the caching level of. */ 807 __u32 handle; 808 809 /** 810 * Cacheing level to apply or return value 811 * 812 * bits0-15 are for generic caching control (i.e. the above defined 813 * values). bits16-31 are reserved for platform-specific variations 814 * (e.g. l3$ caching on gen7). */ 815 __u32 caching; 816 }; 817 818 #define I915_TILING_NONE 0 819 #define I915_TILING_X 1 820 #define I915_TILING_Y 2 821 822 #define I915_BIT_6_SWIZZLE_NONE 0 823 #define I915_BIT_6_SWIZZLE_9 1 824 #define I915_BIT_6_SWIZZLE_9_10 2 825 #define I915_BIT_6_SWIZZLE_9_11 3 826 #define I915_BIT_6_SWIZZLE_9_10_11 4 827 /* Not seen by userland */ 828 #define I915_BIT_6_SWIZZLE_UNKNOWN 5 829 /* Seen by userland. */ 830 #define I915_BIT_6_SWIZZLE_9_17 6 831 #define I915_BIT_6_SWIZZLE_9_10_17 7 832 833 struct drm_i915_gem_set_tiling { 834 /** Handle of the buffer to have its tiling state updated */ 835 __u32 handle; 836 837 /** 838 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 839 * I915_TILING_Y). 840 * 841 * This value is to be set on request, and will be updated by the 842 * kernel on successful return with the actual chosen tiling layout. 843 * 844 * The tiling mode may be demoted to I915_TILING_NONE when the system 845 * has bit 6 swizzling that can't be managed correctly by GEM. 846 * 847 * Buffer contents become undefined when changing tiling_mode. 848 */ 849 __u32 tiling_mode; 850 851 /** 852 * Stride in bytes for the object when in I915_TILING_X or 853 * I915_TILING_Y. 854 */ 855 __u32 stride; 856 857 /** 858 * Returned address bit 6 swizzling required for CPU access through 859 * mmap mapping. 860 */ 861 __u32 swizzle_mode; 862 }; 863 864 struct drm_i915_gem_get_tiling { 865 /** Handle of the buffer to get tiling state for. */ 866 __u32 handle; 867 868 /** 869 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 870 * I915_TILING_Y). 871 */ 872 __u32 tiling_mode; 873 874 /** 875 * Returned address bit 6 swizzling required for CPU access through 876 * mmap mapping. 877 */ 878 __u32 swizzle_mode; 879 }; 880 881 struct drm_i915_gem_get_aperture { 882 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ 883 __u64 aper_size; 884 885 /** 886 * Available space in the aperture used by i915_gem_execbuffer, in 887 * bytes 888 */ 889 __u64 aper_available_size; 890 }; 891 892 struct drm_i915_get_pipe_from_crtc_id { 893 /** ID of CRTC being requested **/ 894 __u32 crtc_id; 895 896 /** pipe of requested CRTC **/ 897 __u32 pipe; 898 }; 899 900 #define I915_MADV_WILLNEED 0 901 #define I915_MADV_DONTNEED 1 902 #define __I915_MADV_PURGED 2 /* internal state */ 903 904 struct drm_i915_gem_madvise { 905 /** Handle of the buffer to change the backing store advice */ 906 __u32 handle; 907 908 /* Advice: either the buffer will be needed again in the near future, 909 * or wont be and could be discarded under memory pressure. 910 */ 911 __u32 madv; 912 913 /** Whether the backing store still exists. */ 914 __u32 retained; 915 }; 916 917 /* flags */ 918 #define I915_OVERLAY_TYPE_MASK 0xff 919 #define I915_OVERLAY_YUV_PLANAR 0x01 920 #define I915_OVERLAY_YUV_PACKED 0x02 921 #define I915_OVERLAY_RGB 0x03 922 923 #define I915_OVERLAY_DEPTH_MASK 0xff00 924 #define I915_OVERLAY_RGB24 0x1000 925 #define I915_OVERLAY_RGB16 0x2000 926 #define I915_OVERLAY_RGB15 0x3000 927 #define I915_OVERLAY_YUV422 0x0100 928 #define I915_OVERLAY_YUV411 0x0200 929 #define I915_OVERLAY_YUV420 0x0300 930 #define I915_OVERLAY_YUV410 0x0400 931 932 #define I915_OVERLAY_SWAP_MASK 0xff0000 933 #define I915_OVERLAY_NO_SWAP 0x000000 934 #define I915_OVERLAY_UV_SWAP 0x010000 935 #define I915_OVERLAY_Y_SWAP 0x020000 936 #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 937 938 #define I915_OVERLAY_FLAGS_MASK 0xff000000 939 #define I915_OVERLAY_ENABLE 0x01000000 940 941 struct drm_intel_overlay_put_image { 942 /* various flags and src format description */ 943 __u32 flags; 944 /* source picture description */ 945 __u32 bo_handle; 946 /* stride values and offsets are in bytes, buffer relative */ 947 __u16 stride_Y; /* stride for packed formats */ 948 __u16 stride_UV; 949 __u32 offset_Y; /* offset for packet formats */ 950 __u32 offset_U; 951 __u32 offset_V; 952 /* in pixels */ 953 __u16 src_width; 954 __u16 src_height; 955 /* to compensate the scaling factors for partially covered surfaces */ 956 __u16 src_scan_width; 957 __u16 src_scan_height; 958 /* output crtc description */ 959 __u32 crtc_id; 960 __u16 dst_x; 961 __u16 dst_y; 962 __u16 dst_width; 963 __u16 dst_height; 964 }; 965 966 /* flags */ 967 #define I915_OVERLAY_UPDATE_ATTRS (1<<0) 968 #define I915_OVERLAY_UPDATE_GAMMA (1<<1) 969 struct drm_intel_overlay_attrs { 970 __u32 flags; 971 __u32 color_key; 972 __s32 brightness; 973 __u32 contrast; 974 __u32 saturation; 975 __u32 gamma0; 976 __u32 gamma1; 977 __u32 gamma2; 978 __u32 gamma3; 979 __u32 gamma4; 980 __u32 gamma5; 981 }; 982 983 /* 984 * Intel sprite handling 985 * 986 * Color keying works with a min/mask/max tuple. Both source and destination 987 * color keying is allowed. 988 * 989 * Source keying: 990 * Sprite pixels within the min & max values, masked against the color channels 991 * specified in the mask field, will be transparent. All other pixels will 992 * be displayed on top of the primary plane. For RGB surfaces, only the min 993 * and mask fields will be used; ranged compares are not allowed. 994 * 995 * Destination keying: 996 * Primary plane pixels that match the min value, masked against the color 997 * channels specified in the mask field, will be replaced by corresponding 998 * pixels from the sprite plane. 999 * 1000 * Note that source & destination keying are exclusive; only one can be 1001 * active on a given plane. 1002 */ 1003 1004 #define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */ 1005 #define I915_SET_COLORKEY_DESTINATION (1<<1) 1006 #define I915_SET_COLORKEY_SOURCE (1<<2) 1007 struct drm_intel_sprite_colorkey { 1008 __u32 plane_id; 1009 __u32 min_value; 1010 __u32 channel_mask; 1011 __u32 max_value; 1012 __u32 flags; 1013 }; 1014 1015 struct drm_i915_gem_wait { 1016 /** Handle of BO we shall wait on */ 1017 __u32 bo_handle; 1018 __u32 flags; 1019 /** Number of nanoseconds to wait, Returns time remaining. */ 1020 __s64 timeout_ns; 1021 }; 1022 1023 struct drm_i915_gem_context_create { 1024 /* output: id of new context*/ 1025 __u32 ctx_id; 1026 __u32 pad; 1027 }; 1028 1029 struct drm_i915_gem_context_destroy { 1030 __u32 ctx_id; 1031 __u32 pad; 1032 }; 1033 1034 struct drm_i915_reg_read { 1035 __u64 offset; 1036 __u64 val; /* Return value */ 1037 }; 1038 1039 struct drm_i915_reset_stats { 1040 __u32 ctx_id; 1041 __u32 flags; 1042 1043 /* All resets since boot/module reload, for all contexts */ 1044 __u32 reset_count; 1045 1046 /* Number of batches lost when active in GPU, for this context */ 1047 __u32 batch_active; 1048 1049 /* Number of batches lost pending for execution, for this context */ 1050 __u32 batch_pending; 1051 1052 __u32 pad; 1053 }; 1054 1055 struct drm_i915_gem_userptr { 1056 __u64 user_ptr; 1057 __u64 user_size; 1058 __u32 flags; 1059 #define I915_USERPTR_READ_ONLY 0x1 1060 #define I915_USERPTR_UNSYNCHRONIZED 0x80000000 1061 /** 1062 * Returned handle for the object. 1063 * 1064 * Object handles are nonzero. 1065 */ 1066 __u32 handle; 1067 }; 1068 1069 #endif /* _UAPI_I915_DRM_H_ */ 1070