1 /* 2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 * 25 */ 26 27 #ifndef _UAPI_I915_DRM_H_ 28 #define _UAPI_I915_DRM_H_ 29 30 #include "drm.h" 31 32 #if defined(__cplusplus) 33 extern "C" { 34 #endif 35 36 /* Please note that modifications to all structs defined here are 37 * subject to backwards-compatibility constraints. 38 */ 39 40 /** 41 * DOC: uevents generated by i915 on it's device node 42 * 43 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch 44 * event from the gpu l3 cache. Additional information supplied is ROW, 45 * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep 46 * track of these events and if a specific cache-line seems to have a 47 * persistent error remap it with the l3 remapping tool supplied in 48 * intel-gpu-tools. The value supplied with the event is always 1. 49 * 50 * I915_ERROR_UEVENT - Generated upon error detection, currently only via 51 * hangcheck. The error detection event is a good indicator of when things 52 * began to go badly. The value supplied with the event is a 1 upon error 53 * detection, and a 0 upon reset completion, signifying no more error 54 * exists. NOTE: Disabling hangcheck or reset via module parameter will 55 * cause the related events to not be seen. 56 * 57 * I915_RESET_UEVENT - Event is generated just before an attempt to reset the 58 * the GPU. The value supplied with the event is always 1. NOTE: Disable 59 * reset via module parameter will cause this event to not be seen. 60 */ 61 #define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR" 62 #define I915_ERROR_UEVENT "ERROR" 63 #define I915_RESET_UEVENT "RESET" 64 65 /* Each region is a minimum of 16k, and there are at most 255 of them. 66 */ 67 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use 68 * of chars for next/prev indices */ 69 #define I915_LOG_MIN_TEX_REGION_SIZE 14 70 71 typedef struct _drm_i915_init { 72 enum { 73 I915_INIT_DMA = 0x01, 74 I915_CLEANUP_DMA = 0x02, 75 I915_RESUME_DMA = 0x03 76 } func; 77 unsigned int mmio_offset; 78 int sarea_priv_offset; 79 unsigned int ring_start; 80 unsigned int ring_end; 81 unsigned int ring_size; 82 unsigned int front_offset; 83 unsigned int back_offset; 84 unsigned int depth_offset; 85 unsigned int w; 86 unsigned int h; 87 unsigned int pitch; 88 unsigned int pitch_bits; 89 unsigned int back_pitch; 90 unsigned int depth_pitch; 91 unsigned int cpp; 92 unsigned int chipset; 93 } drm_i915_init_t; 94 95 typedef struct _drm_i915_sarea { 96 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 97 int last_upload; /* last time texture was uploaded */ 98 int last_enqueue; /* last time a buffer was enqueued */ 99 int last_dispatch; /* age of the most recently dispatched buffer */ 100 int ctxOwner; /* last context to upload state */ 101 int texAge; 102 int pf_enabled; /* is pageflipping allowed? */ 103 int pf_active; 104 int pf_current_page; /* which buffer is being displayed? */ 105 int perf_boxes; /* performance boxes to be displayed */ 106 int width, height; /* screen size in pixels */ 107 108 drm_handle_t front_handle; 109 int front_offset; 110 int front_size; 111 112 drm_handle_t back_handle; 113 int back_offset; 114 int back_size; 115 116 drm_handle_t depth_handle; 117 int depth_offset; 118 int depth_size; 119 120 drm_handle_t tex_handle; 121 int tex_offset; 122 int tex_size; 123 int log_tex_granularity; 124 int pitch; 125 int rotation; /* 0, 90, 180 or 270 */ 126 int rotated_offset; 127 int rotated_size; 128 int rotated_pitch; 129 int virtualX, virtualY; 130 131 unsigned int front_tiled; 132 unsigned int back_tiled; 133 unsigned int depth_tiled; 134 unsigned int rotated_tiled; 135 unsigned int rotated2_tiled; 136 137 int pipeA_x; 138 int pipeA_y; 139 int pipeA_w; 140 int pipeA_h; 141 int pipeB_x; 142 int pipeB_y; 143 int pipeB_w; 144 int pipeB_h; 145 146 /* fill out some space for old userspace triple buffer */ 147 drm_handle_t unused_handle; 148 __u32 unused1, unused2, unused3; 149 150 /* buffer object handles for static buffers. May change 151 * over the lifetime of the client. 152 */ 153 __u32 front_bo_handle; 154 __u32 back_bo_handle; 155 __u32 unused_bo_handle; 156 __u32 depth_bo_handle; 157 158 } drm_i915_sarea_t; 159 160 /* due to userspace building against these headers we need some compat here */ 161 #define planeA_x pipeA_x 162 #define planeA_y pipeA_y 163 #define planeA_w pipeA_w 164 #define planeA_h pipeA_h 165 #define planeB_x pipeB_x 166 #define planeB_y pipeB_y 167 #define planeB_w pipeB_w 168 #define planeB_h pipeB_h 169 170 /* Flags for perf_boxes 171 */ 172 #define I915_BOX_RING_EMPTY 0x1 173 #define I915_BOX_FLIP 0x2 174 #define I915_BOX_WAIT 0x4 175 #define I915_BOX_TEXTURE_LOAD 0x8 176 #define I915_BOX_LOST_CONTEXT 0x10 177 178 /* 179 * i915 specific ioctls. 180 * 181 * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie 182 * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset 183 * against DRM_COMMAND_BASE and should be between [0x0, 0x60). 184 */ 185 #define DRM_I915_INIT 0x00 186 #define DRM_I915_FLUSH 0x01 187 #define DRM_I915_FLIP 0x02 188 #define DRM_I915_BATCHBUFFER 0x03 189 #define DRM_I915_IRQ_EMIT 0x04 190 #define DRM_I915_IRQ_WAIT 0x05 191 #define DRM_I915_GETPARAM 0x06 192 #define DRM_I915_SETPARAM 0x07 193 #define DRM_I915_ALLOC 0x08 194 #define DRM_I915_FREE 0x09 195 #define DRM_I915_INIT_HEAP 0x0a 196 #define DRM_I915_CMDBUFFER 0x0b 197 #define DRM_I915_DESTROY_HEAP 0x0c 198 #define DRM_I915_SET_VBLANK_PIPE 0x0d 199 #define DRM_I915_GET_VBLANK_PIPE 0x0e 200 #define DRM_I915_VBLANK_SWAP 0x0f 201 #define DRM_I915_HWS_ADDR 0x11 202 #define DRM_I915_GEM_INIT 0x13 203 #define DRM_I915_GEM_EXECBUFFER 0x14 204 #define DRM_I915_GEM_PIN 0x15 205 #define DRM_I915_GEM_UNPIN 0x16 206 #define DRM_I915_GEM_BUSY 0x17 207 #define DRM_I915_GEM_THROTTLE 0x18 208 #define DRM_I915_GEM_ENTERVT 0x19 209 #define DRM_I915_GEM_LEAVEVT 0x1a 210 #define DRM_I915_GEM_CREATE 0x1b 211 #define DRM_I915_GEM_PREAD 0x1c 212 #define DRM_I915_GEM_PWRITE 0x1d 213 #define DRM_I915_GEM_MMAP 0x1e 214 #define DRM_I915_GEM_SET_DOMAIN 0x1f 215 #define DRM_I915_GEM_SW_FINISH 0x20 216 #define DRM_I915_GEM_SET_TILING 0x21 217 #define DRM_I915_GEM_GET_TILING 0x22 218 #define DRM_I915_GEM_GET_APERTURE 0x23 219 #define DRM_I915_GEM_MMAP_GTT 0x24 220 #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 221 #define DRM_I915_GEM_MADVISE 0x26 222 #define DRM_I915_OVERLAY_PUT_IMAGE 0x27 223 #define DRM_I915_OVERLAY_ATTRS 0x28 224 #define DRM_I915_GEM_EXECBUFFER2 0x29 225 #define DRM_I915_GET_SPRITE_COLORKEY 0x2a 226 #define DRM_I915_SET_SPRITE_COLORKEY 0x2b 227 #define DRM_I915_GEM_WAIT 0x2c 228 #define DRM_I915_GEM_CONTEXT_CREATE 0x2d 229 #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e 230 #define DRM_I915_GEM_SET_CACHING 0x2f 231 #define DRM_I915_GEM_GET_CACHING 0x30 232 #define DRM_I915_REG_READ 0x31 233 #define DRM_I915_GET_RESET_STATS 0x32 234 #define DRM_I915_GEM_USERPTR 0x33 235 #define DRM_I915_GEM_CONTEXT_GETPARAM 0x34 236 #define DRM_I915_GEM_CONTEXT_SETPARAM 0x35 237 238 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 239 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 240 #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) 241 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 242 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 243 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 244 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 245 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 246 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 247 #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 248 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 249 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 250 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 251 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 252 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 253 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 254 #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) 255 #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 256 #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 257 #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 258 #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 259 #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 260 #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 261 #define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) 262 #define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) 263 #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 264 #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 265 #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 266 #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 267 #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 268 #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 269 #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 270 #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 271 #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 272 #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 273 #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 274 #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 275 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 276 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 277 #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 278 #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) 279 #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 280 #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 281 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 282 #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) 283 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) 284 #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) 285 #define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) 286 #define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats) 287 #define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr) 288 #define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param) 289 #define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param) 290 291 /* Allow drivers to submit batchbuffers directly to hardware, relying 292 * on the security mechanisms provided by hardware. 293 */ 294 typedef struct drm_i915_batchbuffer { 295 int start; /* agp offset */ 296 int used; /* nr bytes in use */ 297 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 298 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 299 int num_cliprects; /* mulitpass with multiple cliprects? */ 300 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 301 } drm_i915_batchbuffer_t; 302 303 /* As above, but pass a pointer to userspace buffer which can be 304 * validated by the kernel prior to sending to hardware. 305 */ 306 typedef struct _drm_i915_cmdbuffer { 307 char __user *buf; /* pointer to userspace command buffer */ 308 int sz; /* nr bytes in buf */ 309 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 310 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 311 int num_cliprects; /* mulitpass with multiple cliprects? */ 312 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 313 } drm_i915_cmdbuffer_t; 314 315 /* Userspace can request & wait on irq's: 316 */ 317 typedef struct drm_i915_irq_emit { 318 int __user *irq_seq; 319 } drm_i915_irq_emit_t; 320 321 typedef struct drm_i915_irq_wait { 322 int irq_seq; 323 } drm_i915_irq_wait_t; 324 325 /* Ioctl to query kernel params: 326 */ 327 #define I915_PARAM_IRQ_ACTIVE 1 328 #define I915_PARAM_ALLOW_BATCHBUFFER 2 329 #define I915_PARAM_LAST_DISPATCH 3 330 #define I915_PARAM_CHIPSET_ID 4 331 #define I915_PARAM_HAS_GEM 5 332 #define I915_PARAM_NUM_FENCES_AVAIL 6 333 #define I915_PARAM_HAS_OVERLAY 7 334 #define I915_PARAM_HAS_PAGEFLIPPING 8 335 #define I915_PARAM_HAS_EXECBUF2 9 336 #define I915_PARAM_HAS_BSD 10 337 #define I915_PARAM_HAS_BLT 11 338 #define I915_PARAM_HAS_RELAXED_FENCING 12 339 #define I915_PARAM_HAS_COHERENT_RINGS 13 340 #define I915_PARAM_HAS_EXEC_CONSTANTS 14 341 #define I915_PARAM_HAS_RELAXED_DELTA 15 342 #define I915_PARAM_HAS_GEN7_SOL_RESET 16 343 #define I915_PARAM_HAS_LLC 17 344 #define I915_PARAM_HAS_ALIASING_PPGTT 18 345 #define I915_PARAM_HAS_WAIT_TIMEOUT 19 346 #define I915_PARAM_HAS_SEMAPHORES 20 347 #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 348 #define I915_PARAM_HAS_VEBOX 22 349 #define I915_PARAM_HAS_SECURE_BATCHES 23 350 #define I915_PARAM_HAS_PINNED_BATCHES 24 351 #define I915_PARAM_HAS_EXEC_NO_RELOC 25 352 #define I915_PARAM_HAS_EXEC_HANDLE_LUT 26 353 #define I915_PARAM_HAS_WT 27 354 #define I915_PARAM_CMD_PARSER_VERSION 28 355 #define I915_PARAM_HAS_COHERENT_PHYS_GTT 29 356 #define I915_PARAM_MMAP_VERSION 30 357 #define I915_PARAM_HAS_BSD2 31 358 #define I915_PARAM_REVISION 32 359 #define I915_PARAM_SUBSLICE_TOTAL 33 360 #define I915_PARAM_EU_TOTAL 34 361 #define I915_PARAM_HAS_GPU_RESET 35 362 #define I915_PARAM_HAS_RESOURCE_STREAMER 36 363 #define I915_PARAM_HAS_EXEC_SOFTPIN 37 364 #define I915_PARAM_HAS_POOLED_EU 38 365 #define I915_PARAM_MIN_EU_IN_POOL 39 366 367 typedef struct drm_i915_getparam { 368 __s32 param; 369 /* 370 * WARNING: Using pointers instead of fixed-size u64 means we need to write 371 * compat32 code. Don't repeat this mistake. 372 */ 373 int __user *value; 374 } drm_i915_getparam_t; 375 376 /* Ioctl to set kernel params: 377 */ 378 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 379 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 380 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 381 #define I915_SETPARAM_NUM_USED_FENCES 4 382 383 typedef struct drm_i915_setparam { 384 int param; 385 int value; 386 } drm_i915_setparam_t; 387 388 /* A memory manager for regions of shared memory: 389 */ 390 #define I915_MEM_REGION_AGP 1 391 392 typedef struct drm_i915_mem_alloc { 393 int region; 394 int alignment; 395 int size; 396 int __user *region_offset; /* offset from start of fb or agp */ 397 } drm_i915_mem_alloc_t; 398 399 typedef struct drm_i915_mem_free { 400 int region; 401 int region_offset; 402 } drm_i915_mem_free_t; 403 404 typedef struct drm_i915_mem_init_heap { 405 int region; 406 int size; 407 int start; 408 } drm_i915_mem_init_heap_t; 409 410 /* Allow memory manager to be torn down and re-initialized (eg on 411 * rotate): 412 */ 413 typedef struct drm_i915_mem_destroy_heap { 414 int region; 415 } drm_i915_mem_destroy_heap_t; 416 417 /* Allow X server to configure which pipes to monitor for vblank signals 418 */ 419 #define DRM_I915_VBLANK_PIPE_A 1 420 #define DRM_I915_VBLANK_PIPE_B 2 421 422 typedef struct drm_i915_vblank_pipe { 423 int pipe; 424 } drm_i915_vblank_pipe_t; 425 426 /* Schedule buffer swap at given vertical blank: 427 */ 428 typedef struct drm_i915_vblank_swap { 429 drm_drawable_t drawable; 430 enum drm_vblank_seq_type seqtype; 431 unsigned int sequence; 432 } drm_i915_vblank_swap_t; 433 434 typedef struct drm_i915_hws_addr { 435 __u64 addr; 436 } drm_i915_hws_addr_t; 437 438 struct drm_i915_gem_init { 439 /** 440 * Beginning offset in the GTT to be managed by the DRM memory 441 * manager. 442 */ 443 __u64 gtt_start; 444 /** 445 * Ending offset in the GTT to be managed by the DRM memory 446 * manager. 447 */ 448 __u64 gtt_end; 449 }; 450 451 struct drm_i915_gem_create { 452 /** 453 * Requested size for the object. 454 * 455 * The (page-aligned) allocated size for the object will be returned. 456 */ 457 __u64 size; 458 /** 459 * Returned handle for the object. 460 * 461 * Object handles are nonzero. 462 */ 463 __u32 handle; 464 __u32 pad; 465 }; 466 467 struct drm_i915_gem_pread { 468 /** Handle for the object being read. */ 469 __u32 handle; 470 __u32 pad; 471 /** Offset into the object to read from */ 472 __u64 offset; 473 /** Length of data to read */ 474 __u64 size; 475 /** 476 * Pointer to write the data into. 477 * 478 * This is a fixed-size type for 32/64 compatibility. 479 */ 480 __u64 data_ptr; 481 }; 482 483 struct drm_i915_gem_pwrite { 484 /** Handle for the object being written to. */ 485 __u32 handle; 486 __u32 pad; 487 /** Offset into the object to write to */ 488 __u64 offset; 489 /** Length of data to write */ 490 __u64 size; 491 /** 492 * Pointer to read the data from. 493 * 494 * This is a fixed-size type for 32/64 compatibility. 495 */ 496 __u64 data_ptr; 497 }; 498 499 struct drm_i915_gem_mmap { 500 /** Handle for the object being mapped. */ 501 __u32 handle; 502 __u32 pad; 503 /** Offset in the object to map. */ 504 __u64 offset; 505 /** 506 * Length of data to map. 507 * 508 * The value will be page-aligned. 509 */ 510 __u64 size; 511 /** 512 * Returned pointer the data was mapped at. 513 * 514 * This is a fixed-size type for 32/64 compatibility. 515 */ 516 __u64 addr_ptr; 517 518 /** 519 * Flags for extended behaviour. 520 * 521 * Added in version 2. 522 */ 523 __u64 flags; 524 #define I915_MMAP_WC 0x1 525 }; 526 527 struct drm_i915_gem_mmap_gtt { 528 /** Handle for the object being mapped. */ 529 __u32 handle; 530 __u32 pad; 531 /** 532 * Fake offset to use for subsequent mmap call 533 * 534 * This is a fixed-size type for 32/64 compatibility. 535 */ 536 __u64 offset; 537 }; 538 539 struct drm_i915_gem_set_domain { 540 /** Handle for the object */ 541 __u32 handle; 542 543 /** New read domains */ 544 __u32 read_domains; 545 546 /** New write domain */ 547 __u32 write_domain; 548 }; 549 550 struct drm_i915_gem_sw_finish { 551 /** Handle for the object */ 552 __u32 handle; 553 }; 554 555 struct drm_i915_gem_relocation_entry { 556 /** 557 * Handle of the buffer being pointed to by this relocation entry. 558 * 559 * It's appealing to make this be an index into the mm_validate_entry 560 * list to refer to the buffer, but this allows the driver to create 561 * a relocation list for state buffers and not re-write it per 562 * exec using the buffer. 563 */ 564 __u32 target_handle; 565 566 /** 567 * Value to be added to the offset of the target buffer to make up 568 * the relocation entry. 569 */ 570 __u32 delta; 571 572 /** Offset in the buffer the relocation entry will be written into */ 573 __u64 offset; 574 575 /** 576 * Offset value of the target buffer that the relocation entry was last 577 * written as. 578 * 579 * If the buffer has the same offset as last time, we can skip syncing 580 * and writing the relocation. This value is written back out by 581 * the execbuffer ioctl when the relocation is written. 582 */ 583 __u64 presumed_offset; 584 585 /** 586 * Target memory domains read by this operation. 587 */ 588 __u32 read_domains; 589 590 /** 591 * Target memory domains written by this operation. 592 * 593 * Note that only one domain may be written by the whole 594 * execbuffer operation, so that where there are conflicts, 595 * the application will get -EINVAL back. 596 */ 597 __u32 write_domain; 598 }; 599 600 /** @{ 601 * Intel memory domains 602 * 603 * Most of these just align with the various caches in 604 * the system and are used to flush and invalidate as 605 * objects end up cached in different domains. 606 */ 607 /** CPU cache */ 608 #define I915_GEM_DOMAIN_CPU 0x00000001 609 /** Render cache, used by 2D and 3D drawing */ 610 #define I915_GEM_DOMAIN_RENDER 0x00000002 611 /** Sampler cache, used by texture engine */ 612 #define I915_GEM_DOMAIN_SAMPLER 0x00000004 613 /** Command queue, used to load batch buffers */ 614 #define I915_GEM_DOMAIN_COMMAND 0x00000008 615 /** Instruction cache, used by shader programs */ 616 #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 617 /** Vertex address cache */ 618 #define I915_GEM_DOMAIN_VERTEX 0x00000020 619 /** GTT domain - aperture and scanout */ 620 #define I915_GEM_DOMAIN_GTT 0x00000040 621 /** @} */ 622 623 struct drm_i915_gem_exec_object { 624 /** 625 * User's handle for a buffer to be bound into the GTT for this 626 * operation. 627 */ 628 __u32 handle; 629 630 /** Number of relocations to be performed on this buffer */ 631 __u32 relocation_count; 632 /** 633 * Pointer to array of struct drm_i915_gem_relocation_entry containing 634 * the relocations to be performed in this buffer. 635 */ 636 __u64 relocs_ptr; 637 638 /** Required alignment in graphics aperture */ 639 __u64 alignment; 640 641 /** 642 * Returned value of the updated offset of the object, for future 643 * presumed_offset writes. 644 */ 645 __u64 offset; 646 }; 647 648 struct drm_i915_gem_execbuffer { 649 /** 650 * List of buffers to be validated with their relocations to be 651 * performend on them. 652 * 653 * This is a pointer to an array of struct drm_i915_gem_validate_entry. 654 * 655 * These buffers must be listed in an order such that all relocations 656 * a buffer is performing refer to buffers that have already appeared 657 * in the validate list. 658 */ 659 __u64 buffers_ptr; 660 __u32 buffer_count; 661 662 /** Offset in the batchbuffer to start execution from. */ 663 __u32 batch_start_offset; 664 /** Bytes used in batchbuffer from batch_start_offset */ 665 __u32 batch_len; 666 __u32 DR1; 667 __u32 DR4; 668 __u32 num_cliprects; 669 /** This is a struct drm_clip_rect *cliprects */ 670 __u64 cliprects_ptr; 671 }; 672 673 struct drm_i915_gem_exec_object2 { 674 /** 675 * User's handle for a buffer to be bound into the GTT for this 676 * operation. 677 */ 678 __u32 handle; 679 680 /** Number of relocations to be performed on this buffer */ 681 __u32 relocation_count; 682 /** 683 * Pointer to array of struct drm_i915_gem_relocation_entry containing 684 * the relocations to be performed in this buffer. 685 */ 686 __u64 relocs_ptr; 687 688 /** Required alignment in graphics aperture */ 689 __u64 alignment; 690 691 /** 692 * When the EXEC_OBJECT_PINNED flag is specified this is populated by 693 * the user with the GTT offset at which this object will be pinned. 694 * When the I915_EXEC_NO_RELOC flag is specified this must contain the 695 * presumed_offset of the object. 696 * During execbuffer2 the kernel populates it with the value of the 697 * current GTT offset of the object, for future presumed_offset writes. 698 */ 699 __u64 offset; 700 701 #define EXEC_OBJECT_NEEDS_FENCE (1<<0) 702 #define EXEC_OBJECT_NEEDS_GTT (1<<1) 703 #define EXEC_OBJECT_WRITE (1<<2) 704 #define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3) 705 #define EXEC_OBJECT_PINNED (1<<4) 706 #define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_PINNED<<1) 707 __u64 flags; 708 709 __u64 rsvd1; 710 __u64 rsvd2; 711 }; 712 713 struct drm_i915_gem_execbuffer2 { 714 /** 715 * List of gem_exec_object2 structs 716 */ 717 __u64 buffers_ptr; 718 __u32 buffer_count; 719 720 /** Offset in the batchbuffer to start execution from. */ 721 __u32 batch_start_offset; 722 /** Bytes used in batchbuffer from batch_start_offset */ 723 __u32 batch_len; 724 __u32 DR1; 725 __u32 DR4; 726 __u32 num_cliprects; 727 /** This is a struct drm_clip_rect *cliprects */ 728 __u64 cliprects_ptr; 729 #define I915_EXEC_RING_MASK (7<<0) 730 #define I915_EXEC_DEFAULT (0<<0) 731 #define I915_EXEC_RENDER (1<<0) 732 #define I915_EXEC_BSD (2<<0) 733 #define I915_EXEC_BLT (3<<0) 734 #define I915_EXEC_VEBOX (4<<0) 735 736 /* Used for switching the constants addressing mode on gen4+ RENDER ring. 737 * Gen6+ only supports relative addressing to dynamic state (default) and 738 * absolute addressing. 739 * 740 * These flags are ignored for the BSD and BLT rings. 741 */ 742 #define I915_EXEC_CONSTANTS_MASK (3<<6) 743 #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ 744 #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) 745 #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ 746 __u64 flags; 747 __u64 rsvd1; /* now used for context info */ 748 __u64 rsvd2; 749 }; 750 751 /** Resets the SO write offset registers for transform feedback on gen7. */ 752 #define I915_EXEC_GEN7_SOL_RESET (1<<8) 753 754 /** Request a privileged ("secure") batch buffer. Note only available for 755 * DRM_ROOT_ONLY | DRM_MASTER processes. 756 */ 757 #define I915_EXEC_SECURE (1<<9) 758 759 /** Inform the kernel that the batch is and will always be pinned. This 760 * negates the requirement for a workaround to be performed to avoid 761 * an incoherent CS (such as can be found on 830/845). If this flag is 762 * not passed, the kernel will endeavour to make sure the batch is 763 * coherent with the CS before execution. If this flag is passed, 764 * userspace assumes the responsibility for ensuring the same. 765 */ 766 #define I915_EXEC_IS_PINNED (1<<10) 767 768 /** Provide a hint to the kernel that the command stream and auxiliary 769 * state buffers already holds the correct presumed addresses and so the 770 * relocation process may be skipped if no buffers need to be moved in 771 * preparation for the execbuffer. 772 */ 773 #define I915_EXEC_NO_RELOC (1<<11) 774 775 /** Use the reloc.handle as an index into the exec object array rather 776 * than as the per-file handle. 777 */ 778 #define I915_EXEC_HANDLE_LUT (1<<12) 779 780 /** Used for switching BSD rings on the platforms with two BSD rings */ 781 #define I915_EXEC_BSD_SHIFT (13) 782 #define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT) 783 /* default ping-pong mode */ 784 #define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT) 785 #define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT) 786 #define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT) 787 788 /** Tell the kernel that the batchbuffer is processed by 789 * the resource streamer. 790 */ 791 #define I915_EXEC_RESOURCE_STREAMER (1<<15) 792 793 #define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_RESOURCE_STREAMER<<1) 794 795 #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) 796 #define i915_execbuffer2_set_context_id(eb2, context) \ 797 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK 798 #define i915_execbuffer2_get_context_id(eb2) \ 799 ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) 800 801 struct drm_i915_gem_pin { 802 /** Handle of the buffer to be pinned. */ 803 __u32 handle; 804 __u32 pad; 805 806 /** alignment required within the aperture */ 807 __u64 alignment; 808 809 /** Returned GTT offset of the buffer. */ 810 __u64 offset; 811 }; 812 813 struct drm_i915_gem_unpin { 814 /** Handle of the buffer to be unpinned. */ 815 __u32 handle; 816 __u32 pad; 817 }; 818 819 struct drm_i915_gem_busy { 820 /** Handle of the buffer to check for busy */ 821 __u32 handle; 822 823 /** Return busy status 824 * 825 * A return of 0 implies that the object is idle (after 826 * having flushed any pending activity), and a non-zero return that 827 * the object is still in-flight on the GPU. (The GPU has not yet 828 * signaled completion for all pending requests that reference the 829 * object.) 830 * 831 * The returned dword is split into two fields to indicate both 832 * the engines on which the object is being read, and the 833 * engine on which it is currently being written (if any). 834 * 835 * The low word (bits 0:15) indicate if the object is being written 836 * to by any engine (there can only be one, as the GEM implicit 837 * synchronisation rules force writes to be serialised). Only the 838 * engine for the last write is reported. 839 * 840 * The high word (bits 16:31) are a bitmask of which engines are 841 * currently reading from the object. Multiple engines may be 842 * reading from the object simultaneously. 843 * 844 * The value of each engine is the same as specified in the 845 * EXECBUFFER2 ioctl, i.e. I915_EXEC_RENDER, I915_EXEC_BSD etc. 846 * Note I915_EXEC_DEFAULT is a symbolic value and is mapped to 847 * the I915_EXEC_RENDER engine for execution, and so it is never 848 * reported as active itself. Some hardware may have parallel 849 * execution engines, e.g. multiple media engines, which are 850 * mapped to the same identifier in the EXECBUFFER2 ioctl and 851 * so are not separately reported for busyness. 852 */ 853 __u32 busy; 854 }; 855 856 /** 857 * I915_CACHING_NONE 858 * 859 * GPU access is not coherent with cpu caches. Default for machines without an 860 * LLC. 861 */ 862 #define I915_CACHING_NONE 0 863 /** 864 * I915_CACHING_CACHED 865 * 866 * GPU access is coherent with cpu caches and furthermore the data is cached in 867 * last-level caches shared between cpu cores and the gpu GT. Default on 868 * machines with HAS_LLC. 869 */ 870 #define I915_CACHING_CACHED 1 871 /** 872 * I915_CACHING_DISPLAY 873 * 874 * Special GPU caching mode which is coherent with the scanout engines. 875 * Transparently falls back to I915_CACHING_NONE on platforms where no special 876 * cache mode (like write-through or gfdt flushing) is available. The kernel 877 * automatically sets this mode when using a buffer as a scanout target. 878 * Userspace can manually set this mode to avoid a costly stall and clflush in 879 * the hotpath of drawing the first frame. 880 */ 881 #define I915_CACHING_DISPLAY 2 882 883 struct drm_i915_gem_caching { 884 /** 885 * Handle of the buffer to set/get the caching level of. */ 886 __u32 handle; 887 888 /** 889 * Cacheing level to apply or return value 890 * 891 * bits0-15 are for generic caching control (i.e. the above defined 892 * values). bits16-31 are reserved for platform-specific variations 893 * (e.g. l3$ caching on gen7). */ 894 __u32 caching; 895 }; 896 897 #define I915_TILING_NONE 0 898 #define I915_TILING_X 1 899 #define I915_TILING_Y 2 900 901 #define I915_BIT_6_SWIZZLE_NONE 0 902 #define I915_BIT_6_SWIZZLE_9 1 903 #define I915_BIT_6_SWIZZLE_9_10 2 904 #define I915_BIT_6_SWIZZLE_9_11 3 905 #define I915_BIT_6_SWIZZLE_9_10_11 4 906 /* Not seen by userland */ 907 #define I915_BIT_6_SWIZZLE_UNKNOWN 5 908 /* Seen by userland. */ 909 #define I915_BIT_6_SWIZZLE_9_17 6 910 #define I915_BIT_6_SWIZZLE_9_10_17 7 911 912 struct drm_i915_gem_set_tiling { 913 /** Handle of the buffer to have its tiling state updated */ 914 __u32 handle; 915 916 /** 917 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 918 * I915_TILING_Y). 919 * 920 * This value is to be set on request, and will be updated by the 921 * kernel on successful return with the actual chosen tiling layout. 922 * 923 * The tiling mode may be demoted to I915_TILING_NONE when the system 924 * has bit 6 swizzling that can't be managed correctly by GEM. 925 * 926 * Buffer contents become undefined when changing tiling_mode. 927 */ 928 __u32 tiling_mode; 929 930 /** 931 * Stride in bytes for the object when in I915_TILING_X or 932 * I915_TILING_Y. 933 */ 934 __u32 stride; 935 936 /** 937 * Returned address bit 6 swizzling required for CPU access through 938 * mmap mapping. 939 */ 940 __u32 swizzle_mode; 941 }; 942 943 struct drm_i915_gem_get_tiling { 944 /** Handle of the buffer to get tiling state for. */ 945 __u32 handle; 946 947 /** 948 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 949 * I915_TILING_Y). 950 */ 951 __u32 tiling_mode; 952 953 /** 954 * Returned address bit 6 swizzling required for CPU access through 955 * mmap mapping. 956 */ 957 __u32 swizzle_mode; 958 959 /** 960 * Returned address bit 6 swizzling required for CPU access through 961 * mmap mapping whilst bound. 962 */ 963 __u32 phys_swizzle_mode; 964 }; 965 966 struct drm_i915_gem_get_aperture { 967 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ 968 __u64 aper_size; 969 970 /** 971 * Available space in the aperture used by i915_gem_execbuffer, in 972 * bytes 973 */ 974 __u64 aper_available_size; 975 }; 976 977 struct drm_i915_get_pipe_from_crtc_id { 978 /** ID of CRTC being requested **/ 979 __u32 crtc_id; 980 981 /** pipe of requested CRTC **/ 982 __u32 pipe; 983 }; 984 985 #define I915_MADV_WILLNEED 0 986 #define I915_MADV_DONTNEED 1 987 #define __I915_MADV_PURGED 2 /* internal state */ 988 989 struct drm_i915_gem_madvise { 990 /** Handle of the buffer to change the backing store advice */ 991 __u32 handle; 992 993 /* Advice: either the buffer will be needed again in the near future, 994 * or wont be and could be discarded under memory pressure. 995 */ 996 __u32 madv; 997 998 /** Whether the backing store still exists. */ 999 __u32 retained; 1000 }; 1001 1002 /* flags */ 1003 #define I915_OVERLAY_TYPE_MASK 0xff 1004 #define I915_OVERLAY_YUV_PLANAR 0x01 1005 #define I915_OVERLAY_YUV_PACKED 0x02 1006 #define I915_OVERLAY_RGB 0x03 1007 1008 #define I915_OVERLAY_DEPTH_MASK 0xff00 1009 #define I915_OVERLAY_RGB24 0x1000 1010 #define I915_OVERLAY_RGB16 0x2000 1011 #define I915_OVERLAY_RGB15 0x3000 1012 #define I915_OVERLAY_YUV422 0x0100 1013 #define I915_OVERLAY_YUV411 0x0200 1014 #define I915_OVERLAY_YUV420 0x0300 1015 #define I915_OVERLAY_YUV410 0x0400 1016 1017 #define I915_OVERLAY_SWAP_MASK 0xff0000 1018 #define I915_OVERLAY_NO_SWAP 0x000000 1019 #define I915_OVERLAY_UV_SWAP 0x010000 1020 #define I915_OVERLAY_Y_SWAP 0x020000 1021 #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 1022 1023 #define I915_OVERLAY_FLAGS_MASK 0xff000000 1024 #define I915_OVERLAY_ENABLE 0x01000000 1025 1026 struct drm_intel_overlay_put_image { 1027 /* various flags and src format description */ 1028 __u32 flags; 1029 /* source picture description */ 1030 __u32 bo_handle; 1031 /* stride values and offsets are in bytes, buffer relative */ 1032 __u16 stride_Y; /* stride for packed formats */ 1033 __u16 stride_UV; 1034 __u32 offset_Y; /* offset for packet formats */ 1035 __u32 offset_U; 1036 __u32 offset_V; 1037 /* in pixels */ 1038 __u16 src_width; 1039 __u16 src_height; 1040 /* to compensate the scaling factors for partially covered surfaces */ 1041 __u16 src_scan_width; 1042 __u16 src_scan_height; 1043 /* output crtc description */ 1044 __u32 crtc_id; 1045 __u16 dst_x; 1046 __u16 dst_y; 1047 __u16 dst_width; 1048 __u16 dst_height; 1049 }; 1050 1051 /* flags */ 1052 #define I915_OVERLAY_UPDATE_ATTRS (1<<0) 1053 #define I915_OVERLAY_UPDATE_GAMMA (1<<1) 1054 #define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2) 1055 struct drm_intel_overlay_attrs { 1056 __u32 flags; 1057 __u32 color_key; 1058 __s32 brightness; 1059 __u32 contrast; 1060 __u32 saturation; 1061 __u32 gamma0; 1062 __u32 gamma1; 1063 __u32 gamma2; 1064 __u32 gamma3; 1065 __u32 gamma4; 1066 __u32 gamma5; 1067 }; 1068 1069 /* 1070 * Intel sprite handling 1071 * 1072 * Color keying works with a min/mask/max tuple. Both source and destination 1073 * color keying is allowed. 1074 * 1075 * Source keying: 1076 * Sprite pixels within the min & max values, masked against the color channels 1077 * specified in the mask field, will be transparent. All other pixels will 1078 * be displayed on top of the primary plane. For RGB surfaces, only the min 1079 * and mask fields will be used; ranged compares are not allowed. 1080 * 1081 * Destination keying: 1082 * Primary plane pixels that match the min value, masked against the color 1083 * channels specified in the mask field, will be replaced by corresponding 1084 * pixels from the sprite plane. 1085 * 1086 * Note that source & destination keying are exclusive; only one can be 1087 * active on a given plane. 1088 */ 1089 1090 #define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */ 1091 #define I915_SET_COLORKEY_DESTINATION (1<<1) 1092 #define I915_SET_COLORKEY_SOURCE (1<<2) 1093 struct drm_intel_sprite_colorkey { 1094 __u32 plane_id; 1095 __u32 min_value; 1096 __u32 channel_mask; 1097 __u32 max_value; 1098 __u32 flags; 1099 }; 1100 1101 struct drm_i915_gem_wait { 1102 /** Handle of BO we shall wait on */ 1103 __u32 bo_handle; 1104 __u32 flags; 1105 /** Number of nanoseconds to wait, Returns time remaining. */ 1106 __s64 timeout_ns; 1107 }; 1108 1109 struct drm_i915_gem_context_create { 1110 /* output: id of new context*/ 1111 __u32 ctx_id; 1112 __u32 pad; 1113 }; 1114 1115 struct drm_i915_gem_context_destroy { 1116 __u32 ctx_id; 1117 __u32 pad; 1118 }; 1119 1120 struct drm_i915_reg_read { 1121 /* 1122 * Register offset. 1123 * For 64bit wide registers where the upper 32bits don't immediately 1124 * follow the lower 32bits, the offset of the lower 32bits must 1125 * be specified 1126 */ 1127 __u64 offset; 1128 __u64 val; /* Return value */ 1129 }; 1130 /* Known registers: 1131 * 1132 * Render engine timestamp - 0x2358 + 64bit - gen7+ 1133 * - Note this register returns an invalid value if using the default 1134 * single instruction 8byte read, in order to workaround that use 1135 * offset (0x2538 | 1) instead. 1136 * 1137 */ 1138 1139 struct drm_i915_reset_stats { 1140 __u32 ctx_id; 1141 __u32 flags; 1142 1143 /* All resets since boot/module reload, for all contexts */ 1144 __u32 reset_count; 1145 1146 /* Number of batches lost when active in GPU, for this context */ 1147 __u32 batch_active; 1148 1149 /* Number of batches lost pending for execution, for this context */ 1150 __u32 batch_pending; 1151 1152 __u32 pad; 1153 }; 1154 1155 struct drm_i915_gem_userptr { 1156 __u64 user_ptr; 1157 __u64 user_size; 1158 __u32 flags; 1159 #define I915_USERPTR_READ_ONLY 0x1 1160 #define I915_USERPTR_UNSYNCHRONIZED 0x80000000 1161 /** 1162 * Returned handle for the object. 1163 * 1164 * Object handles are nonzero. 1165 */ 1166 __u32 handle; 1167 }; 1168 1169 struct drm_i915_gem_context_param { 1170 __u32 ctx_id; 1171 __u32 size; 1172 __u64 param; 1173 #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1 1174 #define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2 1175 #define I915_CONTEXT_PARAM_GTT_SIZE 0x3 1176 #define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4 1177 __u64 value; 1178 }; 1179 1180 #if defined(__cplusplus) 1181 } 1182 #endif 1183 1184 #endif /* _UAPI_I915_DRM_H_ */ 1185