1718dceddSDavid Howells /* 2718dceddSDavid Howells * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 3718dceddSDavid Howells * All Rights Reserved. 4718dceddSDavid Howells * 5718dceddSDavid Howells * Permission is hereby granted, free of charge, to any person obtaining a 6718dceddSDavid Howells * copy of this software and associated documentation files (the 7718dceddSDavid Howells * "Software"), to deal in the Software without restriction, including 8718dceddSDavid Howells * without limitation the rights to use, copy, modify, merge, publish, 9718dceddSDavid Howells * distribute, sub license, and/or sell copies of the Software, and to 10718dceddSDavid Howells * permit persons to whom the Software is furnished to do so, subject to 11718dceddSDavid Howells * the following conditions: 12718dceddSDavid Howells * 13718dceddSDavid Howells * The above copyright notice and this permission notice (including the 14718dceddSDavid Howells * next paragraph) shall be included in all copies or substantial portions 15718dceddSDavid Howells * of the Software. 16718dceddSDavid Howells * 17718dceddSDavid Howells * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18718dceddSDavid Howells * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19718dceddSDavid Howells * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20718dceddSDavid Howells * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 21718dceddSDavid Howells * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22718dceddSDavid Howells * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23718dceddSDavid Howells * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24718dceddSDavid Howells * 25718dceddSDavid Howells */ 26718dceddSDavid Howells 27718dceddSDavid Howells #ifndef _UAPI_I915_DRM_H_ 28718dceddSDavid Howells #define _UAPI_I915_DRM_H_ 29718dceddSDavid Howells 301049102fSGabriel Laskar #include "drm.h" 31718dceddSDavid Howells 32b1c1f5c4SEmil Velikov #if defined(__cplusplus) 33b1c1f5c4SEmil Velikov extern "C" { 34b1c1f5c4SEmil Velikov #endif 35b1c1f5c4SEmil Velikov 36718dceddSDavid Howells /* Please note that modifications to all structs defined here are 37718dceddSDavid Howells * subject to backwards-compatibility constraints. 38718dceddSDavid Howells */ 39718dceddSDavid Howells 40cce723edSBen Widawsky /** 41cce723edSBen Widawsky * DOC: uevents generated by i915 on it's device node 42cce723edSBen Widawsky * 43cce723edSBen Widawsky * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch 44cce723edSBen Widawsky * event from the gpu l3 cache. Additional information supplied is ROW, 4535a85ac6SBen Widawsky * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep 4635a85ac6SBen Widawsky * track of these events and if a specific cache-line seems to have a 4735a85ac6SBen Widawsky * persistent error remap it with the l3 remapping tool supplied in 4835a85ac6SBen Widawsky * intel-gpu-tools. The value supplied with the event is always 1. 49cce723edSBen Widawsky * 50cce723edSBen Widawsky * I915_ERROR_UEVENT - Generated upon error detection, currently only via 51cce723edSBen Widawsky * hangcheck. The error detection event is a good indicator of when things 52cce723edSBen Widawsky * began to go badly. The value supplied with the event is a 1 upon error 53cce723edSBen Widawsky * detection, and a 0 upon reset completion, signifying no more error 54cce723edSBen Widawsky * exists. NOTE: Disabling hangcheck or reset via module parameter will 55cce723edSBen Widawsky * cause the related events to not be seen. 56cce723edSBen Widawsky * 57cce723edSBen Widawsky * I915_RESET_UEVENT - Event is generated just before an attempt to reset the 58cce723edSBen Widawsky * the GPU. The value supplied with the event is always 1. NOTE: Disable 59cce723edSBen Widawsky * reset via module parameter will cause this event to not be seen. 60cce723edSBen Widawsky */ 61cce723edSBen Widawsky #define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR" 62cce723edSBen Widawsky #define I915_ERROR_UEVENT "ERROR" 63cce723edSBen Widawsky #define I915_RESET_UEVENT "RESET" 64718dceddSDavid Howells 653373ce2eSImre Deak /* 669d1305efSChris Wilson * i915_user_extension: Base class for defining a chain of extensions 679d1305efSChris Wilson * 689d1305efSChris Wilson * Many interfaces need to grow over time. In most cases we can simply 699d1305efSChris Wilson * extend the struct and have userspace pass in more data. Another option, 709d1305efSChris Wilson * as demonstrated by Vulkan's approach to providing extensions for forward 719d1305efSChris Wilson * and backward compatibility, is to use a list of optional structs to 729d1305efSChris Wilson * provide those extra details. 739d1305efSChris Wilson * 749d1305efSChris Wilson * The key advantage to using an extension chain is that it allows us to 759d1305efSChris Wilson * redefine the interface more easily than an ever growing struct of 769d1305efSChris Wilson * increasing complexity, and for large parts of that interface to be 779d1305efSChris Wilson * entirely optional. The downside is more pointer chasing; chasing across 789d1305efSChris Wilson * the __user boundary with pointers encapsulated inside u64. 799d1305efSChris Wilson */ 809d1305efSChris Wilson struct i915_user_extension { 819d1305efSChris Wilson __u64 next_extension; 829d1305efSChris Wilson __u32 name; 839d1305efSChris Wilson __u32 flags; /* All undefined bits must be zero. */ 849d1305efSChris Wilson __u32 rsvd[4]; /* Reserved for future use; must be zero. */ 859d1305efSChris Wilson }; 869d1305efSChris Wilson 879d1305efSChris Wilson /* 883373ce2eSImre Deak * MOCS indexes used for GPU surfaces, defining the cacheability of the 893373ce2eSImre Deak * surface data and the coherency for this data wrt. CPU vs. GPU accesses. 903373ce2eSImre Deak */ 913373ce2eSImre Deak enum i915_mocs_table_index { 923373ce2eSImre Deak /* 933373ce2eSImre Deak * Not cached anywhere, coherency between CPU and GPU accesses is 943373ce2eSImre Deak * guaranteed. 953373ce2eSImre Deak */ 963373ce2eSImre Deak I915_MOCS_UNCACHED, 973373ce2eSImre Deak /* 983373ce2eSImre Deak * Cacheability and coherency controlled by the kernel automatically 993373ce2eSImre Deak * based on the DRM_I915_GEM_SET_CACHING IOCTL setting and the current 1003373ce2eSImre Deak * usage of the surface (used for display scanout or not). 1013373ce2eSImre Deak */ 1023373ce2eSImre Deak I915_MOCS_PTE, 1033373ce2eSImre Deak /* 1043373ce2eSImre Deak * Cached in all GPU caches available on the platform. 1053373ce2eSImre Deak * Coherency between CPU and GPU accesses to the surface is not 1063373ce2eSImre Deak * guaranteed without extra synchronization. 1073373ce2eSImre Deak */ 1083373ce2eSImre Deak I915_MOCS_CACHED, 1093373ce2eSImre Deak }; 1103373ce2eSImre Deak 1111803fcbcSTvrtko Ursulin /* 1121803fcbcSTvrtko Ursulin * Different engines serve different roles, and there may be more than one 1131803fcbcSTvrtko Ursulin * engine serving each role. enum drm_i915_gem_engine_class provides a 1141803fcbcSTvrtko Ursulin * classification of the role of the engine, which may be used when requesting 1151803fcbcSTvrtko Ursulin * operations to be performed on a certain subset of engines, or for providing 1161803fcbcSTvrtko Ursulin * information about that group. 1171803fcbcSTvrtko Ursulin */ 1181803fcbcSTvrtko Ursulin enum drm_i915_gem_engine_class { 1191803fcbcSTvrtko Ursulin I915_ENGINE_CLASS_RENDER = 0, 1201803fcbcSTvrtko Ursulin I915_ENGINE_CLASS_COPY = 1, 1211803fcbcSTvrtko Ursulin I915_ENGINE_CLASS_VIDEO = 2, 1221803fcbcSTvrtko Ursulin I915_ENGINE_CLASS_VIDEO_ENHANCE = 3, 1231803fcbcSTvrtko Ursulin 124be03564bSChris Wilson /* should be kept compact */ 125be03564bSChris Wilson 1261803fcbcSTvrtko Ursulin I915_ENGINE_CLASS_INVALID = -1 1271803fcbcSTvrtko Ursulin }; 1281803fcbcSTvrtko Ursulin 129d1172ab3SChris Wilson /* 130d1172ab3SChris Wilson * There may be more than one engine fulfilling any role within the system. 131d1172ab3SChris Wilson * Each engine of a class is given a unique instance number and therefore 132d1172ab3SChris Wilson * any engine can be specified by its class:instance tuplet. APIs that allow 133d1172ab3SChris Wilson * access to any engine in the system will use struct i915_engine_class_instance 134d1172ab3SChris Wilson * for this identification. 135d1172ab3SChris Wilson */ 136d1172ab3SChris Wilson struct i915_engine_class_instance { 137d1172ab3SChris Wilson __u16 engine_class; /* see enum drm_i915_gem_engine_class */ 138d1172ab3SChris Wilson __u16 engine_instance; 139976b55f0SChris Wilson #define I915_ENGINE_CLASS_INVALID_NONE -1 1406d06779eSChris Wilson #define I915_ENGINE_CLASS_INVALID_VIRTUAL -2 141d1172ab3SChris Wilson }; 142d1172ab3SChris Wilson 143b46a33e2STvrtko Ursulin /** 144b46a33e2STvrtko Ursulin * DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915 145b46a33e2STvrtko Ursulin * 146b46a33e2STvrtko Ursulin */ 147b46a33e2STvrtko Ursulin 148b46a33e2STvrtko Ursulin enum drm_i915_pmu_engine_sample { 149b46a33e2STvrtko Ursulin I915_SAMPLE_BUSY = 0, 150b46a33e2STvrtko Ursulin I915_SAMPLE_WAIT = 1, 151b552ae44STvrtko Ursulin I915_SAMPLE_SEMA = 2 152b46a33e2STvrtko Ursulin }; 153b46a33e2STvrtko Ursulin 154b46a33e2STvrtko Ursulin #define I915_PMU_SAMPLE_BITS (4) 155b46a33e2STvrtko Ursulin #define I915_PMU_SAMPLE_MASK (0xf) 156b46a33e2STvrtko Ursulin #define I915_PMU_SAMPLE_INSTANCE_BITS (8) 157b46a33e2STvrtko Ursulin #define I915_PMU_CLASS_SHIFT \ 158b46a33e2STvrtko Ursulin (I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS) 159b46a33e2STvrtko Ursulin 160b46a33e2STvrtko Ursulin #define __I915_PMU_ENGINE(class, instance, sample) \ 161b46a33e2STvrtko Ursulin ((class) << I915_PMU_CLASS_SHIFT | \ 162b46a33e2STvrtko Ursulin (instance) << I915_PMU_SAMPLE_BITS | \ 163b46a33e2STvrtko Ursulin (sample)) 164b46a33e2STvrtko Ursulin 165b46a33e2STvrtko Ursulin #define I915_PMU_ENGINE_BUSY(class, instance) \ 166b46a33e2STvrtko Ursulin __I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY) 167b46a33e2STvrtko Ursulin 168b46a33e2STvrtko Ursulin #define I915_PMU_ENGINE_WAIT(class, instance) \ 169b46a33e2STvrtko Ursulin __I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT) 170b46a33e2STvrtko Ursulin 171b46a33e2STvrtko Ursulin #define I915_PMU_ENGINE_SEMA(class, instance) \ 172b46a33e2STvrtko Ursulin __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA) 173b46a33e2STvrtko Ursulin 174b46a33e2STvrtko Ursulin #define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x)) 175b46a33e2STvrtko Ursulin 176b46a33e2STvrtko Ursulin #define I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0) 177b46a33e2STvrtko Ursulin #define I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1) 1780cd4684dSTvrtko Ursulin #define I915_PMU_INTERRUPTS __I915_PMU_OTHER(2) 1796060b6aeSTvrtko Ursulin #define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3) 1806060b6aeSTvrtko Ursulin 1813452fa30STvrtko Ursulin #define I915_PMU_LAST I915_PMU_RC6_RESIDENCY 182b46a33e2STvrtko Ursulin 183718dceddSDavid Howells /* Each region is a minimum of 16k, and there are at most 255 of them. 184718dceddSDavid Howells */ 185718dceddSDavid Howells #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use 186718dceddSDavid Howells * of chars for next/prev indices */ 187718dceddSDavid Howells #define I915_LOG_MIN_TEX_REGION_SIZE 14 188718dceddSDavid Howells 189718dceddSDavid Howells typedef struct _drm_i915_init { 190718dceddSDavid Howells enum { 191718dceddSDavid Howells I915_INIT_DMA = 0x01, 192718dceddSDavid Howells I915_CLEANUP_DMA = 0x02, 193718dceddSDavid Howells I915_RESUME_DMA = 0x03 194718dceddSDavid Howells } func; 195718dceddSDavid Howells unsigned int mmio_offset; 196718dceddSDavid Howells int sarea_priv_offset; 197718dceddSDavid Howells unsigned int ring_start; 198718dceddSDavid Howells unsigned int ring_end; 199718dceddSDavid Howells unsigned int ring_size; 200718dceddSDavid Howells unsigned int front_offset; 201718dceddSDavid Howells unsigned int back_offset; 202718dceddSDavid Howells unsigned int depth_offset; 203718dceddSDavid Howells unsigned int w; 204718dceddSDavid Howells unsigned int h; 205718dceddSDavid Howells unsigned int pitch; 206718dceddSDavid Howells unsigned int pitch_bits; 207718dceddSDavid Howells unsigned int back_pitch; 208718dceddSDavid Howells unsigned int depth_pitch; 209718dceddSDavid Howells unsigned int cpp; 210718dceddSDavid Howells unsigned int chipset; 211718dceddSDavid Howells } drm_i915_init_t; 212718dceddSDavid Howells 213718dceddSDavid Howells typedef struct _drm_i915_sarea { 214718dceddSDavid Howells struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 215718dceddSDavid Howells int last_upload; /* last time texture was uploaded */ 216718dceddSDavid Howells int last_enqueue; /* last time a buffer was enqueued */ 217718dceddSDavid Howells int last_dispatch; /* age of the most recently dispatched buffer */ 218718dceddSDavid Howells int ctxOwner; /* last context to upload state */ 219718dceddSDavid Howells int texAge; 220718dceddSDavid Howells int pf_enabled; /* is pageflipping allowed? */ 221718dceddSDavid Howells int pf_active; 222718dceddSDavid Howells int pf_current_page; /* which buffer is being displayed? */ 223718dceddSDavid Howells int perf_boxes; /* performance boxes to be displayed */ 224718dceddSDavid Howells int width, height; /* screen size in pixels */ 225718dceddSDavid Howells 226718dceddSDavid Howells drm_handle_t front_handle; 227718dceddSDavid Howells int front_offset; 228718dceddSDavid Howells int front_size; 229718dceddSDavid Howells 230718dceddSDavid Howells drm_handle_t back_handle; 231718dceddSDavid Howells int back_offset; 232718dceddSDavid Howells int back_size; 233718dceddSDavid Howells 234718dceddSDavid Howells drm_handle_t depth_handle; 235718dceddSDavid Howells int depth_offset; 236718dceddSDavid Howells int depth_size; 237718dceddSDavid Howells 238718dceddSDavid Howells drm_handle_t tex_handle; 239718dceddSDavid Howells int tex_offset; 240718dceddSDavid Howells int tex_size; 241718dceddSDavid Howells int log_tex_granularity; 242718dceddSDavid Howells int pitch; 243718dceddSDavid Howells int rotation; /* 0, 90, 180 or 270 */ 244718dceddSDavid Howells int rotated_offset; 245718dceddSDavid Howells int rotated_size; 246718dceddSDavid Howells int rotated_pitch; 247718dceddSDavid Howells int virtualX, virtualY; 248718dceddSDavid Howells 249718dceddSDavid Howells unsigned int front_tiled; 250718dceddSDavid Howells unsigned int back_tiled; 251718dceddSDavid Howells unsigned int depth_tiled; 252718dceddSDavid Howells unsigned int rotated_tiled; 253718dceddSDavid Howells unsigned int rotated2_tiled; 254718dceddSDavid Howells 255718dceddSDavid Howells int pipeA_x; 256718dceddSDavid Howells int pipeA_y; 257718dceddSDavid Howells int pipeA_w; 258718dceddSDavid Howells int pipeA_h; 259718dceddSDavid Howells int pipeB_x; 260718dceddSDavid Howells int pipeB_y; 261718dceddSDavid Howells int pipeB_w; 262718dceddSDavid Howells int pipeB_h; 263718dceddSDavid Howells 264718dceddSDavid Howells /* fill out some space for old userspace triple buffer */ 265718dceddSDavid Howells drm_handle_t unused_handle; 266718dceddSDavid Howells __u32 unused1, unused2, unused3; 267718dceddSDavid Howells 268718dceddSDavid Howells /* buffer object handles for static buffers. May change 269718dceddSDavid Howells * over the lifetime of the client. 270718dceddSDavid Howells */ 271718dceddSDavid Howells __u32 front_bo_handle; 272718dceddSDavid Howells __u32 back_bo_handle; 273718dceddSDavid Howells __u32 unused_bo_handle; 274718dceddSDavid Howells __u32 depth_bo_handle; 275718dceddSDavid Howells 276718dceddSDavid Howells } drm_i915_sarea_t; 277718dceddSDavid Howells 278718dceddSDavid Howells /* due to userspace building against these headers we need some compat here */ 279718dceddSDavid Howells #define planeA_x pipeA_x 280718dceddSDavid Howells #define planeA_y pipeA_y 281718dceddSDavid Howells #define planeA_w pipeA_w 282718dceddSDavid Howells #define planeA_h pipeA_h 283718dceddSDavid Howells #define planeB_x pipeB_x 284718dceddSDavid Howells #define planeB_y pipeB_y 285718dceddSDavid Howells #define planeB_w pipeB_w 286718dceddSDavid Howells #define planeB_h pipeB_h 287718dceddSDavid Howells 288718dceddSDavid Howells /* Flags for perf_boxes 289718dceddSDavid Howells */ 290718dceddSDavid Howells #define I915_BOX_RING_EMPTY 0x1 291718dceddSDavid Howells #define I915_BOX_FLIP 0x2 292718dceddSDavid Howells #define I915_BOX_WAIT 0x4 293718dceddSDavid Howells #define I915_BOX_TEXTURE_LOAD 0x8 294718dceddSDavid Howells #define I915_BOX_LOST_CONTEXT 0x10 295718dceddSDavid Howells 29621631f10SDamien Lespiau /* 29721631f10SDamien Lespiau * i915 specific ioctls. 29821631f10SDamien Lespiau * 29921631f10SDamien Lespiau * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie 30021631f10SDamien Lespiau * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset 30121631f10SDamien Lespiau * against DRM_COMMAND_BASE and should be between [0x0, 0x60). 302718dceddSDavid Howells */ 303718dceddSDavid Howells #define DRM_I915_INIT 0x00 304718dceddSDavid Howells #define DRM_I915_FLUSH 0x01 305718dceddSDavid Howells #define DRM_I915_FLIP 0x02 306718dceddSDavid Howells #define DRM_I915_BATCHBUFFER 0x03 307718dceddSDavid Howells #define DRM_I915_IRQ_EMIT 0x04 308718dceddSDavid Howells #define DRM_I915_IRQ_WAIT 0x05 309718dceddSDavid Howells #define DRM_I915_GETPARAM 0x06 310718dceddSDavid Howells #define DRM_I915_SETPARAM 0x07 311718dceddSDavid Howells #define DRM_I915_ALLOC 0x08 312718dceddSDavid Howells #define DRM_I915_FREE 0x09 313718dceddSDavid Howells #define DRM_I915_INIT_HEAP 0x0a 314718dceddSDavid Howells #define DRM_I915_CMDBUFFER 0x0b 315718dceddSDavid Howells #define DRM_I915_DESTROY_HEAP 0x0c 316718dceddSDavid Howells #define DRM_I915_SET_VBLANK_PIPE 0x0d 317718dceddSDavid Howells #define DRM_I915_GET_VBLANK_PIPE 0x0e 318718dceddSDavid Howells #define DRM_I915_VBLANK_SWAP 0x0f 319718dceddSDavid Howells #define DRM_I915_HWS_ADDR 0x11 320718dceddSDavid Howells #define DRM_I915_GEM_INIT 0x13 321718dceddSDavid Howells #define DRM_I915_GEM_EXECBUFFER 0x14 322718dceddSDavid Howells #define DRM_I915_GEM_PIN 0x15 323718dceddSDavid Howells #define DRM_I915_GEM_UNPIN 0x16 324718dceddSDavid Howells #define DRM_I915_GEM_BUSY 0x17 325718dceddSDavid Howells #define DRM_I915_GEM_THROTTLE 0x18 326718dceddSDavid Howells #define DRM_I915_GEM_ENTERVT 0x19 327718dceddSDavid Howells #define DRM_I915_GEM_LEAVEVT 0x1a 328718dceddSDavid Howells #define DRM_I915_GEM_CREATE 0x1b 329718dceddSDavid Howells #define DRM_I915_GEM_PREAD 0x1c 330718dceddSDavid Howells #define DRM_I915_GEM_PWRITE 0x1d 331718dceddSDavid Howells #define DRM_I915_GEM_MMAP 0x1e 332718dceddSDavid Howells #define DRM_I915_GEM_SET_DOMAIN 0x1f 333718dceddSDavid Howells #define DRM_I915_GEM_SW_FINISH 0x20 334718dceddSDavid Howells #define DRM_I915_GEM_SET_TILING 0x21 335718dceddSDavid Howells #define DRM_I915_GEM_GET_TILING 0x22 336718dceddSDavid Howells #define DRM_I915_GEM_GET_APERTURE 0x23 337718dceddSDavid Howells #define DRM_I915_GEM_MMAP_GTT 0x24 338718dceddSDavid Howells #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 339718dceddSDavid Howells #define DRM_I915_GEM_MADVISE 0x26 340718dceddSDavid Howells #define DRM_I915_OVERLAY_PUT_IMAGE 0x27 341718dceddSDavid Howells #define DRM_I915_OVERLAY_ATTRS 0x28 342718dceddSDavid Howells #define DRM_I915_GEM_EXECBUFFER2 0x29 343fec0445cSChris Wilson #define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2 344718dceddSDavid Howells #define DRM_I915_GET_SPRITE_COLORKEY 0x2a 345718dceddSDavid Howells #define DRM_I915_SET_SPRITE_COLORKEY 0x2b 346718dceddSDavid Howells #define DRM_I915_GEM_WAIT 0x2c 347718dceddSDavid Howells #define DRM_I915_GEM_CONTEXT_CREATE 0x2d 348718dceddSDavid Howells #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e 349718dceddSDavid Howells #define DRM_I915_GEM_SET_CACHING 0x2f 350718dceddSDavid Howells #define DRM_I915_GEM_GET_CACHING 0x30 351718dceddSDavid Howells #define DRM_I915_REG_READ 0x31 352b6359918SMika Kuoppala #define DRM_I915_GET_RESET_STATS 0x32 3535cc9ed4bSChris Wilson #define DRM_I915_GEM_USERPTR 0x33 354c9dc0f35SChris Wilson #define DRM_I915_GEM_CONTEXT_GETPARAM 0x34 355c9dc0f35SChris Wilson #define DRM_I915_GEM_CONTEXT_SETPARAM 0x35 356eec688e1SRobert Bragg #define DRM_I915_PERF_OPEN 0x36 357f89823c2SLionel Landwerlin #define DRM_I915_PERF_ADD_CONFIG 0x37 358f89823c2SLionel Landwerlin #define DRM_I915_PERF_REMOVE_CONFIG 0x38 359a446ae2cSLionel Landwerlin #define DRM_I915_QUERY 0x39 3607f3f317aSChris Wilson #define DRM_I915_GEM_VM_CREATE 0x3a 3617f3f317aSChris Wilson #define DRM_I915_GEM_VM_DESTROY 0x3b 362be03564bSChris Wilson /* Must be kept compact -- no holes */ 363718dceddSDavid Howells 364718dceddSDavid Howells #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 365718dceddSDavid Howells #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 366718dceddSDavid Howells #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) 367718dceddSDavid Howells #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 368718dceddSDavid Howells #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 369718dceddSDavid Howells #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 370718dceddSDavid Howells #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 371718dceddSDavid Howells #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 372718dceddSDavid Howells #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 373718dceddSDavid Howells #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 374718dceddSDavid Howells #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 375718dceddSDavid Howells #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 376718dceddSDavid Howells #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 377718dceddSDavid Howells #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 378718dceddSDavid Howells #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 379718dceddSDavid Howells #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 380718dceddSDavid Howells #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) 381718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 382718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 383718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 384fec0445cSChris Wilson #define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2) 385718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 386718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 387718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 388718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) 389718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) 390718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 391718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 392718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 393718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 394718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 395718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 396718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 397718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 398718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 399718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 400718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 401718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 402718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 403718dceddSDavid Howells #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 404718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 405718dceddSDavid Howells #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) 406718dceddSDavid Howells #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 407718dceddSDavid Howells #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 4082c60fae1STommi Rantala #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 409718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) 410718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) 411b9171541SChris Wilson #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext) 412718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) 413718dceddSDavid Howells #define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) 414b6359918SMika Kuoppala #define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats) 4155cc9ed4bSChris Wilson #define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr) 416c9dc0f35SChris Wilson #define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param) 417c9dc0f35SChris Wilson #define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param) 418eec688e1SRobert Bragg #define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param) 419f89823c2SLionel Landwerlin #define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config) 420f89823c2SLionel Landwerlin #define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64) 421a446ae2cSLionel Landwerlin #define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query) 4227f3f317aSChris Wilson #define DRM_IOCTL_I915_GEM_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control) 4237f3f317aSChris Wilson #define DRM_IOCTL_I915_GEM_VM_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control) 424718dceddSDavid Howells 425718dceddSDavid Howells /* Allow drivers to submit batchbuffers directly to hardware, relying 426718dceddSDavid Howells * on the security mechanisms provided by hardware. 427718dceddSDavid Howells */ 428718dceddSDavid Howells typedef struct drm_i915_batchbuffer { 429718dceddSDavid Howells int start; /* agp offset */ 430718dceddSDavid Howells int used; /* nr bytes in use */ 431718dceddSDavid Howells int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 432718dceddSDavid Howells int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 433718dceddSDavid Howells int num_cliprects; /* mulitpass with multiple cliprects? */ 434718dceddSDavid Howells struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 435718dceddSDavid Howells } drm_i915_batchbuffer_t; 436718dceddSDavid Howells 437718dceddSDavid Howells /* As above, but pass a pointer to userspace buffer which can be 438718dceddSDavid Howells * validated by the kernel prior to sending to hardware. 439718dceddSDavid Howells */ 440718dceddSDavid Howells typedef struct _drm_i915_cmdbuffer { 441718dceddSDavid Howells char __user *buf; /* pointer to userspace command buffer */ 442718dceddSDavid Howells int sz; /* nr bytes in buf */ 443718dceddSDavid Howells int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 444718dceddSDavid Howells int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 445718dceddSDavid Howells int num_cliprects; /* mulitpass with multiple cliprects? */ 446718dceddSDavid Howells struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 447718dceddSDavid Howells } drm_i915_cmdbuffer_t; 448718dceddSDavid Howells 449718dceddSDavid Howells /* Userspace can request & wait on irq's: 450718dceddSDavid Howells */ 451718dceddSDavid Howells typedef struct drm_i915_irq_emit { 452718dceddSDavid Howells int __user *irq_seq; 453718dceddSDavid Howells } drm_i915_irq_emit_t; 454718dceddSDavid Howells 455718dceddSDavid Howells typedef struct drm_i915_irq_wait { 456718dceddSDavid Howells int irq_seq; 457718dceddSDavid Howells } drm_i915_irq_wait_t; 458718dceddSDavid Howells 4594bdafb9dSChris Wilson /* 4604bdafb9dSChris Wilson * Different modes of per-process Graphics Translation Table, 4614bdafb9dSChris Wilson * see I915_PARAM_HAS_ALIASING_PPGTT 4624bdafb9dSChris Wilson */ 4634bdafb9dSChris Wilson #define I915_GEM_PPGTT_NONE 0 4644bdafb9dSChris Wilson #define I915_GEM_PPGTT_ALIASING 1 4654bdafb9dSChris Wilson #define I915_GEM_PPGTT_FULL 2 4664bdafb9dSChris Wilson 467718dceddSDavid Howells /* Ioctl to query kernel params: 468718dceddSDavid Howells */ 469718dceddSDavid Howells #define I915_PARAM_IRQ_ACTIVE 1 470718dceddSDavid Howells #define I915_PARAM_ALLOW_BATCHBUFFER 2 471718dceddSDavid Howells #define I915_PARAM_LAST_DISPATCH 3 472718dceddSDavid Howells #define I915_PARAM_CHIPSET_ID 4 473718dceddSDavid Howells #define I915_PARAM_HAS_GEM 5 474718dceddSDavid Howells #define I915_PARAM_NUM_FENCES_AVAIL 6 475718dceddSDavid Howells #define I915_PARAM_HAS_OVERLAY 7 476718dceddSDavid Howells #define I915_PARAM_HAS_PAGEFLIPPING 8 477718dceddSDavid Howells #define I915_PARAM_HAS_EXECBUF2 9 478718dceddSDavid Howells #define I915_PARAM_HAS_BSD 10 479718dceddSDavid Howells #define I915_PARAM_HAS_BLT 11 480718dceddSDavid Howells #define I915_PARAM_HAS_RELAXED_FENCING 12 481718dceddSDavid Howells #define I915_PARAM_HAS_COHERENT_RINGS 13 482718dceddSDavid Howells #define I915_PARAM_HAS_EXEC_CONSTANTS 14 483718dceddSDavid Howells #define I915_PARAM_HAS_RELAXED_DELTA 15 484718dceddSDavid Howells #define I915_PARAM_HAS_GEN7_SOL_RESET 16 485718dceddSDavid Howells #define I915_PARAM_HAS_LLC 17 486718dceddSDavid Howells #define I915_PARAM_HAS_ALIASING_PPGTT 18 487718dceddSDavid Howells #define I915_PARAM_HAS_WAIT_TIMEOUT 19 488718dceddSDavid Howells #define I915_PARAM_HAS_SEMAPHORES 20 489718dceddSDavid Howells #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 490a1f2cc73SXiang, Haihao #define I915_PARAM_HAS_VEBOX 22 491c2fb7916SDaniel Vetter #define I915_PARAM_HAS_SECURE_BATCHES 23 492b45305fcSDaniel Vetter #define I915_PARAM_HAS_PINNED_BATCHES 24 493ed5982e6SDaniel Vetter #define I915_PARAM_HAS_EXEC_NO_RELOC 25 494eef90ccbSChris Wilson #define I915_PARAM_HAS_EXEC_HANDLE_LUT 26 495651d794fSChris Wilson #define I915_PARAM_HAS_WT 27 496d728c8efSBrad Volkin #define I915_PARAM_CMD_PARSER_VERSION 28 4976a2c4232SChris Wilson #define I915_PARAM_HAS_COHERENT_PHYS_GTT 29 4981816f923SAkash Goel #define I915_PARAM_MMAP_VERSION 30 49908e16dc8SZhipeng Gong #define I915_PARAM_HAS_BSD2 31 50027cd4461SNeil Roberts #define I915_PARAM_REVISION 32 501a1559ffeSJeff McGee #define I915_PARAM_SUBSLICE_TOTAL 33 502a1559ffeSJeff McGee #define I915_PARAM_EU_TOTAL 34 50349e4d842SChris Wilson #define I915_PARAM_HAS_GPU_RESET 35 504a9ed33caSAbdiel Janulgue #define I915_PARAM_HAS_RESOURCE_STREAMER 36 505506a8e87SChris Wilson #define I915_PARAM_HAS_EXEC_SOFTPIN 37 50637f501afSarun.siluvery@linux.intel.com #define I915_PARAM_HAS_POOLED_EU 38 50737f501afSarun.siluvery@linux.intel.com #define I915_PARAM_MIN_EU_IN_POOL 39 5084cc69075SChris Wilson #define I915_PARAM_MMAP_GTT_VERSION 40 509718dceddSDavid Howells 510bf64e0b0SChris Wilson /* 511bf64e0b0SChris Wilson * Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution 5120de9136dSChris Wilson * priorities and the driver will attempt to execute batches in priority order. 513bf64e0b0SChris Wilson * The param returns a capability bitmask, nonzero implies that the scheduler 514bf64e0b0SChris Wilson * is enabled, with different features present according to the mask. 515ac14fbd4SChris Wilson * 516ac14fbd4SChris Wilson * The initial priority for each batch is supplied by the context and is 517ac14fbd4SChris Wilson * controlled via I915_CONTEXT_PARAM_PRIORITY. 5180de9136dSChris Wilson */ 5190de9136dSChris Wilson #define I915_PARAM_HAS_SCHEDULER 41 520bf64e0b0SChris Wilson #define I915_SCHEDULER_CAP_ENABLED (1ul << 0) 521bf64e0b0SChris Wilson #define I915_SCHEDULER_CAP_PRIORITY (1ul << 1) 522bf64e0b0SChris Wilson #define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2) 523e8861964SChris Wilson #define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3) 524bf64e0b0SChris Wilson 5255464cd65SAnusha Srivatsa #define I915_PARAM_HUC_STATUS 42 5260de9136dSChris Wilson 52777ae9957SChris Wilson /* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of 52877ae9957SChris Wilson * synchronisation with implicit fencing on individual objects. 52977ae9957SChris Wilson * See EXEC_OBJECT_ASYNC. 53077ae9957SChris Wilson */ 53177ae9957SChris Wilson #define I915_PARAM_HAS_EXEC_ASYNC 43 53277ae9957SChris Wilson 533fec0445cSChris Wilson /* Query whether DRM_I915_GEM_EXECBUFFER2 supports explicit fence support - 534fec0445cSChris Wilson * both being able to pass in a sync_file fd to wait upon before executing, 535fec0445cSChris Wilson * and being able to return a new sync_file fd that is signaled when the 536fec0445cSChris Wilson * current request is complete. See I915_EXEC_FENCE_IN and I915_EXEC_FENCE_OUT. 537fec0445cSChris Wilson */ 538fec0445cSChris Wilson #define I915_PARAM_HAS_EXEC_FENCE 44 539fec0445cSChris Wilson 540b0fd47adSChris Wilson /* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to capture 541b0fd47adSChris Wilson * user specified bufffers for post-mortem debugging of GPU hangs. See 542b0fd47adSChris Wilson * EXEC_OBJECT_CAPTURE. 543b0fd47adSChris Wilson */ 544b0fd47adSChris Wilson #define I915_PARAM_HAS_EXEC_CAPTURE 45 545b0fd47adSChris Wilson 5467fed555cSRobert Bragg #define I915_PARAM_SLICE_MASK 46 5477fed555cSRobert Bragg 548f5320233SRobert Bragg /* Assuming it's uniform for each slice, this queries the mask of subslices 549f5320233SRobert Bragg * per-slice for this system. 550f5320233SRobert Bragg */ 551f5320233SRobert Bragg #define I915_PARAM_SUBSLICE_MASK 47 552f5320233SRobert Bragg 5531a71cf2fSChris Wilson /* 5541a71cf2fSChris Wilson * Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying the batch buffer 5551a71cf2fSChris Wilson * as the first execobject as opposed to the last. See I915_EXEC_BATCH_FIRST. 5561a71cf2fSChris Wilson */ 5571a71cf2fSChris Wilson #define I915_PARAM_HAS_EXEC_BATCH_FIRST 48 5581a71cf2fSChris Wilson 559cf6e7bacSJason Ekstrand /* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of 560cf6e7bacSJason Ekstrand * drm_i915_gem_exec_fence structures. See I915_EXEC_FENCE_ARRAY. 561cf6e7bacSJason Ekstrand */ 562cf6e7bacSJason Ekstrand #define I915_PARAM_HAS_EXEC_FENCE_ARRAY 49 563cf6e7bacSJason Ekstrand 564d2b4b979SChris Wilson /* 565d2b4b979SChris Wilson * Query whether every context (both per-file default and user created) is 566d2b4b979SChris Wilson * isolated (insofar as HW supports). If this parameter is not true, then 567d2b4b979SChris Wilson * freshly created contexts may inherit values from an existing context, 568d2b4b979SChris Wilson * rather than default HW values. If true, it also ensures (insofar as HW 569d2b4b979SChris Wilson * supports) that all state set by this context will not leak to any other 570d2b4b979SChris Wilson * context. 571d2b4b979SChris Wilson * 572d2b4b979SChris Wilson * As not every engine across every gen support contexts, the returned 573d2b4b979SChris Wilson * value reports the support of context isolation for individual engines by 574d2b4b979SChris Wilson * returning a bitmask of each engine class set to true if that class supports 575d2b4b979SChris Wilson * isolation. 576d2b4b979SChris Wilson */ 577d2b4b979SChris Wilson #define I915_PARAM_HAS_CONTEXT_ISOLATION 50 578d2b4b979SChris Wilson 579dab91783SLionel Landwerlin /* Frequency of the command streamer timestamps given by the *_TIMESTAMP 580dab91783SLionel Landwerlin * registers. This used to be fixed per platform but from CNL onwards, this 581dab91783SLionel Landwerlin * might vary depending on the parts. 582dab91783SLionel Landwerlin */ 583dab91783SLionel Landwerlin #define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51 584dab91783SLionel Landwerlin 585900ccf30SChris Wilson /* 586900ccf30SChris Wilson * Once upon a time we supposed that writes through the GGTT would be 587900ccf30SChris Wilson * immediately in physical memory (once flushed out of the CPU path). However, 588900ccf30SChris Wilson * on a few different processors and chipsets, this is not necessarily the case 589900ccf30SChris Wilson * as the writes appear to be buffered internally. Thus a read of the backing 590900ccf30SChris Wilson * storage (physical memory) via a different path (with different physical tags 591900ccf30SChris Wilson * to the indirect write via the GGTT) will see stale values from before 592900ccf30SChris Wilson * the GGTT write. Inside the kernel, we can for the most part keep track of 593900ccf30SChris Wilson * the different read/write domains in use (e.g. set-domain), but the assumption 594900ccf30SChris Wilson * of coherency is baked into the ABI, hence reporting its true state in this 595900ccf30SChris Wilson * parameter. 596900ccf30SChris Wilson * 597900ccf30SChris Wilson * Reports true when writes via mmap_gtt are immediately visible following an 598900ccf30SChris Wilson * lfence to flush the WCB. 599900ccf30SChris Wilson * 600900ccf30SChris Wilson * Reports false when writes via mmap_gtt are indeterminately delayed in an in 601900ccf30SChris Wilson * internal buffer and are _not_ immediately visible to third parties accessing 602900ccf30SChris Wilson * directly via mmap_cpu/mmap_wc. Use of mmap_gtt as part of an IPC 603900ccf30SChris Wilson * communications channel when reporting false is strongly disadvised. 604900ccf30SChris Wilson */ 605900ccf30SChris Wilson #define I915_PARAM_MMAP_GTT_COHERENT 52 606900ccf30SChris Wilson 607be03564bSChris Wilson /* Must be kept compact -- no holes and well documented */ 608be03564bSChris Wilson 609718dceddSDavid Howells typedef struct drm_i915_getparam { 61016f7249dSArtem Savkov __s32 param; 611346add78SDaniel Vetter /* 612346add78SDaniel Vetter * WARNING: Using pointers instead of fixed-size u64 means we need to write 613346add78SDaniel Vetter * compat32 code. Don't repeat this mistake. 614346add78SDaniel Vetter */ 615718dceddSDavid Howells int __user *value; 616718dceddSDavid Howells } drm_i915_getparam_t; 617718dceddSDavid Howells 618718dceddSDavid Howells /* Ioctl to set kernel params: 619718dceddSDavid Howells */ 620718dceddSDavid Howells #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 621718dceddSDavid Howells #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 622718dceddSDavid Howells #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 623718dceddSDavid Howells #define I915_SETPARAM_NUM_USED_FENCES 4 624be03564bSChris Wilson /* Must be kept compact -- no holes */ 625718dceddSDavid Howells 626718dceddSDavid Howells typedef struct drm_i915_setparam { 627718dceddSDavid Howells int param; 628718dceddSDavid Howells int value; 629718dceddSDavid Howells } drm_i915_setparam_t; 630718dceddSDavid Howells 631718dceddSDavid Howells /* A memory manager for regions of shared memory: 632718dceddSDavid Howells */ 633718dceddSDavid Howells #define I915_MEM_REGION_AGP 1 634718dceddSDavid Howells 635718dceddSDavid Howells typedef struct drm_i915_mem_alloc { 636718dceddSDavid Howells int region; 637718dceddSDavid Howells int alignment; 638718dceddSDavid Howells int size; 639718dceddSDavid Howells int __user *region_offset; /* offset from start of fb or agp */ 640718dceddSDavid Howells } drm_i915_mem_alloc_t; 641718dceddSDavid Howells 642718dceddSDavid Howells typedef struct drm_i915_mem_free { 643718dceddSDavid Howells int region; 644718dceddSDavid Howells int region_offset; 645718dceddSDavid Howells } drm_i915_mem_free_t; 646718dceddSDavid Howells 647718dceddSDavid Howells typedef struct drm_i915_mem_init_heap { 648718dceddSDavid Howells int region; 649718dceddSDavid Howells int size; 650718dceddSDavid Howells int start; 651718dceddSDavid Howells } drm_i915_mem_init_heap_t; 652718dceddSDavid Howells 653718dceddSDavid Howells /* Allow memory manager to be torn down and re-initialized (eg on 654718dceddSDavid Howells * rotate): 655718dceddSDavid Howells */ 656718dceddSDavid Howells typedef struct drm_i915_mem_destroy_heap { 657718dceddSDavid Howells int region; 658718dceddSDavid Howells } drm_i915_mem_destroy_heap_t; 659718dceddSDavid Howells 660718dceddSDavid Howells /* Allow X server to configure which pipes to monitor for vblank signals 661718dceddSDavid Howells */ 662718dceddSDavid Howells #define DRM_I915_VBLANK_PIPE_A 1 663718dceddSDavid Howells #define DRM_I915_VBLANK_PIPE_B 2 664718dceddSDavid Howells 665718dceddSDavid Howells typedef struct drm_i915_vblank_pipe { 666718dceddSDavid Howells int pipe; 667718dceddSDavid Howells } drm_i915_vblank_pipe_t; 668718dceddSDavid Howells 669718dceddSDavid Howells /* Schedule buffer swap at given vertical blank: 670718dceddSDavid Howells */ 671718dceddSDavid Howells typedef struct drm_i915_vblank_swap { 672718dceddSDavid Howells drm_drawable_t drawable; 673718dceddSDavid Howells enum drm_vblank_seq_type seqtype; 674718dceddSDavid Howells unsigned int sequence; 675718dceddSDavid Howells } drm_i915_vblank_swap_t; 676718dceddSDavid Howells 677718dceddSDavid Howells typedef struct drm_i915_hws_addr { 678718dceddSDavid Howells __u64 addr; 679718dceddSDavid Howells } drm_i915_hws_addr_t; 680718dceddSDavid Howells 681718dceddSDavid Howells struct drm_i915_gem_init { 682718dceddSDavid Howells /** 683718dceddSDavid Howells * Beginning offset in the GTT to be managed by the DRM memory 684718dceddSDavid Howells * manager. 685718dceddSDavid Howells */ 686718dceddSDavid Howells __u64 gtt_start; 687718dceddSDavid Howells /** 688718dceddSDavid Howells * Ending offset in the GTT to be managed by the DRM memory 689718dceddSDavid Howells * manager. 690718dceddSDavid Howells */ 691718dceddSDavid Howells __u64 gtt_end; 692718dceddSDavid Howells }; 693718dceddSDavid Howells 694718dceddSDavid Howells struct drm_i915_gem_create { 695718dceddSDavid Howells /** 696718dceddSDavid Howells * Requested size for the object. 697718dceddSDavid Howells * 698718dceddSDavid Howells * The (page-aligned) allocated size for the object will be returned. 699718dceddSDavid Howells */ 700718dceddSDavid Howells __u64 size; 701718dceddSDavid Howells /** 702718dceddSDavid Howells * Returned handle for the object. 703718dceddSDavid Howells * 704718dceddSDavid Howells * Object handles are nonzero. 705718dceddSDavid Howells */ 706718dceddSDavid Howells __u32 handle; 707718dceddSDavid Howells __u32 pad; 708718dceddSDavid Howells }; 709718dceddSDavid Howells 710718dceddSDavid Howells struct drm_i915_gem_pread { 711718dceddSDavid Howells /** Handle for the object being read. */ 712718dceddSDavid Howells __u32 handle; 713718dceddSDavid Howells __u32 pad; 714718dceddSDavid Howells /** Offset into the object to read from */ 715718dceddSDavid Howells __u64 offset; 716718dceddSDavid Howells /** Length of data to read */ 717718dceddSDavid Howells __u64 size; 718718dceddSDavid Howells /** 719718dceddSDavid Howells * Pointer to write the data into. 720718dceddSDavid Howells * 721718dceddSDavid Howells * This is a fixed-size type for 32/64 compatibility. 722718dceddSDavid Howells */ 723718dceddSDavid Howells __u64 data_ptr; 724718dceddSDavid Howells }; 725718dceddSDavid Howells 726718dceddSDavid Howells struct drm_i915_gem_pwrite { 727718dceddSDavid Howells /** Handle for the object being written to. */ 728718dceddSDavid Howells __u32 handle; 729718dceddSDavid Howells __u32 pad; 730718dceddSDavid Howells /** Offset into the object to write to */ 731718dceddSDavid Howells __u64 offset; 732718dceddSDavid Howells /** Length of data to write */ 733718dceddSDavid Howells __u64 size; 734718dceddSDavid Howells /** 735718dceddSDavid Howells * Pointer to read the data from. 736718dceddSDavid Howells * 737718dceddSDavid Howells * This is a fixed-size type for 32/64 compatibility. 738718dceddSDavid Howells */ 739718dceddSDavid Howells __u64 data_ptr; 740718dceddSDavid Howells }; 741718dceddSDavid Howells 742718dceddSDavid Howells struct drm_i915_gem_mmap { 743718dceddSDavid Howells /** Handle for the object being mapped. */ 744718dceddSDavid Howells __u32 handle; 745718dceddSDavid Howells __u32 pad; 746718dceddSDavid Howells /** Offset in the object to map. */ 747718dceddSDavid Howells __u64 offset; 748718dceddSDavid Howells /** 749718dceddSDavid Howells * Length of data to map. 750718dceddSDavid Howells * 751718dceddSDavid Howells * The value will be page-aligned. 752718dceddSDavid Howells */ 753718dceddSDavid Howells __u64 size; 754718dceddSDavid Howells /** 755718dceddSDavid Howells * Returned pointer the data was mapped at. 756718dceddSDavid Howells * 757718dceddSDavid Howells * This is a fixed-size type for 32/64 compatibility. 758718dceddSDavid Howells */ 759718dceddSDavid Howells __u64 addr_ptr; 7601816f923SAkash Goel 7611816f923SAkash Goel /** 7621816f923SAkash Goel * Flags for extended behaviour. 7631816f923SAkash Goel * 7641816f923SAkash Goel * Added in version 2. 7651816f923SAkash Goel */ 7661816f923SAkash Goel __u64 flags; 7671816f923SAkash Goel #define I915_MMAP_WC 0x1 768718dceddSDavid Howells }; 769718dceddSDavid Howells 770718dceddSDavid Howells struct drm_i915_gem_mmap_gtt { 771718dceddSDavid Howells /** Handle for the object being mapped. */ 772718dceddSDavid Howells __u32 handle; 773718dceddSDavid Howells __u32 pad; 774718dceddSDavid Howells /** 775718dceddSDavid Howells * Fake offset to use for subsequent mmap call 776718dceddSDavid Howells * 777718dceddSDavid Howells * This is a fixed-size type for 32/64 compatibility. 778718dceddSDavid Howells */ 779718dceddSDavid Howells __u64 offset; 780718dceddSDavid Howells }; 781718dceddSDavid Howells 782718dceddSDavid Howells struct drm_i915_gem_set_domain { 783718dceddSDavid Howells /** Handle for the object */ 784718dceddSDavid Howells __u32 handle; 785718dceddSDavid Howells 786718dceddSDavid Howells /** New read domains */ 787718dceddSDavid Howells __u32 read_domains; 788718dceddSDavid Howells 789718dceddSDavid Howells /** New write domain */ 790718dceddSDavid Howells __u32 write_domain; 791718dceddSDavid Howells }; 792718dceddSDavid Howells 793718dceddSDavid Howells struct drm_i915_gem_sw_finish { 794718dceddSDavid Howells /** Handle for the object */ 795718dceddSDavid Howells __u32 handle; 796718dceddSDavid Howells }; 797718dceddSDavid Howells 798718dceddSDavid Howells struct drm_i915_gem_relocation_entry { 799718dceddSDavid Howells /** 800718dceddSDavid Howells * Handle of the buffer being pointed to by this relocation entry. 801718dceddSDavid Howells * 802718dceddSDavid Howells * It's appealing to make this be an index into the mm_validate_entry 803718dceddSDavid Howells * list to refer to the buffer, but this allows the driver to create 804718dceddSDavid Howells * a relocation list for state buffers and not re-write it per 805718dceddSDavid Howells * exec using the buffer. 806718dceddSDavid Howells */ 807718dceddSDavid Howells __u32 target_handle; 808718dceddSDavid Howells 809718dceddSDavid Howells /** 810718dceddSDavid Howells * Value to be added to the offset of the target buffer to make up 811718dceddSDavid Howells * the relocation entry. 812718dceddSDavid Howells */ 813718dceddSDavid Howells __u32 delta; 814718dceddSDavid Howells 815718dceddSDavid Howells /** Offset in the buffer the relocation entry will be written into */ 816718dceddSDavid Howells __u64 offset; 817718dceddSDavid Howells 818718dceddSDavid Howells /** 819718dceddSDavid Howells * Offset value of the target buffer that the relocation entry was last 820718dceddSDavid Howells * written as. 821718dceddSDavid Howells * 822718dceddSDavid Howells * If the buffer has the same offset as last time, we can skip syncing 823718dceddSDavid Howells * and writing the relocation. This value is written back out by 824718dceddSDavid Howells * the execbuffer ioctl when the relocation is written. 825718dceddSDavid Howells */ 826718dceddSDavid Howells __u64 presumed_offset; 827718dceddSDavid Howells 828718dceddSDavid Howells /** 829718dceddSDavid Howells * Target memory domains read by this operation. 830718dceddSDavid Howells */ 831718dceddSDavid Howells __u32 read_domains; 832718dceddSDavid Howells 833718dceddSDavid Howells /** 834718dceddSDavid Howells * Target memory domains written by this operation. 835718dceddSDavid Howells * 836718dceddSDavid Howells * Note that only one domain may be written by the whole 837718dceddSDavid Howells * execbuffer operation, so that where there are conflicts, 838718dceddSDavid Howells * the application will get -EINVAL back. 839718dceddSDavid Howells */ 840718dceddSDavid Howells __u32 write_domain; 841718dceddSDavid Howells }; 842718dceddSDavid Howells 843718dceddSDavid Howells /** @{ 844718dceddSDavid Howells * Intel memory domains 845718dceddSDavid Howells * 846718dceddSDavid Howells * Most of these just align with the various caches in 847718dceddSDavid Howells * the system and are used to flush and invalidate as 848718dceddSDavid Howells * objects end up cached in different domains. 849718dceddSDavid Howells */ 850718dceddSDavid Howells /** CPU cache */ 851718dceddSDavid Howells #define I915_GEM_DOMAIN_CPU 0x00000001 852718dceddSDavid Howells /** Render cache, used by 2D and 3D drawing */ 853718dceddSDavid Howells #define I915_GEM_DOMAIN_RENDER 0x00000002 854718dceddSDavid Howells /** Sampler cache, used by texture engine */ 855718dceddSDavid Howells #define I915_GEM_DOMAIN_SAMPLER 0x00000004 856718dceddSDavid Howells /** Command queue, used to load batch buffers */ 857718dceddSDavid Howells #define I915_GEM_DOMAIN_COMMAND 0x00000008 858718dceddSDavid Howells /** Instruction cache, used by shader programs */ 859718dceddSDavid Howells #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 860718dceddSDavid Howells /** Vertex address cache */ 861718dceddSDavid Howells #define I915_GEM_DOMAIN_VERTEX 0x00000020 862718dceddSDavid Howells /** GTT domain - aperture and scanout */ 863718dceddSDavid Howells #define I915_GEM_DOMAIN_GTT 0x00000040 864e22d8e3cSChris Wilson /** WC domain - uncached access */ 865e22d8e3cSChris Wilson #define I915_GEM_DOMAIN_WC 0x00000080 866718dceddSDavid Howells /** @} */ 867718dceddSDavid Howells 868718dceddSDavid Howells struct drm_i915_gem_exec_object { 869718dceddSDavid Howells /** 870718dceddSDavid Howells * User's handle for a buffer to be bound into the GTT for this 871718dceddSDavid Howells * operation. 872718dceddSDavid Howells */ 873718dceddSDavid Howells __u32 handle; 874718dceddSDavid Howells 875718dceddSDavid Howells /** Number of relocations to be performed on this buffer */ 876718dceddSDavid Howells __u32 relocation_count; 877718dceddSDavid Howells /** 878718dceddSDavid Howells * Pointer to array of struct drm_i915_gem_relocation_entry containing 879718dceddSDavid Howells * the relocations to be performed in this buffer. 880718dceddSDavid Howells */ 881718dceddSDavid Howells __u64 relocs_ptr; 882718dceddSDavid Howells 883718dceddSDavid Howells /** Required alignment in graphics aperture */ 884718dceddSDavid Howells __u64 alignment; 885718dceddSDavid Howells 886718dceddSDavid Howells /** 887718dceddSDavid Howells * Returned value of the updated offset of the object, for future 888718dceddSDavid Howells * presumed_offset writes. 889718dceddSDavid Howells */ 890718dceddSDavid Howells __u64 offset; 891718dceddSDavid Howells }; 892718dceddSDavid Howells 893718dceddSDavid Howells struct drm_i915_gem_execbuffer { 894718dceddSDavid Howells /** 895718dceddSDavid Howells * List of buffers to be validated with their relocations to be 896718dceddSDavid Howells * performend on them. 897718dceddSDavid Howells * 898718dceddSDavid Howells * This is a pointer to an array of struct drm_i915_gem_validate_entry. 899718dceddSDavid Howells * 900718dceddSDavid Howells * These buffers must be listed in an order such that all relocations 901718dceddSDavid Howells * a buffer is performing refer to buffers that have already appeared 902718dceddSDavid Howells * in the validate list. 903718dceddSDavid Howells */ 904718dceddSDavid Howells __u64 buffers_ptr; 905718dceddSDavid Howells __u32 buffer_count; 906718dceddSDavid Howells 907718dceddSDavid Howells /** Offset in the batchbuffer to start execution from. */ 908718dceddSDavid Howells __u32 batch_start_offset; 909718dceddSDavid Howells /** Bytes used in batchbuffer from batch_start_offset */ 910718dceddSDavid Howells __u32 batch_len; 911718dceddSDavid Howells __u32 DR1; 912718dceddSDavid Howells __u32 DR4; 913718dceddSDavid Howells __u32 num_cliprects; 914718dceddSDavid Howells /** This is a struct drm_clip_rect *cliprects */ 915718dceddSDavid Howells __u64 cliprects_ptr; 916718dceddSDavid Howells }; 917718dceddSDavid Howells 918718dceddSDavid Howells struct drm_i915_gem_exec_object2 { 919718dceddSDavid Howells /** 920718dceddSDavid Howells * User's handle for a buffer to be bound into the GTT for this 921718dceddSDavid Howells * operation. 922718dceddSDavid Howells */ 923718dceddSDavid Howells __u32 handle; 924718dceddSDavid Howells 925718dceddSDavid Howells /** Number of relocations to be performed on this buffer */ 926718dceddSDavid Howells __u32 relocation_count; 927718dceddSDavid Howells /** 928718dceddSDavid Howells * Pointer to array of struct drm_i915_gem_relocation_entry containing 929718dceddSDavid Howells * the relocations to be performed in this buffer. 930718dceddSDavid Howells */ 931718dceddSDavid Howells __u64 relocs_ptr; 932718dceddSDavid Howells 933718dceddSDavid Howells /** Required alignment in graphics aperture */ 934718dceddSDavid Howells __u64 alignment; 935718dceddSDavid Howells 936718dceddSDavid Howells /** 937506a8e87SChris Wilson * When the EXEC_OBJECT_PINNED flag is specified this is populated by 938506a8e87SChris Wilson * the user with the GTT offset at which this object will be pinned. 939506a8e87SChris Wilson * When the I915_EXEC_NO_RELOC flag is specified this must contain the 940506a8e87SChris Wilson * presumed_offset of the object. 941506a8e87SChris Wilson * During execbuffer2 the kernel populates it with the value of the 942506a8e87SChris Wilson * current GTT offset of the object, for future presumed_offset writes. 943718dceddSDavid Howells */ 944718dceddSDavid Howells __u64 offset; 945718dceddSDavid Howells 946718dceddSDavid Howells #define EXEC_OBJECT_NEEDS_FENCE (1<<0) 947ed5982e6SDaniel Vetter #define EXEC_OBJECT_NEEDS_GTT (1<<1) 948ed5982e6SDaniel Vetter #define EXEC_OBJECT_WRITE (1<<2) 949101b506aSMichel Thierry #define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3) 950506a8e87SChris Wilson #define EXEC_OBJECT_PINNED (1<<4) 95191b2db6fSChris Wilson #define EXEC_OBJECT_PAD_TO_SIZE (1<<5) 95277ae9957SChris Wilson /* The kernel implicitly tracks GPU activity on all GEM objects, and 95377ae9957SChris Wilson * synchronises operations with outstanding rendering. This includes 95477ae9957SChris Wilson * rendering on other devices if exported via dma-buf. However, sometimes 95577ae9957SChris Wilson * this tracking is too coarse and the user knows better. For example, 95677ae9957SChris Wilson * if the object is split into non-overlapping ranges shared between different 95777ae9957SChris Wilson * clients or engines (i.e. suballocating objects), the implicit tracking 95877ae9957SChris Wilson * by kernel assumes that each operation affects the whole object rather 95977ae9957SChris Wilson * than an individual range, causing needless synchronisation between clients. 96077ae9957SChris Wilson * The kernel will also forgo any CPU cache flushes prior to rendering from 96177ae9957SChris Wilson * the object as the client is expected to be also handling such domain 96277ae9957SChris Wilson * tracking. 96377ae9957SChris Wilson * 96477ae9957SChris Wilson * The kernel maintains the implicit tracking in order to manage resources 96577ae9957SChris Wilson * used by the GPU - this flag only disables the synchronisation prior to 96677ae9957SChris Wilson * rendering with this object in this execbuf. 96777ae9957SChris Wilson * 96877ae9957SChris Wilson * Opting out of implicit synhronisation requires the user to do its own 96977ae9957SChris Wilson * explicit tracking to avoid rendering corruption. See, for example, 97077ae9957SChris Wilson * I915_PARAM_HAS_EXEC_FENCE to order execbufs and execute them asynchronously. 97177ae9957SChris Wilson */ 97277ae9957SChris Wilson #define EXEC_OBJECT_ASYNC (1<<6) 973b0fd47adSChris Wilson /* Request that the contents of this execobject be copied into the error 974b0fd47adSChris Wilson * state upon a GPU hang involving this batch for post-mortem debugging. 975b0fd47adSChris Wilson * These buffers are recorded in no particular order as "user" in 976b0fd47adSChris Wilson * /sys/class/drm/cardN/error. Query I915_PARAM_HAS_EXEC_CAPTURE to see 977b0fd47adSChris Wilson * if the kernel supports this flag. 978b0fd47adSChris Wilson */ 979b0fd47adSChris Wilson #define EXEC_OBJECT_CAPTURE (1<<7) 9809e2793f6SDave Gordon /* All remaining bits are MBZ and RESERVED FOR FUTURE USE */ 981b0fd47adSChris Wilson #define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_CAPTURE<<1) 982718dceddSDavid Howells __u64 flags; 983ed5982e6SDaniel Vetter 98491b2db6fSChris Wilson union { 985718dceddSDavid Howells __u64 rsvd1; 98691b2db6fSChris Wilson __u64 pad_to_size; 98791b2db6fSChris Wilson }; 988718dceddSDavid Howells __u64 rsvd2; 989718dceddSDavid Howells }; 990718dceddSDavid Howells 991cf6e7bacSJason Ekstrand struct drm_i915_gem_exec_fence { 992cf6e7bacSJason Ekstrand /** 993cf6e7bacSJason Ekstrand * User's handle for a drm_syncobj to wait on or signal. 994cf6e7bacSJason Ekstrand */ 995cf6e7bacSJason Ekstrand __u32 handle; 996cf6e7bacSJason Ekstrand 997cf6e7bacSJason Ekstrand #define I915_EXEC_FENCE_WAIT (1<<0) 998cf6e7bacSJason Ekstrand #define I915_EXEC_FENCE_SIGNAL (1<<1) 999ebcaa1ffSTvrtko Ursulin #define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1)) 1000cf6e7bacSJason Ekstrand __u32 flags; 1001cf6e7bacSJason Ekstrand }; 1002cf6e7bacSJason Ekstrand 1003718dceddSDavid Howells struct drm_i915_gem_execbuffer2 { 1004718dceddSDavid Howells /** 1005718dceddSDavid Howells * List of gem_exec_object2 structs 1006718dceddSDavid Howells */ 1007718dceddSDavid Howells __u64 buffers_ptr; 1008718dceddSDavid Howells __u32 buffer_count; 1009718dceddSDavid Howells 1010718dceddSDavid Howells /** Offset in the batchbuffer to start execution from. */ 1011718dceddSDavid Howells __u32 batch_start_offset; 1012718dceddSDavid Howells /** Bytes used in batchbuffer from batch_start_offset */ 1013718dceddSDavid Howells __u32 batch_len; 1014718dceddSDavid Howells __u32 DR1; 1015718dceddSDavid Howells __u32 DR4; 1016718dceddSDavid Howells __u32 num_cliprects; 1017cf6e7bacSJason Ekstrand /** 1018cf6e7bacSJason Ekstrand * This is a struct drm_clip_rect *cliprects if I915_EXEC_FENCE_ARRAY 1019cf6e7bacSJason Ekstrand * is not set. If I915_EXEC_FENCE_ARRAY is set, then this is a 1020cf6e7bacSJason Ekstrand * struct drm_i915_gem_exec_fence *fences. 1021cf6e7bacSJason Ekstrand */ 1022718dceddSDavid Howells __u64 cliprects_ptr; 1023d90c06d5SChris Wilson #define I915_EXEC_RING_MASK (0x3f) 1024718dceddSDavid Howells #define I915_EXEC_DEFAULT (0<<0) 1025718dceddSDavid Howells #define I915_EXEC_RENDER (1<<0) 1026718dceddSDavid Howells #define I915_EXEC_BSD (2<<0) 1027718dceddSDavid Howells #define I915_EXEC_BLT (3<<0) 102882f91b6eSXiang, Haihao #define I915_EXEC_VEBOX (4<<0) 1029718dceddSDavid Howells 1030718dceddSDavid Howells /* Used for switching the constants addressing mode on gen4+ RENDER ring. 1031718dceddSDavid Howells * Gen6+ only supports relative addressing to dynamic state (default) and 1032718dceddSDavid Howells * absolute addressing. 1033718dceddSDavid Howells * 1034718dceddSDavid Howells * These flags are ignored for the BSD and BLT rings. 1035718dceddSDavid Howells */ 1036718dceddSDavid Howells #define I915_EXEC_CONSTANTS_MASK (3<<6) 1037718dceddSDavid Howells #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ 1038718dceddSDavid Howells #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) 1039718dceddSDavid Howells #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ 1040718dceddSDavid Howells __u64 flags; 1041718dceddSDavid Howells __u64 rsvd1; /* now used for context info */ 1042718dceddSDavid Howells __u64 rsvd2; 1043718dceddSDavid Howells }; 1044718dceddSDavid Howells 1045718dceddSDavid Howells /** Resets the SO write offset registers for transform feedback on gen7. */ 1046718dceddSDavid Howells #define I915_EXEC_GEN7_SOL_RESET (1<<8) 1047718dceddSDavid Howells 1048c2fb7916SDaniel Vetter /** Request a privileged ("secure") batch buffer. Note only available for 1049c2fb7916SDaniel Vetter * DRM_ROOT_ONLY | DRM_MASTER processes. 1050c2fb7916SDaniel Vetter */ 1051c2fb7916SDaniel Vetter #define I915_EXEC_SECURE (1<<9) 1052c2fb7916SDaniel Vetter 1053b45305fcSDaniel Vetter /** Inform the kernel that the batch is and will always be pinned. This 1054b45305fcSDaniel Vetter * negates the requirement for a workaround to be performed to avoid 1055b45305fcSDaniel Vetter * an incoherent CS (such as can be found on 830/845). If this flag is 1056b45305fcSDaniel Vetter * not passed, the kernel will endeavour to make sure the batch is 1057b45305fcSDaniel Vetter * coherent with the CS before execution. If this flag is passed, 1058b45305fcSDaniel Vetter * userspace assumes the responsibility for ensuring the same. 1059b45305fcSDaniel Vetter */ 1060b45305fcSDaniel Vetter #define I915_EXEC_IS_PINNED (1<<10) 1061b45305fcSDaniel Vetter 1062c3d19d3cSGeert Uytterhoeven /** Provide a hint to the kernel that the command stream and auxiliary 1063ed5982e6SDaniel Vetter * state buffers already holds the correct presumed addresses and so the 1064ed5982e6SDaniel Vetter * relocation process may be skipped if no buffers need to be moved in 1065ed5982e6SDaniel Vetter * preparation for the execbuffer. 1066ed5982e6SDaniel Vetter */ 1067ed5982e6SDaniel Vetter #define I915_EXEC_NO_RELOC (1<<11) 1068ed5982e6SDaniel Vetter 1069eef90ccbSChris Wilson /** Use the reloc.handle as an index into the exec object array rather 1070eef90ccbSChris Wilson * than as the per-file handle. 1071eef90ccbSChris Wilson */ 1072eef90ccbSChris Wilson #define I915_EXEC_HANDLE_LUT (1<<12) 1073eef90ccbSChris Wilson 10748d360dffSZhipeng Gong /** Used for switching BSD rings on the platforms with two BSD rings */ 1075d9da6aa0STvrtko Ursulin #define I915_EXEC_BSD_SHIFT (13) 1076d9da6aa0STvrtko Ursulin #define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT) 1077d9da6aa0STvrtko Ursulin /* default ping-pong mode */ 1078d9da6aa0STvrtko Ursulin #define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT) 1079d9da6aa0STvrtko Ursulin #define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT) 1080d9da6aa0STvrtko Ursulin #define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT) 10818d360dffSZhipeng Gong 1082a9ed33caSAbdiel Janulgue /** Tell the kernel that the batchbuffer is processed by 1083a9ed33caSAbdiel Janulgue * the resource streamer. 1084a9ed33caSAbdiel Janulgue */ 1085a9ed33caSAbdiel Janulgue #define I915_EXEC_RESOURCE_STREAMER (1<<15) 1086a9ed33caSAbdiel Janulgue 1087fec0445cSChris Wilson /* Setting I915_EXEC_FENCE_IN implies that lower_32_bits(rsvd2) represent 1088fec0445cSChris Wilson * a sync_file fd to wait upon (in a nonblocking manner) prior to executing 1089fec0445cSChris Wilson * the batch. 1090fec0445cSChris Wilson * 1091fec0445cSChris Wilson * Returns -EINVAL if the sync_file fd cannot be found. 1092fec0445cSChris Wilson */ 1093fec0445cSChris Wilson #define I915_EXEC_FENCE_IN (1<<16) 1094fec0445cSChris Wilson 1095fec0445cSChris Wilson /* Setting I915_EXEC_FENCE_OUT causes the ioctl to return a sync_file fd 1096fec0445cSChris Wilson * in the upper_32_bits(rsvd2) upon success. Ownership of the fd is given 1097fec0445cSChris Wilson * to the caller, and it should be close() after use. (The fd is a regular 1098fec0445cSChris Wilson * file descriptor and will be cleaned up on process termination. It holds 1099fec0445cSChris Wilson * a reference to the request, but nothing else.) 1100fec0445cSChris Wilson * 1101fec0445cSChris Wilson * The sync_file fd can be combined with other sync_file and passed either 1102fec0445cSChris Wilson * to execbuf using I915_EXEC_FENCE_IN, to atomic KMS ioctls (so that a flip 1103fec0445cSChris Wilson * will only occur after this request completes), or to other devices. 1104fec0445cSChris Wilson * 1105fec0445cSChris Wilson * Using I915_EXEC_FENCE_OUT requires use of 1106fec0445cSChris Wilson * DRM_IOCTL_I915_GEM_EXECBUFFER2_WR ioctl so that the result is written 1107fec0445cSChris Wilson * back to userspace. Failure to do so will cause the out-fence to always 1108fec0445cSChris Wilson * be reported as zero, and the real fence fd to be leaked. 1109fec0445cSChris Wilson */ 1110fec0445cSChris Wilson #define I915_EXEC_FENCE_OUT (1<<17) 1111fec0445cSChris Wilson 11121a71cf2fSChris Wilson /* 11131a71cf2fSChris Wilson * Traditionally the execbuf ioctl has only considered the final element in 11141a71cf2fSChris Wilson * the execobject[] to be the executable batch. Often though, the client 11151a71cf2fSChris Wilson * will known the batch object prior to construction and being able to place 11161a71cf2fSChris Wilson * it into the execobject[] array first can simplify the relocation tracking. 11171a71cf2fSChris Wilson * Setting I915_EXEC_BATCH_FIRST tells execbuf to use element 0 of the 11181a71cf2fSChris Wilson * execobject[] as the * batch instead (the default is to use the last 11191a71cf2fSChris Wilson * element). 11201a71cf2fSChris Wilson */ 11211a71cf2fSChris Wilson #define I915_EXEC_BATCH_FIRST (1<<18) 1122cf6e7bacSJason Ekstrand 1123cf6e7bacSJason Ekstrand /* Setting I915_FENCE_ARRAY implies that num_cliprects and cliprects_ptr 1124cf6e7bacSJason Ekstrand * define an array of i915_gem_exec_fence structures which specify a set of 1125cf6e7bacSJason Ekstrand * dma fences to wait upon or signal. 1126cf6e7bacSJason Ekstrand */ 1127cf6e7bacSJason Ekstrand #define I915_EXEC_FENCE_ARRAY (1<<19) 1128cf6e7bacSJason Ekstrand 1129cf6e7bacSJason Ekstrand #define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_ARRAY<<1)) 1130ed5982e6SDaniel Vetter 1131718dceddSDavid Howells #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) 1132718dceddSDavid Howells #define i915_execbuffer2_set_context_id(eb2, context) \ 1133718dceddSDavid Howells (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK 1134718dceddSDavid Howells #define i915_execbuffer2_get_context_id(eb2) \ 1135718dceddSDavid Howells ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) 1136718dceddSDavid Howells 1137718dceddSDavid Howells struct drm_i915_gem_pin { 1138718dceddSDavid Howells /** Handle of the buffer to be pinned. */ 1139718dceddSDavid Howells __u32 handle; 1140718dceddSDavid Howells __u32 pad; 1141718dceddSDavid Howells 1142718dceddSDavid Howells /** alignment required within the aperture */ 1143718dceddSDavid Howells __u64 alignment; 1144718dceddSDavid Howells 1145718dceddSDavid Howells /** Returned GTT offset of the buffer. */ 1146718dceddSDavid Howells __u64 offset; 1147718dceddSDavid Howells }; 1148718dceddSDavid Howells 1149718dceddSDavid Howells struct drm_i915_gem_unpin { 1150718dceddSDavid Howells /** Handle of the buffer to be unpinned. */ 1151718dceddSDavid Howells __u32 handle; 1152718dceddSDavid Howells __u32 pad; 1153718dceddSDavid Howells }; 1154718dceddSDavid Howells 1155718dceddSDavid Howells struct drm_i915_gem_busy { 1156718dceddSDavid Howells /** Handle of the buffer to check for busy */ 1157718dceddSDavid Howells __u32 handle; 1158718dceddSDavid Howells 1159426960beSChris Wilson /** Return busy status 1160426960beSChris Wilson * 1161426960beSChris Wilson * A return of 0 implies that the object is idle (after 1162426960beSChris Wilson * having flushed any pending activity), and a non-zero return that 1163426960beSChris Wilson * the object is still in-flight on the GPU. (The GPU has not yet 1164426960beSChris Wilson * signaled completion for all pending requests that reference the 11651255501dSChris Wilson * object.) An object is guaranteed to become idle eventually (so 11661255501dSChris Wilson * long as no new GPU commands are executed upon it). Due to the 11671255501dSChris Wilson * asynchronous nature of the hardware, an object reported 11681255501dSChris Wilson * as busy may become idle before the ioctl is completed. 11691255501dSChris Wilson * 11701255501dSChris Wilson * Furthermore, if the object is busy, which engine is busy is only 1171c8b50242SChris Wilson * provided as a guide and only indirectly by reporting its class 1172c8b50242SChris Wilson * (there may be more than one engine in each class). There are race 1173c8b50242SChris Wilson * conditions which prevent the report of which engines are busy from 1174c8b50242SChris Wilson * being always accurate. However, the converse is not true. If the 1175c8b50242SChris Wilson * object is idle, the result of the ioctl, that all engines are idle, 1176c8b50242SChris Wilson * is accurate. 1177426960beSChris Wilson * 1178426960beSChris Wilson * The returned dword is split into two fields to indicate both 1179c8b50242SChris Wilson * the engine classess on which the object is being read, and the 1180c8b50242SChris Wilson * engine class on which it is currently being written (if any). 1181426960beSChris Wilson * 1182426960beSChris Wilson * The low word (bits 0:15) indicate if the object is being written 1183426960beSChris Wilson * to by any engine (there can only be one, as the GEM implicit 1184426960beSChris Wilson * synchronisation rules force writes to be serialised). Only the 1185c8b50242SChris Wilson * engine class (offset by 1, I915_ENGINE_CLASS_RENDER is reported as 1186c8b50242SChris Wilson * 1 not 0 etc) for the last write is reported. 1187426960beSChris Wilson * 1188c8b50242SChris Wilson * The high word (bits 16:31) are a bitmask of which engines classes 1189c8b50242SChris Wilson * are currently reading from the object. Multiple engines may be 1190426960beSChris Wilson * reading from the object simultaneously. 1191426960beSChris Wilson * 1192c8b50242SChris Wilson * The value of each engine class is the same as specified in the 1193c8b50242SChris Wilson * I915_CONTEXT_SET_ENGINES parameter and via perf, i.e. 1194c8b50242SChris Wilson * I915_ENGINE_CLASS_RENDER, I915_ENGINE_CLASS_COPY, etc. 1195426960beSChris Wilson * reported as active itself. Some hardware may have parallel 1196426960beSChris Wilson * execution engines, e.g. multiple media engines, which are 1197c8b50242SChris Wilson * mapped to the same class identifier and so are not separately 1198c8b50242SChris Wilson * reported for busyness. 11991255501dSChris Wilson * 12001255501dSChris Wilson * Caveat emptor: 12011255501dSChris Wilson * Only the boolean result of this query is reliable; that is whether 12021255501dSChris Wilson * the object is idle or busy. The report of which engines are busy 12031255501dSChris Wilson * should be only used as a heuristic. 1204718dceddSDavid Howells */ 1205718dceddSDavid Howells __u32 busy; 1206718dceddSDavid Howells }; 1207718dceddSDavid Howells 120835c7ab42SDaniel Vetter /** 120935c7ab42SDaniel Vetter * I915_CACHING_NONE 121035c7ab42SDaniel Vetter * 121135c7ab42SDaniel Vetter * GPU access is not coherent with cpu caches. Default for machines without an 121235c7ab42SDaniel Vetter * LLC. 121335c7ab42SDaniel Vetter */ 1214718dceddSDavid Howells #define I915_CACHING_NONE 0 121535c7ab42SDaniel Vetter /** 121635c7ab42SDaniel Vetter * I915_CACHING_CACHED 121735c7ab42SDaniel Vetter * 121835c7ab42SDaniel Vetter * GPU access is coherent with cpu caches and furthermore the data is cached in 121935c7ab42SDaniel Vetter * last-level caches shared between cpu cores and the gpu GT. Default on 122035c7ab42SDaniel Vetter * machines with HAS_LLC. 122135c7ab42SDaniel Vetter */ 1222718dceddSDavid Howells #define I915_CACHING_CACHED 1 122335c7ab42SDaniel Vetter /** 122435c7ab42SDaniel Vetter * I915_CACHING_DISPLAY 122535c7ab42SDaniel Vetter * 122635c7ab42SDaniel Vetter * Special GPU caching mode which is coherent with the scanout engines. 122735c7ab42SDaniel Vetter * Transparently falls back to I915_CACHING_NONE on platforms where no special 122835c7ab42SDaniel Vetter * cache mode (like write-through or gfdt flushing) is available. The kernel 122935c7ab42SDaniel Vetter * automatically sets this mode when using a buffer as a scanout target. 123035c7ab42SDaniel Vetter * Userspace can manually set this mode to avoid a costly stall and clflush in 123135c7ab42SDaniel Vetter * the hotpath of drawing the first frame. 123235c7ab42SDaniel Vetter */ 123335c7ab42SDaniel Vetter #define I915_CACHING_DISPLAY 2 1234718dceddSDavid Howells 1235718dceddSDavid Howells struct drm_i915_gem_caching { 1236718dceddSDavid Howells /** 1237718dceddSDavid Howells * Handle of the buffer to set/get the caching level of. */ 1238718dceddSDavid Howells __u32 handle; 1239718dceddSDavid Howells 1240718dceddSDavid Howells /** 1241718dceddSDavid Howells * Cacheing level to apply or return value 1242718dceddSDavid Howells * 1243718dceddSDavid Howells * bits0-15 are for generic caching control (i.e. the above defined 1244718dceddSDavid Howells * values). bits16-31 are reserved for platform-specific variations 1245718dceddSDavid Howells * (e.g. l3$ caching on gen7). */ 1246718dceddSDavid Howells __u32 caching; 1247718dceddSDavid Howells }; 1248718dceddSDavid Howells 1249718dceddSDavid Howells #define I915_TILING_NONE 0 1250718dceddSDavid Howells #define I915_TILING_X 1 1251718dceddSDavid Howells #define I915_TILING_Y 2 1252deeb1519SChris Wilson #define I915_TILING_LAST I915_TILING_Y 1253718dceddSDavid Howells 1254718dceddSDavid Howells #define I915_BIT_6_SWIZZLE_NONE 0 1255718dceddSDavid Howells #define I915_BIT_6_SWIZZLE_9 1 1256718dceddSDavid Howells #define I915_BIT_6_SWIZZLE_9_10 2 1257718dceddSDavid Howells #define I915_BIT_6_SWIZZLE_9_11 3 1258718dceddSDavid Howells #define I915_BIT_6_SWIZZLE_9_10_11 4 1259718dceddSDavid Howells /* Not seen by userland */ 1260718dceddSDavid Howells #define I915_BIT_6_SWIZZLE_UNKNOWN 5 1261718dceddSDavid Howells /* Seen by userland. */ 1262718dceddSDavid Howells #define I915_BIT_6_SWIZZLE_9_17 6 1263718dceddSDavid Howells #define I915_BIT_6_SWIZZLE_9_10_17 7 1264718dceddSDavid Howells 1265718dceddSDavid Howells struct drm_i915_gem_set_tiling { 1266718dceddSDavid Howells /** Handle of the buffer to have its tiling state updated */ 1267718dceddSDavid Howells __u32 handle; 1268718dceddSDavid Howells 1269718dceddSDavid Howells /** 1270718dceddSDavid Howells * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 1271718dceddSDavid Howells * I915_TILING_Y). 1272718dceddSDavid Howells * 1273718dceddSDavid Howells * This value is to be set on request, and will be updated by the 1274718dceddSDavid Howells * kernel on successful return with the actual chosen tiling layout. 1275718dceddSDavid Howells * 1276718dceddSDavid Howells * The tiling mode may be demoted to I915_TILING_NONE when the system 1277718dceddSDavid Howells * has bit 6 swizzling that can't be managed correctly by GEM. 1278718dceddSDavid Howells * 1279718dceddSDavid Howells * Buffer contents become undefined when changing tiling_mode. 1280718dceddSDavid Howells */ 1281718dceddSDavid Howells __u32 tiling_mode; 1282718dceddSDavid Howells 1283718dceddSDavid Howells /** 1284718dceddSDavid Howells * Stride in bytes for the object when in I915_TILING_X or 1285718dceddSDavid Howells * I915_TILING_Y. 1286718dceddSDavid Howells */ 1287718dceddSDavid Howells __u32 stride; 1288718dceddSDavid Howells 1289718dceddSDavid Howells /** 1290718dceddSDavid Howells * Returned address bit 6 swizzling required for CPU access through 1291718dceddSDavid Howells * mmap mapping. 1292718dceddSDavid Howells */ 1293718dceddSDavid Howells __u32 swizzle_mode; 1294718dceddSDavid Howells }; 1295718dceddSDavid Howells 1296718dceddSDavid Howells struct drm_i915_gem_get_tiling { 1297718dceddSDavid Howells /** Handle of the buffer to get tiling state for. */ 1298718dceddSDavid Howells __u32 handle; 1299718dceddSDavid Howells 1300718dceddSDavid Howells /** 1301718dceddSDavid Howells * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 1302718dceddSDavid Howells * I915_TILING_Y). 1303718dceddSDavid Howells */ 1304718dceddSDavid Howells __u32 tiling_mode; 1305718dceddSDavid Howells 1306718dceddSDavid Howells /** 1307718dceddSDavid Howells * Returned address bit 6 swizzling required for CPU access through 1308718dceddSDavid Howells * mmap mapping. 1309718dceddSDavid Howells */ 1310718dceddSDavid Howells __u32 swizzle_mode; 131170f2f5c7SChris Wilson 131270f2f5c7SChris Wilson /** 131370f2f5c7SChris Wilson * Returned address bit 6 swizzling required for CPU access through 131470f2f5c7SChris Wilson * mmap mapping whilst bound. 131570f2f5c7SChris Wilson */ 131670f2f5c7SChris Wilson __u32 phys_swizzle_mode; 1317718dceddSDavid Howells }; 1318718dceddSDavid Howells 1319718dceddSDavid Howells struct drm_i915_gem_get_aperture { 1320718dceddSDavid Howells /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ 1321718dceddSDavid Howells __u64 aper_size; 1322718dceddSDavid Howells 1323718dceddSDavid Howells /** 1324718dceddSDavid Howells * Available space in the aperture used by i915_gem_execbuffer, in 1325718dceddSDavid Howells * bytes 1326718dceddSDavid Howells */ 1327718dceddSDavid Howells __u64 aper_available_size; 1328718dceddSDavid Howells }; 1329718dceddSDavid Howells 1330718dceddSDavid Howells struct drm_i915_get_pipe_from_crtc_id { 1331718dceddSDavid Howells /** ID of CRTC being requested **/ 1332718dceddSDavid Howells __u32 crtc_id; 1333718dceddSDavid Howells 1334718dceddSDavid Howells /** pipe of requested CRTC **/ 1335718dceddSDavid Howells __u32 pipe; 1336718dceddSDavid Howells }; 1337718dceddSDavid Howells 1338718dceddSDavid Howells #define I915_MADV_WILLNEED 0 1339718dceddSDavid Howells #define I915_MADV_DONTNEED 1 1340718dceddSDavid Howells #define __I915_MADV_PURGED 2 /* internal state */ 1341718dceddSDavid Howells 1342718dceddSDavid Howells struct drm_i915_gem_madvise { 1343718dceddSDavid Howells /** Handle of the buffer to change the backing store advice */ 1344718dceddSDavid Howells __u32 handle; 1345718dceddSDavid Howells 1346718dceddSDavid Howells /* Advice: either the buffer will be needed again in the near future, 1347718dceddSDavid Howells * or wont be and could be discarded under memory pressure. 1348718dceddSDavid Howells */ 1349718dceddSDavid Howells __u32 madv; 1350718dceddSDavid Howells 1351718dceddSDavid Howells /** Whether the backing store still exists. */ 1352718dceddSDavid Howells __u32 retained; 1353718dceddSDavid Howells }; 1354718dceddSDavid Howells 1355718dceddSDavid Howells /* flags */ 1356718dceddSDavid Howells #define I915_OVERLAY_TYPE_MASK 0xff 1357718dceddSDavid Howells #define I915_OVERLAY_YUV_PLANAR 0x01 1358718dceddSDavid Howells #define I915_OVERLAY_YUV_PACKED 0x02 1359718dceddSDavid Howells #define I915_OVERLAY_RGB 0x03 1360718dceddSDavid Howells 1361718dceddSDavid Howells #define I915_OVERLAY_DEPTH_MASK 0xff00 1362718dceddSDavid Howells #define I915_OVERLAY_RGB24 0x1000 1363718dceddSDavid Howells #define I915_OVERLAY_RGB16 0x2000 1364718dceddSDavid Howells #define I915_OVERLAY_RGB15 0x3000 1365718dceddSDavid Howells #define I915_OVERLAY_YUV422 0x0100 1366718dceddSDavid Howells #define I915_OVERLAY_YUV411 0x0200 1367718dceddSDavid Howells #define I915_OVERLAY_YUV420 0x0300 1368718dceddSDavid Howells #define I915_OVERLAY_YUV410 0x0400 1369718dceddSDavid Howells 1370718dceddSDavid Howells #define I915_OVERLAY_SWAP_MASK 0xff0000 1371718dceddSDavid Howells #define I915_OVERLAY_NO_SWAP 0x000000 1372718dceddSDavid Howells #define I915_OVERLAY_UV_SWAP 0x010000 1373718dceddSDavid Howells #define I915_OVERLAY_Y_SWAP 0x020000 1374718dceddSDavid Howells #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 1375718dceddSDavid Howells 1376718dceddSDavid Howells #define I915_OVERLAY_FLAGS_MASK 0xff000000 1377718dceddSDavid Howells #define I915_OVERLAY_ENABLE 0x01000000 1378718dceddSDavid Howells 1379718dceddSDavid Howells struct drm_intel_overlay_put_image { 1380718dceddSDavid Howells /* various flags and src format description */ 1381718dceddSDavid Howells __u32 flags; 1382718dceddSDavid Howells /* source picture description */ 1383718dceddSDavid Howells __u32 bo_handle; 1384718dceddSDavid Howells /* stride values and offsets are in bytes, buffer relative */ 1385718dceddSDavid Howells __u16 stride_Y; /* stride for packed formats */ 1386718dceddSDavid Howells __u16 stride_UV; 1387718dceddSDavid Howells __u32 offset_Y; /* offset for packet formats */ 1388718dceddSDavid Howells __u32 offset_U; 1389718dceddSDavid Howells __u32 offset_V; 1390718dceddSDavid Howells /* in pixels */ 1391718dceddSDavid Howells __u16 src_width; 1392718dceddSDavid Howells __u16 src_height; 1393718dceddSDavid Howells /* to compensate the scaling factors for partially covered surfaces */ 1394718dceddSDavid Howells __u16 src_scan_width; 1395718dceddSDavid Howells __u16 src_scan_height; 1396718dceddSDavid Howells /* output crtc description */ 1397718dceddSDavid Howells __u32 crtc_id; 1398718dceddSDavid Howells __u16 dst_x; 1399718dceddSDavid Howells __u16 dst_y; 1400718dceddSDavid Howells __u16 dst_width; 1401718dceddSDavid Howells __u16 dst_height; 1402718dceddSDavid Howells }; 1403718dceddSDavid Howells 1404718dceddSDavid Howells /* flags */ 1405718dceddSDavid Howells #define I915_OVERLAY_UPDATE_ATTRS (1<<0) 1406718dceddSDavid Howells #define I915_OVERLAY_UPDATE_GAMMA (1<<1) 1407ea9da4e4SChris Wilson #define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2) 1408718dceddSDavid Howells struct drm_intel_overlay_attrs { 1409718dceddSDavid Howells __u32 flags; 1410718dceddSDavid Howells __u32 color_key; 1411718dceddSDavid Howells __s32 brightness; 1412718dceddSDavid Howells __u32 contrast; 1413718dceddSDavid Howells __u32 saturation; 1414718dceddSDavid Howells __u32 gamma0; 1415718dceddSDavid Howells __u32 gamma1; 1416718dceddSDavid Howells __u32 gamma2; 1417718dceddSDavid Howells __u32 gamma3; 1418718dceddSDavid Howells __u32 gamma4; 1419718dceddSDavid Howells __u32 gamma5; 1420718dceddSDavid Howells }; 1421718dceddSDavid Howells 1422718dceddSDavid Howells /* 1423718dceddSDavid Howells * Intel sprite handling 1424718dceddSDavid Howells * 1425718dceddSDavid Howells * Color keying works with a min/mask/max tuple. Both source and destination 1426718dceddSDavid Howells * color keying is allowed. 1427718dceddSDavid Howells * 1428718dceddSDavid Howells * Source keying: 1429718dceddSDavid Howells * Sprite pixels within the min & max values, masked against the color channels 1430718dceddSDavid Howells * specified in the mask field, will be transparent. All other pixels will 1431718dceddSDavid Howells * be displayed on top of the primary plane. For RGB surfaces, only the min 1432718dceddSDavid Howells * and mask fields will be used; ranged compares are not allowed. 1433718dceddSDavid Howells * 1434718dceddSDavid Howells * Destination keying: 1435718dceddSDavid Howells * Primary plane pixels that match the min value, masked against the color 1436718dceddSDavid Howells * channels specified in the mask field, will be replaced by corresponding 1437718dceddSDavid Howells * pixels from the sprite plane. 1438718dceddSDavid Howells * 1439718dceddSDavid Howells * Note that source & destination keying are exclusive; only one can be 1440718dceddSDavid Howells * active on a given plane. 1441718dceddSDavid Howells */ 1442718dceddSDavid Howells 14436ec5bd34SVille Syrjälä #define I915_SET_COLORKEY_NONE (1<<0) /* Deprecated. Instead set 14446ec5bd34SVille Syrjälä * flags==0 to disable colorkeying. 14456ec5bd34SVille Syrjälä */ 1446718dceddSDavid Howells #define I915_SET_COLORKEY_DESTINATION (1<<1) 1447718dceddSDavid Howells #define I915_SET_COLORKEY_SOURCE (1<<2) 1448718dceddSDavid Howells struct drm_intel_sprite_colorkey { 1449718dceddSDavid Howells __u32 plane_id; 1450718dceddSDavid Howells __u32 min_value; 1451718dceddSDavid Howells __u32 channel_mask; 1452718dceddSDavid Howells __u32 max_value; 1453718dceddSDavid Howells __u32 flags; 1454718dceddSDavid Howells }; 1455718dceddSDavid Howells 1456718dceddSDavid Howells struct drm_i915_gem_wait { 1457718dceddSDavid Howells /** Handle of BO we shall wait on */ 1458718dceddSDavid Howells __u32 bo_handle; 1459718dceddSDavid Howells __u32 flags; 1460718dceddSDavid Howells /** Number of nanoseconds to wait, Returns time remaining. */ 1461718dceddSDavid Howells __s64 timeout_ns; 1462718dceddSDavid Howells }; 1463718dceddSDavid Howells 1464718dceddSDavid Howells struct drm_i915_gem_context_create { 1465b9171541SChris Wilson __u32 ctx_id; /* output: id of new context*/ 1466718dceddSDavid Howells __u32 pad; 1467718dceddSDavid Howells }; 1468718dceddSDavid Howells 1469b9171541SChris Wilson struct drm_i915_gem_context_create_ext { 1470b9171541SChris Wilson __u32 ctx_id; /* output: id of new context*/ 1471b9171541SChris Wilson __u32 flags; 1472b9171541SChris Wilson #define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0) 14738319f44cSChris Wilson #define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE (1u << 1) 1474b9171541SChris Wilson #define I915_CONTEXT_CREATE_FLAGS_UNKNOWN \ 14758319f44cSChris Wilson (-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1)) 1476e0695db7SChris Wilson __u64 extensions; 14775cc9ed4bSChris Wilson }; 14785cc9ed4bSChris Wilson 1479c9dc0f35SChris Wilson struct drm_i915_gem_context_param { 1480c9dc0f35SChris Wilson __u32 ctx_id; 1481c9dc0f35SChris Wilson __u32 size; 1482c9dc0f35SChris Wilson __u64 param; 1483c9dc0f35SChris Wilson #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1 1484b1b38278SDavid Weinehall #define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2 1485fa8848f2SChris Wilson #define I915_CONTEXT_PARAM_GTT_SIZE 0x3 1486bc3d6744SChris Wilson #define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4 148784102171SMika Kuoppala #define I915_CONTEXT_PARAM_BANNABLE 0x5 1488ac14fbd4SChris Wilson #define I915_CONTEXT_PARAM_PRIORITY 0x6 1489ac14fbd4SChris Wilson #define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */ 1490ac14fbd4SChris Wilson #define I915_CONTEXT_DEFAULT_PRIORITY 0 1491ac14fbd4SChris Wilson #define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */ 1492e46c2e99STvrtko Ursulin /* 1493e46c2e99STvrtko Ursulin * When using the following param, value should be a pointer to 1494e46c2e99STvrtko Ursulin * drm_i915_gem_context_param_sseu. 1495e46c2e99STvrtko Ursulin */ 1496e46c2e99STvrtko Ursulin #define I915_CONTEXT_PARAM_SSEU 0x7 1497ba4fda62SChris Wilson 1498ba4fda62SChris Wilson /* 1499ba4fda62SChris Wilson * Not all clients may want to attempt automatic recover of a context after 1500ba4fda62SChris Wilson * a hang (for example, some clients may only submit very small incremental 1501ba4fda62SChris Wilson * batches relying on known logical state of previous batches which will never 1502ba4fda62SChris Wilson * recover correctly and each attempt will hang), and so would prefer that 1503ba4fda62SChris Wilson * the context is forever banned instead. 1504ba4fda62SChris Wilson * 1505ba4fda62SChris Wilson * If set to false (0), after a reset, subsequent (and in flight) rendering 1506ba4fda62SChris Wilson * from this context is discarded, and the client will need to create a new 1507ba4fda62SChris Wilson * context to use instead. 1508ba4fda62SChris Wilson * 1509ba4fda62SChris Wilson * If set to true (1), the kernel will automatically attempt to recover the 1510ba4fda62SChris Wilson * context by skipping the hanging batch and executing the next batch starting 1511ba4fda62SChris Wilson * from the default context state (discarding the incomplete logical context 1512ba4fda62SChris Wilson * state lost due to the reset). 1513ba4fda62SChris Wilson * 1514ba4fda62SChris Wilson * On creation, all new contexts are marked as recoverable. 1515ba4fda62SChris Wilson */ 1516ba4fda62SChris Wilson #define I915_CONTEXT_PARAM_RECOVERABLE 0x8 15177f3f317aSChris Wilson 15187f3f317aSChris Wilson /* 15197f3f317aSChris Wilson * The id of the associated virtual memory address space (ppGTT) of 15207f3f317aSChris Wilson * this context. Can be retrieved and passed to another context 15217f3f317aSChris Wilson * (on the same fd) for both to use the same ppGTT and so share 15227f3f317aSChris Wilson * address layouts, and avoid reloading the page tables on context 15237f3f317aSChris Wilson * switches between themselves. 15247f3f317aSChris Wilson * 15257f3f317aSChris Wilson * See DRM_I915_GEM_VM_CREATE and DRM_I915_GEM_VM_DESTROY. 15267f3f317aSChris Wilson */ 15277f3f317aSChris Wilson #define I915_CONTEXT_PARAM_VM 0x9 1528976b55f0SChris Wilson 1529976b55f0SChris Wilson /* 1530976b55f0SChris Wilson * I915_CONTEXT_PARAM_ENGINES: 1531976b55f0SChris Wilson * 1532976b55f0SChris Wilson * Bind this context to operate on this subset of available engines. Henceforth, 1533976b55f0SChris Wilson * the I915_EXEC_RING selector for DRM_IOCTL_I915_GEM_EXECBUFFER2 operates as 1534976b55f0SChris Wilson * an index into this array of engines; I915_EXEC_DEFAULT selecting engine[0] 1535976b55f0SChris Wilson * and upwards. Slots 0...N are filled in using the specified (class, instance). 1536976b55f0SChris Wilson * Use 1537976b55f0SChris Wilson * engine_class: I915_ENGINE_CLASS_INVALID, 1538976b55f0SChris Wilson * engine_instance: I915_ENGINE_CLASS_INVALID_NONE 1539976b55f0SChris Wilson * to specify a gap in the array that can be filled in later, e.g. by a 1540976b55f0SChris Wilson * virtual engine used for load balancing. 1541976b55f0SChris Wilson * 1542976b55f0SChris Wilson * Setting the number of engines bound to the context to 0, by passing a zero 1543976b55f0SChris Wilson * sized argument, will revert back to default settings. 1544976b55f0SChris Wilson * 1545976b55f0SChris Wilson * See struct i915_context_param_engines. 1546ee113690SChris Wilson * 1547ee113690SChris Wilson * Extensions: 1548ee113690SChris Wilson * i915_context_engines_load_balance (I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE) 1549ee113690SChris Wilson * i915_context_engines_bond (I915_CONTEXT_ENGINES_EXT_BOND) 1550976b55f0SChris Wilson */ 1551976b55f0SChris Wilson #define I915_CONTEXT_PARAM_ENGINES 0xa 1552be03564bSChris Wilson /* Must be kept compact -- no holes and well documented */ 1553e0695db7SChris Wilson 1554c9dc0f35SChris Wilson __u64 value; 1555c9dc0f35SChris Wilson }; 1556c9dc0f35SChris Wilson 1557e46c2e99STvrtko Ursulin /** 1558e46c2e99STvrtko Ursulin * Context SSEU programming 1559e46c2e99STvrtko Ursulin * 1560e46c2e99STvrtko Ursulin * It may be necessary for either functional or performance reason to configure 1561e46c2e99STvrtko Ursulin * a context to run with a reduced number of SSEU (where SSEU stands for Slice/ 1562e46c2e99STvrtko Ursulin * Sub-slice/EU). 1563e46c2e99STvrtko Ursulin * 1564e46c2e99STvrtko Ursulin * This is done by configuring SSEU configuration using the below 1565e46c2e99STvrtko Ursulin * @struct drm_i915_gem_context_param_sseu for every supported engine which 1566e46c2e99STvrtko Ursulin * userspace intends to use. 1567e46c2e99STvrtko Ursulin * 1568e46c2e99STvrtko Ursulin * Not all GPUs or engines support this functionality in which case an error 1569e46c2e99STvrtko Ursulin * code -ENODEV will be returned. 1570e46c2e99STvrtko Ursulin * 1571e46c2e99STvrtko Ursulin * Also, flexibility of possible SSEU configuration permutations varies between 1572e46c2e99STvrtko Ursulin * GPU generations and software imposed limitations. Requesting such a 1573e46c2e99STvrtko Ursulin * combination will return an error code of -EINVAL. 1574e46c2e99STvrtko Ursulin * 1575e46c2e99STvrtko Ursulin * NOTE: When perf/OA is active the context's SSEU configuration is ignored in 1576e46c2e99STvrtko Ursulin * favour of a single global setting. 1577e46c2e99STvrtko Ursulin */ 1578e46c2e99STvrtko Ursulin struct drm_i915_gem_context_param_sseu { 1579e46c2e99STvrtko Ursulin /* 1580e46c2e99STvrtko Ursulin * Engine class & instance to be configured or queried. 1581e46c2e99STvrtko Ursulin */ 1582d1172ab3SChris Wilson struct i915_engine_class_instance engine; 1583e46c2e99STvrtko Ursulin 1584e46c2e99STvrtko Ursulin /* 1585e620f7b3SChris Wilson * Unknown flags must be cleared to zero. 1586e46c2e99STvrtko Ursulin */ 1587e46c2e99STvrtko Ursulin __u32 flags; 1588e620f7b3SChris Wilson #define I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX (1u << 0) 1589e46c2e99STvrtko Ursulin 1590e46c2e99STvrtko Ursulin /* 1591e46c2e99STvrtko Ursulin * Mask of slices to enable for the context. Valid values are a subset 1592e46c2e99STvrtko Ursulin * of the bitmask value returned for I915_PARAM_SLICE_MASK. 1593e46c2e99STvrtko Ursulin */ 1594e46c2e99STvrtko Ursulin __u64 slice_mask; 1595e46c2e99STvrtko Ursulin 1596e46c2e99STvrtko Ursulin /* 1597e46c2e99STvrtko Ursulin * Mask of subslices to enable for the context. Valid values are a 1598e46c2e99STvrtko Ursulin * subset of the bitmask value return by I915_PARAM_SUBSLICE_MASK. 1599e46c2e99STvrtko Ursulin */ 1600e46c2e99STvrtko Ursulin __u64 subslice_mask; 1601e46c2e99STvrtko Ursulin 1602e46c2e99STvrtko Ursulin /* 1603e46c2e99STvrtko Ursulin * Minimum/Maximum number of EUs to enable per subslice for the 1604e46c2e99STvrtko Ursulin * context. min_eus_per_subslice must be inferior or equal to 1605e46c2e99STvrtko Ursulin * max_eus_per_subslice. 1606e46c2e99STvrtko Ursulin */ 1607e46c2e99STvrtko Ursulin __u16 min_eus_per_subslice; 1608e46c2e99STvrtko Ursulin __u16 max_eus_per_subslice; 1609e46c2e99STvrtko Ursulin 1610e46c2e99STvrtko Ursulin /* 1611e46c2e99STvrtko Ursulin * Unused for now. Must be cleared to zero. 1612e46c2e99STvrtko Ursulin */ 1613e46c2e99STvrtko Ursulin __u32 rsvd; 1614e46c2e99STvrtko Ursulin }; 1615e46c2e99STvrtko Ursulin 16166d06779eSChris Wilson /* 16176d06779eSChris Wilson * i915_context_engines_load_balance: 16186d06779eSChris Wilson * 16196d06779eSChris Wilson * Enable load balancing across this set of engines. 16206d06779eSChris Wilson * 16216d06779eSChris Wilson * Into the I915_EXEC_DEFAULT slot [0], a virtual engine is created that when 16226d06779eSChris Wilson * used will proxy the execbuffer request onto one of the set of engines 16236d06779eSChris Wilson * in such a way as to distribute the load evenly across the set. 16246d06779eSChris Wilson * 16256d06779eSChris Wilson * The set of engines must be compatible (e.g. the same HW class) as they 16266d06779eSChris Wilson * will share the same logical GPU context and ring. 16276d06779eSChris Wilson * 16286d06779eSChris Wilson * To intermix rendering with the virtual engine and direct rendering onto 16296d06779eSChris Wilson * the backing engines (bypassing the load balancing proxy), the context must 16306d06779eSChris Wilson * be defined to use a single timeline for all engines. 16316d06779eSChris Wilson */ 16326d06779eSChris Wilson struct i915_context_engines_load_balance { 16336d06779eSChris Wilson struct i915_user_extension base; 16346d06779eSChris Wilson 16356d06779eSChris Wilson __u16 engine_index; 16366d06779eSChris Wilson __u16 num_siblings; 16376d06779eSChris Wilson __u32 flags; /* all undefined flags must be zero */ 16386d06779eSChris Wilson 16396d06779eSChris Wilson __u64 mbz64; /* reserved for future use; must be zero */ 16406d06779eSChris Wilson 16416d06779eSChris Wilson struct i915_engine_class_instance engines[0]; 16426d06779eSChris Wilson } __attribute__((packed)); 16436d06779eSChris Wilson 16446d06779eSChris Wilson #define I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(name__, N__) struct { \ 16456d06779eSChris Wilson struct i915_user_extension base; \ 16466d06779eSChris Wilson __u16 engine_index; \ 16476d06779eSChris Wilson __u16 num_siblings; \ 16486d06779eSChris Wilson __u32 flags; \ 16496d06779eSChris Wilson __u64 mbz64; \ 16506d06779eSChris Wilson struct i915_engine_class_instance engines[N__]; \ 16516d06779eSChris Wilson } __attribute__((packed)) name__ 16526d06779eSChris Wilson 1653ee113690SChris Wilson /* 1654ee113690SChris Wilson * i915_context_engines_bond: 1655ee113690SChris Wilson * 1656ee113690SChris Wilson * Constructed bonded pairs for execution within a virtual engine. 1657ee113690SChris Wilson * 1658ee113690SChris Wilson * All engines are equal, but some are more equal than others. Given 1659ee113690SChris Wilson * the distribution of resources in the HW, it may be preferable to run 1660ee113690SChris Wilson * a request on a given subset of engines in parallel to a request on a 1661ee113690SChris Wilson * specific engine. We enable this selection of engines within a virtual 1662ee113690SChris Wilson * engine by specifying bonding pairs, for any given master engine we will 1663ee113690SChris Wilson * only execute on one of the corresponding siblings within the virtual engine. 1664ee113690SChris Wilson * 1665ee113690SChris Wilson * To execute a request in parallel on the master engine and a sibling requires 1666ee113690SChris Wilson * coordination with a I915_EXEC_FENCE_SUBMIT. 1667ee113690SChris Wilson */ 1668ee113690SChris Wilson struct i915_context_engines_bond { 1669ee113690SChris Wilson struct i915_user_extension base; 1670ee113690SChris Wilson 1671ee113690SChris Wilson struct i915_engine_class_instance master; 1672ee113690SChris Wilson 1673ee113690SChris Wilson __u16 virtual_index; /* index of virtual engine in ctx->engines[] */ 1674ee113690SChris Wilson __u16 num_bonds; 1675ee113690SChris Wilson 1676ee113690SChris Wilson __u64 flags; /* all undefined flags must be zero */ 1677ee113690SChris Wilson __u64 mbz64[4]; /* reserved for future use; must be zero */ 1678ee113690SChris Wilson 1679ee113690SChris Wilson struct i915_engine_class_instance engines[0]; 1680ee113690SChris Wilson } __attribute__((packed)); 1681ee113690SChris Wilson 1682ee113690SChris Wilson #define I915_DEFINE_CONTEXT_ENGINES_BOND(name__, N__) struct { \ 1683ee113690SChris Wilson struct i915_user_extension base; \ 1684ee113690SChris Wilson struct i915_engine_class_instance master; \ 1685ee113690SChris Wilson __u16 virtual_index; \ 1686ee113690SChris Wilson __u16 num_bonds; \ 1687ee113690SChris Wilson __u64 flags; \ 1688ee113690SChris Wilson __u64 mbz64[4]; \ 1689ee113690SChris Wilson struct i915_engine_class_instance engines[N__]; \ 1690ee113690SChris Wilson } __attribute__((packed)) name__ 1691ee113690SChris Wilson 1692976b55f0SChris Wilson struct i915_context_param_engines { 1693976b55f0SChris Wilson __u64 extensions; /* linked chain of extension blocks, 0 terminates */ 16946d06779eSChris Wilson #define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */ 1695ee113690SChris Wilson #define I915_CONTEXT_ENGINES_EXT_BOND 1 /* see i915_context_engines_bond */ 1696976b55f0SChris Wilson struct i915_engine_class_instance engines[0]; 1697976b55f0SChris Wilson } __attribute__((packed)); 1698976b55f0SChris Wilson 1699976b55f0SChris Wilson #define I915_DEFINE_CONTEXT_PARAM_ENGINES(name__, N__) struct { \ 1700976b55f0SChris Wilson __u64 extensions; \ 1701976b55f0SChris Wilson struct i915_engine_class_instance engines[N__]; \ 1702976b55f0SChris Wilson } __attribute__((packed)) name__ 1703976b55f0SChris Wilson 1704b9171541SChris Wilson struct drm_i915_gem_context_create_ext_setparam { 1705b9171541SChris Wilson #define I915_CONTEXT_CREATE_EXT_SETPARAM 0 1706b9171541SChris Wilson struct i915_user_extension base; 1707b9171541SChris Wilson struct drm_i915_gem_context_param param; 1708b9171541SChris Wilson }; 1709b9171541SChris Wilson 1710b81dde71SChris Wilson struct drm_i915_gem_context_create_ext_clone { 1711b81dde71SChris Wilson #define I915_CONTEXT_CREATE_EXT_CLONE 1 1712b81dde71SChris Wilson struct i915_user_extension base; 1713b81dde71SChris Wilson __u32 clone_id; 1714b81dde71SChris Wilson __u32 flags; 1715b81dde71SChris Wilson #define I915_CONTEXT_CLONE_ENGINES (1u << 0) 1716b81dde71SChris Wilson #define I915_CONTEXT_CLONE_FLAGS (1u << 1) 1717b81dde71SChris Wilson #define I915_CONTEXT_CLONE_SCHEDATTR (1u << 2) 1718b81dde71SChris Wilson #define I915_CONTEXT_CLONE_SSEU (1u << 3) 1719b81dde71SChris Wilson #define I915_CONTEXT_CLONE_TIMELINE (1u << 4) 1720b81dde71SChris Wilson #define I915_CONTEXT_CLONE_VM (1u << 5) 1721b81dde71SChris Wilson #define I915_CONTEXT_CLONE_UNKNOWN -(I915_CONTEXT_CLONE_VM << 1) 1722b81dde71SChris Wilson __u64 rsvd; 1723b81dde71SChris Wilson }; 1724b81dde71SChris Wilson 1725b9171541SChris Wilson struct drm_i915_gem_context_destroy { 1726b9171541SChris Wilson __u32 ctx_id; 1727b9171541SChris Wilson __u32 pad; 1728b9171541SChris Wilson }; 1729b9171541SChris Wilson 1730b9171541SChris Wilson /* 1731b9171541SChris Wilson * DRM_I915_GEM_VM_CREATE - 1732b9171541SChris Wilson * 1733b9171541SChris Wilson * Create a new virtual memory address space (ppGTT) for use within a context 1734b9171541SChris Wilson * on the same file. Extensions can be provided to configure exactly how the 1735b9171541SChris Wilson * address space is setup upon creation. 1736b9171541SChris Wilson * 1737b9171541SChris Wilson * The id of new VM (bound to the fd) for use with I915_CONTEXT_PARAM_VM is 1738b9171541SChris Wilson * returned in the outparam @id. 1739b9171541SChris Wilson * 1740b9171541SChris Wilson * No flags are defined, with all bits reserved and must be zero. 1741b9171541SChris Wilson * 1742b9171541SChris Wilson * An extension chain maybe provided, starting with @extensions, and terminated 1743b9171541SChris Wilson * by the @next_extension being 0. Currently, no extensions are defined. 1744b9171541SChris Wilson * 1745b9171541SChris Wilson * DRM_I915_GEM_VM_DESTROY - 1746b9171541SChris Wilson * 1747b9171541SChris Wilson * Destroys a previously created VM id, specified in @id. 1748b9171541SChris Wilson * 1749b9171541SChris Wilson * No extensions or flags are allowed currently, and so must be zero. 1750b9171541SChris Wilson */ 1751b9171541SChris Wilson struct drm_i915_gem_vm_control { 1752b9171541SChris Wilson __u64 extensions; 1753b9171541SChris Wilson __u32 flags; 1754b9171541SChris Wilson __u32 vm_id; 1755b9171541SChris Wilson }; 1756b9171541SChris Wilson 1757b9171541SChris Wilson struct drm_i915_reg_read { 1758b9171541SChris Wilson /* 1759b9171541SChris Wilson * Register offset. 1760b9171541SChris Wilson * For 64bit wide registers where the upper 32bits don't immediately 1761b9171541SChris Wilson * follow the lower 32bits, the offset of the lower 32bits must 1762b9171541SChris Wilson * be specified 1763b9171541SChris Wilson */ 1764b9171541SChris Wilson __u64 offset; 1765b9171541SChris Wilson #define I915_REG_READ_8B_WA (1ul << 0) 1766b9171541SChris Wilson 1767b9171541SChris Wilson __u64 val; /* Return value */ 1768b9171541SChris Wilson }; 1769b9171541SChris Wilson 1770b9171541SChris Wilson /* Known registers: 1771b9171541SChris Wilson * 1772b9171541SChris Wilson * Render engine timestamp - 0x2358 + 64bit - gen7+ 1773b9171541SChris Wilson * - Note this register returns an invalid value if using the default 1774b9171541SChris Wilson * single instruction 8byte read, in order to workaround that pass 1775b9171541SChris Wilson * flag I915_REG_READ_8B_WA in offset field. 1776b9171541SChris Wilson * 1777b9171541SChris Wilson */ 1778b9171541SChris Wilson 1779b9171541SChris Wilson struct drm_i915_reset_stats { 1780b9171541SChris Wilson __u32 ctx_id; 1781b9171541SChris Wilson __u32 flags; 1782b9171541SChris Wilson 1783b9171541SChris Wilson /* All resets since boot/module reload, for all contexts */ 1784b9171541SChris Wilson __u32 reset_count; 1785b9171541SChris Wilson 1786b9171541SChris Wilson /* Number of batches lost when active in GPU, for this context */ 1787b9171541SChris Wilson __u32 batch_active; 1788b9171541SChris Wilson 1789b9171541SChris Wilson /* Number of batches lost pending for execution, for this context */ 1790b9171541SChris Wilson __u32 batch_pending; 1791b9171541SChris Wilson 1792b9171541SChris Wilson __u32 pad; 1793b9171541SChris Wilson }; 1794b9171541SChris Wilson 1795b9171541SChris Wilson struct drm_i915_gem_userptr { 1796b9171541SChris Wilson __u64 user_ptr; 1797b9171541SChris Wilson __u64 user_size; 1798b9171541SChris Wilson __u32 flags; 1799b9171541SChris Wilson #define I915_USERPTR_READ_ONLY 0x1 1800b9171541SChris Wilson #define I915_USERPTR_UNSYNCHRONIZED 0x80000000 1801b9171541SChris Wilson /** 1802b9171541SChris Wilson * Returned handle for the object. 1803b9171541SChris Wilson * 1804b9171541SChris Wilson * Object handles are nonzero. 1805b9171541SChris Wilson */ 1806b9171541SChris Wilson __u32 handle; 1807b9171541SChris Wilson }; 1808b9171541SChris Wilson 1809d7965152SRobert Bragg enum drm_i915_oa_format { 181019f81df2SRobert Bragg I915_OA_FORMAT_A13 = 1, /* HSW only */ 181119f81df2SRobert Bragg I915_OA_FORMAT_A29, /* HSW only */ 181219f81df2SRobert Bragg I915_OA_FORMAT_A13_B8_C8, /* HSW only */ 181319f81df2SRobert Bragg I915_OA_FORMAT_B4_C8, /* HSW only */ 181419f81df2SRobert Bragg I915_OA_FORMAT_A45_B8_C8, /* HSW only */ 181519f81df2SRobert Bragg I915_OA_FORMAT_B4_C8_A16, /* HSW only */ 181619f81df2SRobert Bragg I915_OA_FORMAT_C4_B8, /* HSW+ */ 181719f81df2SRobert Bragg 181819f81df2SRobert Bragg /* Gen8+ */ 181919f81df2SRobert Bragg I915_OA_FORMAT_A12, 182019f81df2SRobert Bragg I915_OA_FORMAT_A12_B8_C8, 182119f81df2SRobert Bragg I915_OA_FORMAT_A32u40_A4u32_B8_C8, 1822d7965152SRobert Bragg 1823d7965152SRobert Bragg I915_OA_FORMAT_MAX /* non-ABI */ 1824d7965152SRobert Bragg }; 1825d7965152SRobert Bragg 1826eec688e1SRobert Bragg enum drm_i915_perf_property_id { 1827eec688e1SRobert Bragg /** 1828eec688e1SRobert Bragg * Open the stream for a specific context handle (as used with 1829eec688e1SRobert Bragg * execbuffer2). A stream opened for a specific context this way 1830eec688e1SRobert Bragg * won't typically require root privileges. 1831eec688e1SRobert Bragg */ 1832eec688e1SRobert Bragg DRM_I915_PERF_PROP_CTX_HANDLE = 1, 1833eec688e1SRobert Bragg 1834d7965152SRobert Bragg /** 1835d7965152SRobert Bragg * A value of 1 requests the inclusion of raw OA unit reports as 1836d7965152SRobert Bragg * part of stream samples. 1837d7965152SRobert Bragg */ 1838d7965152SRobert Bragg DRM_I915_PERF_PROP_SAMPLE_OA, 1839d7965152SRobert Bragg 1840d7965152SRobert Bragg /** 1841d7965152SRobert Bragg * The value specifies which set of OA unit metrics should be 1842d7965152SRobert Bragg * be configured, defining the contents of any OA unit reports. 1843d7965152SRobert Bragg */ 1844d7965152SRobert Bragg DRM_I915_PERF_PROP_OA_METRICS_SET, 1845d7965152SRobert Bragg 1846d7965152SRobert Bragg /** 1847d7965152SRobert Bragg * The value specifies the size and layout of OA unit reports. 1848d7965152SRobert Bragg */ 1849d7965152SRobert Bragg DRM_I915_PERF_PROP_OA_FORMAT, 1850d7965152SRobert Bragg 1851d7965152SRobert Bragg /** 1852d7965152SRobert Bragg * Specifying this property implicitly requests periodic OA unit 1853d7965152SRobert Bragg * sampling and (at least on Haswell) the sampling frequency is derived 1854d7965152SRobert Bragg * from this exponent as follows: 1855d7965152SRobert Bragg * 1856d7965152SRobert Bragg * 80ns * 2^(period_exponent + 1) 1857d7965152SRobert Bragg */ 1858d7965152SRobert Bragg DRM_I915_PERF_PROP_OA_EXPONENT, 1859d7965152SRobert Bragg 1860eec688e1SRobert Bragg DRM_I915_PERF_PROP_MAX /* non-ABI */ 1861eec688e1SRobert Bragg }; 1862eec688e1SRobert Bragg 1863eec688e1SRobert Bragg struct drm_i915_perf_open_param { 1864eec688e1SRobert Bragg __u32 flags; 1865eec688e1SRobert Bragg #define I915_PERF_FLAG_FD_CLOEXEC (1<<0) 1866eec688e1SRobert Bragg #define I915_PERF_FLAG_FD_NONBLOCK (1<<1) 1867eec688e1SRobert Bragg #define I915_PERF_FLAG_DISABLED (1<<2) 1868eec688e1SRobert Bragg 1869eec688e1SRobert Bragg /** The number of u64 (id, value) pairs */ 1870eec688e1SRobert Bragg __u32 num_properties; 1871eec688e1SRobert Bragg 1872eec688e1SRobert Bragg /** 1873eec688e1SRobert Bragg * Pointer to array of u64 (id, value) pairs configuring the stream 1874eec688e1SRobert Bragg * to open. 1875eec688e1SRobert Bragg */ 1876cd8bddc4SChris Wilson __u64 properties_ptr; 1877eec688e1SRobert Bragg }; 1878eec688e1SRobert Bragg 1879d7965152SRobert Bragg /** 1880d7965152SRobert Bragg * Enable data capture for a stream that was either opened in a disabled state 1881d7965152SRobert Bragg * via I915_PERF_FLAG_DISABLED or was later disabled via 1882d7965152SRobert Bragg * I915_PERF_IOCTL_DISABLE. 1883d7965152SRobert Bragg * 1884d7965152SRobert Bragg * It is intended to be cheaper to disable and enable a stream than it may be 1885d7965152SRobert Bragg * to close and re-open a stream with the same configuration. 1886d7965152SRobert Bragg * 1887d7965152SRobert Bragg * It's undefined whether any pending data for the stream will be lost. 1888d7965152SRobert Bragg */ 1889eec688e1SRobert Bragg #define I915_PERF_IOCTL_ENABLE _IO('i', 0x0) 1890d7965152SRobert Bragg 1891d7965152SRobert Bragg /** 1892d7965152SRobert Bragg * Disable data capture for a stream. 1893d7965152SRobert Bragg * 1894d7965152SRobert Bragg * It is an error to try and read a stream that is disabled. 1895d7965152SRobert Bragg */ 1896eec688e1SRobert Bragg #define I915_PERF_IOCTL_DISABLE _IO('i', 0x1) 1897eec688e1SRobert Bragg 1898eec688e1SRobert Bragg /** 1899eec688e1SRobert Bragg * Common to all i915 perf records 1900eec688e1SRobert Bragg */ 1901eec688e1SRobert Bragg struct drm_i915_perf_record_header { 1902eec688e1SRobert Bragg __u32 type; 1903eec688e1SRobert Bragg __u16 pad; 1904eec688e1SRobert Bragg __u16 size; 1905eec688e1SRobert Bragg }; 1906eec688e1SRobert Bragg 1907eec688e1SRobert Bragg enum drm_i915_perf_record_type { 1908eec688e1SRobert Bragg 1909eec688e1SRobert Bragg /** 1910eec688e1SRobert Bragg * Samples are the work horse record type whose contents are extensible 1911eec688e1SRobert Bragg * and defined when opening an i915 perf stream based on the given 1912eec688e1SRobert Bragg * properties. 1913eec688e1SRobert Bragg * 1914eec688e1SRobert Bragg * Boolean properties following the naming convention 1915eec688e1SRobert Bragg * DRM_I915_PERF_SAMPLE_xyz_PROP request the inclusion of 'xyz' data in 1916eec688e1SRobert Bragg * every sample. 1917eec688e1SRobert Bragg * 1918eec688e1SRobert Bragg * The order of these sample properties given by userspace has no 1919d7965152SRobert Bragg * affect on the ordering of data within a sample. The order is 1920eec688e1SRobert Bragg * documented here. 1921eec688e1SRobert Bragg * 1922eec688e1SRobert Bragg * struct { 1923eec688e1SRobert Bragg * struct drm_i915_perf_record_header header; 1924eec688e1SRobert Bragg * 1925d7965152SRobert Bragg * { u32 oa_report[]; } && DRM_I915_PERF_PROP_SAMPLE_OA 1926eec688e1SRobert Bragg * }; 1927eec688e1SRobert Bragg */ 1928eec688e1SRobert Bragg DRM_I915_PERF_RECORD_SAMPLE = 1, 1929eec688e1SRobert Bragg 1930d7965152SRobert Bragg /* 1931d7965152SRobert Bragg * Indicates that one or more OA reports were not written by the 1932d7965152SRobert Bragg * hardware. This can happen for example if an MI_REPORT_PERF_COUNT 1933d7965152SRobert Bragg * command collides with periodic sampling - which would be more likely 1934d7965152SRobert Bragg * at higher sampling frequencies. 1935d7965152SRobert Bragg */ 1936d7965152SRobert Bragg DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2, 1937d7965152SRobert Bragg 1938d7965152SRobert Bragg /** 1939d7965152SRobert Bragg * An error occurred that resulted in all pending OA reports being lost. 1940d7965152SRobert Bragg */ 1941d7965152SRobert Bragg DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3, 1942d7965152SRobert Bragg 1943eec688e1SRobert Bragg DRM_I915_PERF_RECORD_MAX /* non-ABI */ 1944eec688e1SRobert Bragg }; 1945eec688e1SRobert Bragg 1946f89823c2SLionel Landwerlin /** 1947f89823c2SLionel Landwerlin * Structure to upload perf dynamic configuration into the kernel. 1948f89823c2SLionel Landwerlin */ 1949f89823c2SLionel Landwerlin struct drm_i915_perf_oa_config { 1950f89823c2SLionel Landwerlin /** String formatted like "%08x-%04x-%04x-%04x-%012x" */ 1951f89823c2SLionel Landwerlin char uuid[36]; 1952f89823c2SLionel Landwerlin 1953f89823c2SLionel Landwerlin __u32 n_mux_regs; 1954f89823c2SLionel Landwerlin __u32 n_boolean_regs; 1955f89823c2SLionel Landwerlin __u32 n_flex_regs; 1956f89823c2SLionel Landwerlin 1957ee427e25SLionel Landwerlin /* 1958a446ae2cSLionel Landwerlin * These fields are pointers to tuples of u32 values (register address, 1959a446ae2cSLionel Landwerlin * value). For example the expected length of the buffer pointed by 1960a446ae2cSLionel Landwerlin * mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs). 1961ee427e25SLionel Landwerlin */ 196217ad4fddSChris Wilson __u64 mux_regs_ptr; 196317ad4fddSChris Wilson __u64 boolean_regs_ptr; 196417ad4fddSChris Wilson __u64 flex_regs_ptr; 1965f89823c2SLionel Landwerlin }; 1966f89823c2SLionel Landwerlin 1967a446ae2cSLionel Landwerlin struct drm_i915_query_item { 1968a446ae2cSLionel Landwerlin __u64 query_id; 1969c822e059SLionel Landwerlin #define DRM_I915_QUERY_TOPOLOGY_INFO 1 1970be03564bSChris Wilson /* Must be kept compact -- no holes and well documented */ 1971a446ae2cSLionel Landwerlin 1972a446ae2cSLionel Landwerlin /* 1973a446ae2cSLionel Landwerlin * When set to zero by userspace, this is filled with the size of the 1974a446ae2cSLionel Landwerlin * data to be written at the data_ptr pointer. The kernel sets this 1975a446ae2cSLionel Landwerlin * value to a negative value to signal an error on a particular query 1976a446ae2cSLionel Landwerlin * item. 1977a446ae2cSLionel Landwerlin */ 1978a446ae2cSLionel Landwerlin __s32 length; 1979a446ae2cSLionel Landwerlin 1980a446ae2cSLionel Landwerlin /* 1981a446ae2cSLionel Landwerlin * Unused for now. Must be cleared to zero. 1982a446ae2cSLionel Landwerlin */ 1983a446ae2cSLionel Landwerlin __u32 flags; 1984a446ae2cSLionel Landwerlin 1985a446ae2cSLionel Landwerlin /* 1986a446ae2cSLionel Landwerlin * Data will be written at the location pointed by data_ptr when the 1987a446ae2cSLionel Landwerlin * value of length matches the length of the data to be written by the 1988a446ae2cSLionel Landwerlin * kernel. 1989a446ae2cSLionel Landwerlin */ 1990a446ae2cSLionel Landwerlin __u64 data_ptr; 1991a446ae2cSLionel Landwerlin }; 1992a446ae2cSLionel Landwerlin 1993a446ae2cSLionel Landwerlin struct drm_i915_query { 1994a446ae2cSLionel Landwerlin __u32 num_items; 1995a446ae2cSLionel Landwerlin 1996a446ae2cSLionel Landwerlin /* 1997a446ae2cSLionel Landwerlin * Unused for now. Must be cleared to zero. 1998a446ae2cSLionel Landwerlin */ 1999a446ae2cSLionel Landwerlin __u32 flags; 2000a446ae2cSLionel Landwerlin 2001a446ae2cSLionel Landwerlin /* 2002a446ae2cSLionel Landwerlin * This points to an array of num_items drm_i915_query_item structures. 2003a446ae2cSLionel Landwerlin */ 2004a446ae2cSLionel Landwerlin __u64 items_ptr; 2005a446ae2cSLionel Landwerlin }; 2006a446ae2cSLionel Landwerlin 2007c822e059SLionel Landwerlin /* 2008c822e059SLionel Landwerlin * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO : 2009c822e059SLionel Landwerlin * 2010c822e059SLionel Landwerlin * data: contains the 3 pieces of information : 2011c822e059SLionel Landwerlin * 2012c822e059SLionel Landwerlin * - the slice mask with one bit per slice telling whether a slice is 2013c822e059SLionel Landwerlin * available. The availability of slice X can be queried with the following 2014c822e059SLionel Landwerlin * formula : 2015c822e059SLionel Landwerlin * 2016c822e059SLionel Landwerlin * (data[X / 8] >> (X % 8)) & 1 2017c822e059SLionel Landwerlin * 2018c822e059SLionel Landwerlin * - the subslice mask for each slice with one bit per subslice telling 2019c822e059SLionel Landwerlin * whether a subslice is available. The availability of subslice Y in slice 2020c822e059SLionel Landwerlin * X can be queried with the following formula : 2021c822e059SLionel Landwerlin * 2022c822e059SLionel Landwerlin * (data[subslice_offset + 2023c822e059SLionel Landwerlin * X * subslice_stride + 2024c822e059SLionel Landwerlin * Y / 8] >> (Y % 8)) & 1 2025c822e059SLionel Landwerlin * 2026c822e059SLionel Landwerlin * - the EU mask for each subslice in each slice with one bit per EU telling 2027c822e059SLionel Landwerlin * whether an EU is available. The availability of EU Z in subslice Y in 2028c822e059SLionel Landwerlin * slice X can be queried with the following formula : 2029c822e059SLionel Landwerlin * 2030c822e059SLionel Landwerlin * (data[eu_offset + 2031c822e059SLionel Landwerlin * (X * max_subslices + Y) * eu_stride + 2032c822e059SLionel Landwerlin * Z / 8] >> (Z % 8)) & 1 2033c822e059SLionel Landwerlin */ 2034c822e059SLionel Landwerlin struct drm_i915_query_topology_info { 2035c822e059SLionel Landwerlin /* 2036c822e059SLionel Landwerlin * Unused for now. Must be cleared to zero. 2037c822e059SLionel Landwerlin */ 2038c822e059SLionel Landwerlin __u16 flags; 2039c822e059SLionel Landwerlin 2040c822e059SLionel Landwerlin __u16 max_slices; 2041c822e059SLionel Landwerlin __u16 max_subslices; 2042c822e059SLionel Landwerlin __u16 max_eus_per_subslice; 2043c822e059SLionel Landwerlin 2044c822e059SLionel Landwerlin /* 2045c822e059SLionel Landwerlin * Offset in data[] at which the subslice masks are stored. 2046c822e059SLionel Landwerlin */ 2047c822e059SLionel Landwerlin __u16 subslice_offset; 2048c822e059SLionel Landwerlin 2049c822e059SLionel Landwerlin /* 2050c822e059SLionel Landwerlin * Stride at which each of the subslice masks for each slice are 2051c822e059SLionel Landwerlin * stored. 2052c822e059SLionel Landwerlin */ 2053c822e059SLionel Landwerlin __u16 subslice_stride; 2054c822e059SLionel Landwerlin 2055c822e059SLionel Landwerlin /* 2056c822e059SLionel Landwerlin * Offset in data[] at which the EU masks are stored. 2057c822e059SLionel Landwerlin */ 2058c822e059SLionel Landwerlin __u16 eu_offset; 2059c822e059SLionel Landwerlin 2060c822e059SLionel Landwerlin /* 2061c822e059SLionel Landwerlin * Stride at which each of the EU masks for each subslice are stored. 2062c822e059SLionel Landwerlin */ 2063c822e059SLionel Landwerlin __u16 eu_stride; 2064c822e059SLionel Landwerlin 2065c822e059SLionel Landwerlin __u8 data[]; 2066c822e059SLionel Landwerlin }; 2067c822e059SLionel Landwerlin 2068b1c1f5c4SEmil Velikov #if defined(__cplusplus) 2069b1c1f5c4SEmil Velikov } 2070b1c1f5c4SEmil Velikov #endif 2071b1c1f5c4SEmil Velikov 2072718dceddSDavid Howells #endif /* _UAPI_I915_DRM_H_ */ 2073