1718dceddSDavid Howells /* 2718dceddSDavid Howells * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 3718dceddSDavid Howells * All Rights Reserved. 4718dceddSDavid Howells * 5718dceddSDavid Howells * Permission is hereby granted, free of charge, to any person obtaining a 6718dceddSDavid Howells * copy of this software and associated documentation files (the 7718dceddSDavid Howells * "Software"), to deal in the Software without restriction, including 8718dceddSDavid Howells * without limitation the rights to use, copy, modify, merge, publish, 9718dceddSDavid Howells * distribute, sub license, and/or sell copies of the Software, and to 10718dceddSDavid Howells * permit persons to whom the Software is furnished to do so, subject to 11718dceddSDavid Howells * the following conditions: 12718dceddSDavid Howells * 13718dceddSDavid Howells * The above copyright notice and this permission notice (including the 14718dceddSDavid Howells * next paragraph) shall be included in all copies or substantial portions 15718dceddSDavid Howells * of the Software. 16718dceddSDavid Howells * 17718dceddSDavid Howells * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18718dceddSDavid Howells * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19718dceddSDavid Howells * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20718dceddSDavid Howells * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 21718dceddSDavid Howells * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22718dceddSDavid Howells * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23718dceddSDavid Howells * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24718dceddSDavid Howells * 25718dceddSDavid Howells */ 26718dceddSDavid Howells 27718dceddSDavid Howells #ifndef _UAPI_I915_DRM_H_ 28718dceddSDavid Howells #define _UAPI_I915_DRM_H_ 29718dceddSDavid Howells 30718dceddSDavid Howells #include <drm/drm.h> 31718dceddSDavid Howells 32718dceddSDavid Howells /* Please note that modifications to all structs defined here are 33718dceddSDavid Howells * subject to backwards-compatibility constraints. 34718dceddSDavid Howells */ 35718dceddSDavid Howells 36cce723edSBen Widawsky /** 37cce723edSBen Widawsky * DOC: uevents generated by i915 on it's device node 38cce723edSBen Widawsky * 39cce723edSBen Widawsky * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch 40cce723edSBen Widawsky * event from the gpu l3 cache. Additional information supplied is ROW, 4135a85ac6SBen Widawsky * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep 4235a85ac6SBen Widawsky * track of these events and if a specific cache-line seems to have a 4335a85ac6SBen Widawsky * persistent error remap it with the l3 remapping tool supplied in 4435a85ac6SBen Widawsky * intel-gpu-tools. The value supplied with the event is always 1. 45cce723edSBen Widawsky * 46cce723edSBen Widawsky * I915_ERROR_UEVENT - Generated upon error detection, currently only via 47cce723edSBen Widawsky * hangcheck. The error detection event is a good indicator of when things 48cce723edSBen Widawsky * began to go badly. The value supplied with the event is a 1 upon error 49cce723edSBen Widawsky * detection, and a 0 upon reset completion, signifying no more error 50cce723edSBen Widawsky * exists. NOTE: Disabling hangcheck or reset via module parameter will 51cce723edSBen Widawsky * cause the related events to not be seen. 52cce723edSBen Widawsky * 53cce723edSBen Widawsky * I915_RESET_UEVENT - Event is generated just before an attempt to reset the 54cce723edSBen Widawsky * the GPU. The value supplied with the event is always 1. NOTE: Disable 55cce723edSBen Widawsky * reset via module parameter will cause this event to not be seen. 56cce723edSBen Widawsky */ 57cce723edSBen Widawsky #define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR" 58cce723edSBen Widawsky #define I915_ERROR_UEVENT "ERROR" 59cce723edSBen Widawsky #define I915_RESET_UEVENT "RESET" 60718dceddSDavid Howells 61718dceddSDavid Howells /* Each region is a minimum of 16k, and there are at most 255 of them. 62718dceddSDavid Howells */ 63718dceddSDavid Howells #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use 64718dceddSDavid Howells * of chars for next/prev indices */ 65718dceddSDavid Howells #define I915_LOG_MIN_TEX_REGION_SIZE 14 66718dceddSDavid Howells 67718dceddSDavid Howells typedef struct _drm_i915_init { 68718dceddSDavid Howells enum { 69718dceddSDavid Howells I915_INIT_DMA = 0x01, 70718dceddSDavid Howells I915_CLEANUP_DMA = 0x02, 71718dceddSDavid Howells I915_RESUME_DMA = 0x03 72718dceddSDavid Howells } func; 73718dceddSDavid Howells unsigned int mmio_offset; 74718dceddSDavid Howells int sarea_priv_offset; 75718dceddSDavid Howells unsigned int ring_start; 76718dceddSDavid Howells unsigned int ring_end; 77718dceddSDavid Howells unsigned int ring_size; 78718dceddSDavid Howells unsigned int front_offset; 79718dceddSDavid Howells unsigned int back_offset; 80718dceddSDavid Howells unsigned int depth_offset; 81718dceddSDavid Howells unsigned int w; 82718dceddSDavid Howells unsigned int h; 83718dceddSDavid Howells unsigned int pitch; 84718dceddSDavid Howells unsigned int pitch_bits; 85718dceddSDavid Howells unsigned int back_pitch; 86718dceddSDavid Howells unsigned int depth_pitch; 87718dceddSDavid Howells unsigned int cpp; 88718dceddSDavid Howells unsigned int chipset; 89718dceddSDavid Howells } drm_i915_init_t; 90718dceddSDavid Howells 91718dceddSDavid Howells typedef struct _drm_i915_sarea { 92718dceddSDavid Howells struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 93718dceddSDavid Howells int last_upload; /* last time texture was uploaded */ 94718dceddSDavid Howells int last_enqueue; /* last time a buffer was enqueued */ 95718dceddSDavid Howells int last_dispatch; /* age of the most recently dispatched buffer */ 96718dceddSDavid Howells int ctxOwner; /* last context to upload state */ 97718dceddSDavid Howells int texAge; 98718dceddSDavid Howells int pf_enabled; /* is pageflipping allowed? */ 99718dceddSDavid Howells int pf_active; 100718dceddSDavid Howells int pf_current_page; /* which buffer is being displayed? */ 101718dceddSDavid Howells int perf_boxes; /* performance boxes to be displayed */ 102718dceddSDavid Howells int width, height; /* screen size in pixels */ 103718dceddSDavid Howells 104718dceddSDavid Howells drm_handle_t front_handle; 105718dceddSDavid Howells int front_offset; 106718dceddSDavid Howells int front_size; 107718dceddSDavid Howells 108718dceddSDavid Howells drm_handle_t back_handle; 109718dceddSDavid Howells int back_offset; 110718dceddSDavid Howells int back_size; 111718dceddSDavid Howells 112718dceddSDavid Howells drm_handle_t depth_handle; 113718dceddSDavid Howells int depth_offset; 114718dceddSDavid Howells int depth_size; 115718dceddSDavid Howells 116718dceddSDavid Howells drm_handle_t tex_handle; 117718dceddSDavid Howells int tex_offset; 118718dceddSDavid Howells int tex_size; 119718dceddSDavid Howells int log_tex_granularity; 120718dceddSDavid Howells int pitch; 121718dceddSDavid Howells int rotation; /* 0, 90, 180 or 270 */ 122718dceddSDavid Howells int rotated_offset; 123718dceddSDavid Howells int rotated_size; 124718dceddSDavid Howells int rotated_pitch; 125718dceddSDavid Howells int virtualX, virtualY; 126718dceddSDavid Howells 127718dceddSDavid Howells unsigned int front_tiled; 128718dceddSDavid Howells unsigned int back_tiled; 129718dceddSDavid Howells unsigned int depth_tiled; 130718dceddSDavid Howells unsigned int rotated_tiled; 131718dceddSDavid Howells unsigned int rotated2_tiled; 132718dceddSDavid Howells 133718dceddSDavid Howells int pipeA_x; 134718dceddSDavid Howells int pipeA_y; 135718dceddSDavid Howells int pipeA_w; 136718dceddSDavid Howells int pipeA_h; 137718dceddSDavid Howells int pipeB_x; 138718dceddSDavid Howells int pipeB_y; 139718dceddSDavid Howells int pipeB_w; 140718dceddSDavid Howells int pipeB_h; 141718dceddSDavid Howells 142718dceddSDavid Howells /* fill out some space for old userspace triple buffer */ 143718dceddSDavid Howells drm_handle_t unused_handle; 144718dceddSDavid Howells __u32 unused1, unused2, unused3; 145718dceddSDavid Howells 146718dceddSDavid Howells /* buffer object handles for static buffers. May change 147718dceddSDavid Howells * over the lifetime of the client. 148718dceddSDavid Howells */ 149718dceddSDavid Howells __u32 front_bo_handle; 150718dceddSDavid Howells __u32 back_bo_handle; 151718dceddSDavid Howells __u32 unused_bo_handle; 152718dceddSDavid Howells __u32 depth_bo_handle; 153718dceddSDavid Howells 154718dceddSDavid Howells } drm_i915_sarea_t; 155718dceddSDavid Howells 156718dceddSDavid Howells /* due to userspace building against these headers we need some compat here */ 157718dceddSDavid Howells #define planeA_x pipeA_x 158718dceddSDavid Howells #define planeA_y pipeA_y 159718dceddSDavid Howells #define planeA_w pipeA_w 160718dceddSDavid Howells #define planeA_h pipeA_h 161718dceddSDavid Howells #define planeB_x pipeB_x 162718dceddSDavid Howells #define planeB_y pipeB_y 163718dceddSDavid Howells #define planeB_w pipeB_w 164718dceddSDavid Howells #define planeB_h pipeB_h 165718dceddSDavid Howells 166718dceddSDavid Howells /* Flags for perf_boxes 167718dceddSDavid Howells */ 168718dceddSDavid Howells #define I915_BOX_RING_EMPTY 0x1 169718dceddSDavid Howells #define I915_BOX_FLIP 0x2 170718dceddSDavid Howells #define I915_BOX_WAIT 0x4 171718dceddSDavid Howells #define I915_BOX_TEXTURE_LOAD 0x8 172718dceddSDavid Howells #define I915_BOX_LOST_CONTEXT 0x10 173718dceddSDavid Howells 174718dceddSDavid Howells /* I915 specific ioctls 175718dceddSDavid Howells * The device specific ioctl range is 0x40 to 0x79. 176718dceddSDavid Howells */ 177718dceddSDavid Howells #define DRM_I915_INIT 0x00 178718dceddSDavid Howells #define DRM_I915_FLUSH 0x01 179718dceddSDavid Howells #define DRM_I915_FLIP 0x02 180718dceddSDavid Howells #define DRM_I915_BATCHBUFFER 0x03 181718dceddSDavid Howells #define DRM_I915_IRQ_EMIT 0x04 182718dceddSDavid Howells #define DRM_I915_IRQ_WAIT 0x05 183718dceddSDavid Howells #define DRM_I915_GETPARAM 0x06 184718dceddSDavid Howells #define DRM_I915_SETPARAM 0x07 185718dceddSDavid Howells #define DRM_I915_ALLOC 0x08 186718dceddSDavid Howells #define DRM_I915_FREE 0x09 187718dceddSDavid Howells #define DRM_I915_INIT_HEAP 0x0a 188718dceddSDavid Howells #define DRM_I915_CMDBUFFER 0x0b 189718dceddSDavid Howells #define DRM_I915_DESTROY_HEAP 0x0c 190718dceddSDavid Howells #define DRM_I915_SET_VBLANK_PIPE 0x0d 191718dceddSDavid Howells #define DRM_I915_GET_VBLANK_PIPE 0x0e 192718dceddSDavid Howells #define DRM_I915_VBLANK_SWAP 0x0f 193718dceddSDavid Howells #define DRM_I915_HWS_ADDR 0x11 194718dceddSDavid Howells #define DRM_I915_GEM_INIT 0x13 195718dceddSDavid Howells #define DRM_I915_GEM_EXECBUFFER 0x14 196718dceddSDavid Howells #define DRM_I915_GEM_PIN 0x15 197718dceddSDavid Howells #define DRM_I915_GEM_UNPIN 0x16 198718dceddSDavid Howells #define DRM_I915_GEM_BUSY 0x17 199718dceddSDavid Howells #define DRM_I915_GEM_THROTTLE 0x18 200718dceddSDavid Howells #define DRM_I915_GEM_ENTERVT 0x19 201718dceddSDavid Howells #define DRM_I915_GEM_LEAVEVT 0x1a 202718dceddSDavid Howells #define DRM_I915_GEM_CREATE 0x1b 203718dceddSDavid Howells #define DRM_I915_GEM_PREAD 0x1c 204718dceddSDavid Howells #define DRM_I915_GEM_PWRITE 0x1d 205718dceddSDavid Howells #define DRM_I915_GEM_MMAP 0x1e 206718dceddSDavid Howells #define DRM_I915_GEM_SET_DOMAIN 0x1f 207718dceddSDavid Howells #define DRM_I915_GEM_SW_FINISH 0x20 208718dceddSDavid Howells #define DRM_I915_GEM_SET_TILING 0x21 209718dceddSDavid Howells #define DRM_I915_GEM_GET_TILING 0x22 210718dceddSDavid Howells #define DRM_I915_GEM_GET_APERTURE 0x23 211718dceddSDavid Howells #define DRM_I915_GEM_MMAP_GTT 0x24 212718dceddSDavid Howells #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 213718dceddSDavid Howells #define DRM_I915_GEM_MADVISE 0x26 214718dceddSDavid Howells #define DRM_I915_OVERLAY_PUT_IMAGE 0x27 215718dceddSDavid Howells #define DRM_I915_OVERLAY_ATTRS 0x28 216718dceddSDavid Howells #define DRM_I915_GEM_EXECBUFFER2 0x29 217718dceddSDavid Howells #define DRM_I915_GET_SPRITE_COLORKEY 0x2a 218718dceddSDavid Howells #define DRM_I915_SET_SPRITE_COLORKEY 0x2b 219718dceddSDavid Howells #define DRM_I915_GEM_WAIT 0x2c 220718dceddSDavid Howells #define DRM_I915_GEM_CONTEXT_CREATE 0x2d 221718dceddSDavid Howells #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e 222718dceddSDavid Howells #define DRM_I915_GEM_SET_CACHING 0x2f 223718dceddSDavid Howells #define DRM_I915_GEM_GET_CACHING 0x30 224718dceddSDavid Howells #define DRM_I915_REG_READ 0x31 225b6359918SMika Kuoppala #define DRM_I915_GET_RESET_STATS 0x32 226718dceddSDavid Howells 227718dceddSDavid Howells #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 228718dceddSDavid Howells #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 229718dceddSDavid Howells #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) 230718dceddSDavid Howells #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 231718dceddSDavid Howells #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 232718dceddSDavid Howells #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 233718dceddSDavid Howells #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 234718dceddSDavid Howells #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 235718dceddSDavid Howells #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 236718dceddSDavid Howells #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 237718dceddSDavid Howells #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 238718dceddSDavid Howells #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 239718dceddSDavid Howells #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 240718dceddSDavid Howells #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 241718dceddSDavid Howells #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 242718dceddSDavid Howells #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 243718dceddSDavid Howells #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) 244718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 245718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 246718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 247718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 248718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 249718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 250718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) 251718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) 252718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 253718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 254718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 255718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 256718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 257718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 258718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 259718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 260718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 261718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 262718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 263718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 264718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 265718dceddSDavid Howells #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 266718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 267718dceddSDavid Howells #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) 268718dceddSDavid Howells #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 269718dceddSDavid Howells #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 270718dceddSDavid Howells #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 271718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) 272718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) 273718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) 274718dceddSDavid Howells #define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) 275b6359918SMika Kuoppala #define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats) 276718dceddSDavid Howells 277718dceddSDavid Howells /* Allow drivers to submit batchbuffers directly to hardware, relying 278718dceddSDavid Howells * on the security mechanisms provided by hardware. 279718dceddSDavid Howells */ 280718dceddSDavid Howells typedef struct drm_i915_batchbuffer { 281718dceddSDavid Howells int start; /* agp offset */ 282718dceddSDavid Howells int used; /* nr bytes in use */ 283718dceddSDavid Howells int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 284718dceddSDavid Howells int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 285718dceddSDavid Howells int num_cliprects; /* mulitpass with multiple cliprects? */ 286718dceddSDavid Howells struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 287718dceddSDavid Howells } drm_i915_batchbuffer_t; 288718dceddSDavid Howells 289718dceddSDavid Howells /* As above, but pass a pointer to userspace buffer which can be 290718dceddSDavid Howells * validated by the kernel prior to sending to hardware. 291718dceddSDavid Howells */ 292718dceddSDavid Howells typedef struct _drm_i915_cmdbuffer { 293718dceddSDavid Howells char __user *buf; /* pointer to userspace command buffer */ 294718dceddSDavid Howells int sz; /* nr bytes in buf */ 295718dceddSDavid Howells int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 296718dceddSDavid Howells int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 297718dceddSDavid Howells int num_cliprects; /* mulitpass with multiple cliprects? */ 298718dceddSDavid Howells struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 299718dceddSDavid Howells } drm_i915_cmdbuffer_t; 300718dceddSDavid Howells 301718dceddSDavid Howells /* Userspace can request & wait on irq's: 302718dceddSDavid Howells */ 303718dceddSDavid Howells typedef struct drm_i915_irq_emit { 304718dceddSDavid Howells int __user *irq_seq; 305718dceddSDavid Howells } drm_i915_irq_emit_t; 306718dceddSDavid Howells 307718dceddSDavid Howells typedef struct drm_i915_irq_wait { 308718dceddSDavid Howells int irq_seq; 309718dceddSDavid Howells } drm_i915_irq_wait_t; 310718dceddSDavid Howells 311718dceddSDavid Howells /* Ioctl to query kernel params: 312718dceddSDavid Howells */ 313718dceddSDavid Howells #define I915_PARAM_IRQ_ACTIVE 1 314718dceddSDavid Howells #define I915_PARAM_ALLOW_BATCHBUFFER 2 315718dceddSDavid Howells #define I915_PARAM_LAST_DISPATCH 3 316718dceddSDavid Howells #define I915_PARAM_CHIPSET_ID 4 317718dceddSDavid Howells #define I915_PARAM_HAS_GEM 5 318718dceddSDavid Howells #define I915_PARAM_NUM_FENCES_AVAIL 6 319718dceddSDavid Howells #define I915_PARAM_HAS_OVERLAY 7 320718dceddSDavid Howells #define I915_PARAM_HAS_PAGEFLIPPING 8 321718dceddSDavid Howells #define I915_PARAM_HAS_EXECBUF2 9 322718dceddSDavid Howells #define I915_PARAM_HAS_BSD 10 323718dceddSDavid Howells #define I915_PARAM_HAS_BLT 11 324718dceddSDavid Howells #define I915_PARAM_HAS_RELAXED_FENCING 12 325718dceddSDavid Howells #define I915_PARAM_HAS_COHERENT_RINGS 13 326718dceddSDavid Howells #define I915_PARAM_HAS_EXEC_CONSTANTS 14 327718dceddSDavid Howells #define I915_PARAM_HAS_RELAXED_DELTA 15 328718dceddSDavid Howells #define I915_PARAM_HAS_GEN7_SOL_RESET 16 329718dceddSDavid Howells #define I915_PARAM_HAS_LLC 17 330718dceddSDavid Howells #define I915_PARAM_HAS_ALIASING_PPGTT 18 331718dceddSDavid Howells #define I915_PARAM_HAS_WAIT_TIMEOUT 19 332718dceddSDavid Howells #define I915_PARAM_HAS_SEMAPHORES 20 333718dceddSDavid Howells #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 334a1f2cc73SXiang, Haihao #define I915_PARAM_HAS_VEBOX 22 335c2fb7916SDaniel Vetter #define I915_PARAM_HAS_SECURE_BATCHES 23 336b45305fcSDaniel Vetter #define I915_PARAM_HAS_PINNED_BATCHES 24 337ed5982e6SDaniel Vetter #define I915_PARAM_HAS_EXEC_NO_RELOC 25 338eef90ccbSChris Wilson #define I915_PARAM_HAS_EXEC_HANDLE_LUT 26 339651d794fSChris Wilson #define I915_PARAM_HAS_WT 27 340d728c8efSBrad Volkin #define I915_PARAM_CMD_PARSER_VERSION 28 341718dceddSDavid Howells 342718dceddSDavid Howells typedef struct drm_i915_getparam { 343718dceddSDavid Howells int param; 344718dceddSDavid Howells int __user *value; 345718dceddSDavid Howells } drm_i915_getparam_t; 346718dceddSDavid Howells 347718dceddSDavid Howells /* Ioctl to set kernel params: 348718dceddSDavid Howells */ 349718dceddSDavid Howells #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 350718dceddSDavid Howells #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 351718dceddSDavid Howells #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 352718dceddSDavid Howells #define I915_SETPARAM_NUM_USED_FENCES 4 353718dceddSDavid Howells 354718dceddSDavid Howells typedef struct drm_i915_setparam { 355718dceddSDavid Howells int param; 356718dceddSDavid Howells int value; 357718dceddSDavid Howells } drm_i915_setparam_t; 358718dceddSDavid Howells 359718dceddSDavid Howells /* A memory manager for regions of shared memory: 360718dceddSDavid Howells */ 361718dceddSDavid Howells #define I915_MEM_REGION_AGP 1 362718dceddSDavid Howells 363718dceddSDavid Howells typedef struct drm_i915_mem_alloc { 364718dceddSDavid Howells int region; 365718dceddSDavid Howells int alignment; 366718dceddSDavid Howells int size; 367718dceddSDavid Howells int __user *region_offset; /* offset from start of fb or agp */ 368718dceddSDavid Howells } drm_i915_mem_alloc_t; 369718dceddSDavid Howells 370718dceddSDavid Howells typedef struct drm_i915_mem_free { 371718dceddSDavid Howells int region; 372718dceddSDavid Howells int region_offset; 373718dceddSDavid Howells } drm_i915_mem_free_t; 374718dceddSDavid Howells 375718dceddSDavid Howells typedef struct drm_i915_mem_init_heap { 376718dceddSDavid Howells int region; 377718dceddSDavid Howells int size; 378718dceddSDavid Howells int start; 379718dceddSDavid Howells } drm_i915_mem_init_heap_t; 380718dceddSDavid Howells 381718dceddSDavid Howells /* Allow memory manager to be torn down and re-initialized (eg on 382718dceddSDavid Howells * rotate): 383718dceddSDavid Howells */ 384718dceddSDavid Howells typedef struct drm_i915_mem_destroy_heap { 385718dceddSDavid Howells int region; 386718dceddSDavid Howells } drm_i915_mem_destroy_heap_t; 387718dceddSDavid Howells 388718dceddSDavid Howells /* Allow X server to configure which pipes to monitor for vblank signals 389718dceddSDavid Howells */ 390718dceddSDavid Howells #define DRM_I915_VBLANK_PIPE_A 1 391718dceddSDavid Howells #define DRM_I915_VBLANK_PIPE_B 2 392718dceddSDavid Howells 393718dceddSDavid Howells typedef struct drm_i915_vblank_pipe { 394718dceddSDavid Howells int pipe; 395718dceddSDavid Howells } drm_i915_vblank_pipe_t; 396718dceddSDavid Howells 397718dceddSDavid Howells /* Schedule buffer swap at given vertical blank: 398718dceddSDavid Howells */ 399718dceddSDavid Howells typedef struct drm_i915_vblank_swap { 400718dceddSDavid Howells drm_drawable_t drawable; 401718dceddSDavid Howells enum drm_vblank_seq_type seqtype; 402718dceddSDavid Howells unsigned int sequence; 403718dceddSDavid Howells } drm_i915_vblank_swap_t; 404718dceddSDavid Howells 405718dceddSDavid Howells typedef struct drm_i915_hws_addr { 406718dceddSDavid Howells __u64 addr; 407718dceddSDavid Howells } drm_i915_hws_addr_t; 408718dceddSDavid Howells 409718dceddSDavid Howells struct drm_i915_gem_init { 410718dceddSDavid Howells /** 411718dceddSDavid Howells * Beginning offset in the GTT to be managed by the DRM memory 412718dceddSDavid Howells * manager. 413718dceddSDavid Howells */ 414718dceddSDavid Howells __u64 gtt_start; 415718dceddSDavid Howells /** 416718dceddSDavid Howells * Ending offset in the GTT to be managed by the DRM memory 417718dceddSDavid Howells * manager. 418718dceddSDavid Howells */ 419718dceddSDavid Howells __u64 gtt_end; 420718dceddSDavid Howells }; 421718dceddSDavid Howells 422718dceddSDavid Howells struct drm_i915_gem_create { 423718dceddSDavid Howells /** 424718dceddSDavid Howells * Requested size for the object. 425718dceddSDavid Howells * 426718dceddSDavid Howells * The (page-aligned) allocated size for the object will be returned. 427718dceddSDavid Howells */ 428718dceddSDavid Howells __u64 size; 429718dceddSDavid Howells /** 430718dceddSDavid Howells * Returned handle for the object. 431718dceddSDavid Howells * 432718dceddSDavid Howells * Object handles are nonzero. 433718dceddSDavid Howells */ 434718dceddSDavid Howells __u32 handle; 435718dceddSDavid Howells __u32 pad; 436718dceddSDavid Howells }; 437718dceddSDavid Howells 438718dceddSDavid Howells struct drm_i915_gem_pread { 439718dceddSDavid Howells /** Handle for the object being read. */ 440718dceddSDavid Howells __u32 handle; 441718dceddSDavid Howells __u32 pad; 442718dceddSDavid Howells /** Offset into the object to read from */ 443718dceddSDavid Howells __u64 offset; 444718dceddSDavid Howells /** Length of data to read */ 445718dceddSDavid Howells __u64 size; 446718dceddSDavid Howells /** 447718dceddSDavid Howells * Pointer to write the data into. 448718dceddSDavid Howells * 449718dceddSDavid Howells * This is a fixed-size type for 32/64 compatibility. 450718dceddSDavid Howells */ 451718dceddSDavid Howells __u64 data_ptr; 452718dceddSDavid Howells }; 453718dceddSDavid Howells 454718dceddSDavid Howells struct drm_i915_gem_pwrite { 455718dceddSDavid Howells /** Handle for the object being written to. */ 456718dceddSDavid Howells __u32 handle; 457718dceddSDavid Howells __u32 pad; 458718dceddSDavid Howells /** Offset into the object to write to */ 459718dceddSDavid Howells __u64 offset; 460718dceddSDavid Howells /** Length of data to write */ 461718dceddSDavid Howells __u64 size; 462718dceddSDavid Howells /** 463718dceddSDavid Howells * Pointer to read the data from. 464718dceddSDavid Howells * 465718dceddSDavid Howells * This is a fixed-size type for 32/64 compatibility. 466718dceddSDavid Howells */ 467718dceddSDavid Howells __u64 data_ptr; 468718dceddSDavid Howells }; 469718dceddSDavid Howells 470718dceddSDavid Howells struct drm_i915_gem_mmap { 471718dceddSDavid Howells /** Handle for the object being mapped. */ 472718dceddSDavid Howells __u32 handle; 473718dceddSDavid Howells __u32 pad; 474718dceddSDavid Howells /** Offset in the object to map. */ 475718dceddSDavid Howells __u64 offset; 476718dceddSDavid Howells /** 477718dceddSDavid Howells * Length of data to map. 478718dceddSDavid Howells * 479718dceddSDavid Howells * The value will be page-aligned. 480718dceddSDavid Howells */ 481718dceddSDavid Howells __u64 size; 482718dceddSDavid Howells /** 483718dceddSDavid Howells * Returned pointer the data was mapped at. 484718dceddSDavid Howells * 485718dceddSDavid Howells * This is a fixed-size type for 32/64 compatibility. 486718dceddSDavid Howells */ 487718dceddSDavid Howells __u64 addr_ptr; 488718dceddSDavid Howells }; 489718dceddSDavid Howells 490718dceddSDavid Howells struct drm_i915_gem_mmap_gtt { 491718dceddSDavid Howells /** Handle for the object being mapped. */ 492718dceddSDavid Howells __u32 handle; 493718dceddSDavid Howells __u32 pad; 494718dceddSDavid Howells /** 495718dceddSDavid Howells * Fake offset to use for subsequent mmap call 496718dceddSDavid Howells * 497718dceddSDavid Howells * This is a fixed-size type for 32/64 compatibility. 498718dceddSDavid Howells */ 499718dceddSDavid Howells __u64 offset; 500718dceddSDavid Howells }; 501718dceddSDavid Howells 502718dceddSDavid Howells struct drm_i915_gem_set_domain { 503718dceddSDavid Howells /** Handle for the object */ 504718dceddSDavid Howells __u32 handle; 505718dceddSDavid Howells 506718dceddSDavid Howells /** New read domains */ 507718dceddSDavid Howells __u32 read_domains; 508718dceddSDavid Howells 509718dceddSDavid Howells /** New write domain */ 510718dceddSDavid Howells __u32 write_domain; 511718dceddSDavid Howells }; 512718dceddSDavid Howells 513718dceddSDavid Howells struct drm_i915_gem_sw_finish { 514718dceddSDavid Howells /** Handle for the object */ 515718dceddSDavid Howells __u32 handle; 516718dceddSDavid Howells }; 517718dceddSDavid Howells 518718dceddSDavid Howells struct drm_i915_gem_relocation_entry { 519718dceddSDavid Howells /** 520718dceddSDavid Howells * Handle of the buffer being pointed to by this relocation entry. 521718dceddSDavid Howells * 522718dceddSDavid Howells * It's appealing to make this be an index into the mm_validate_entry 523718dceddSDavid Howells * list to refer to the buffer, but this allows the driver to create 524718dceddSDavid Howells * a relocation list for state buffers and not re-write it per 525718dceddSDavid Howells * exec using the buffer. 526718dceddSDavid Howells */ 527718dceddSDavid Howells __u32 target_handle; 528718dceddSDavid Howells 529718dceddSDavid Howells /** 530718dceddSDavid Howells * Value to be added to the offset of the target buffer to make up 531718dceddSDavid Howells * the relocation entry. 532718dceddSDavid Howells */ 533718dceddSDavid Howells __u32 delta; 534718dceddSDavid Howells 535718dceddSDavid Howells /** Offset in the buffer the relocation entry will be written into */ 536718dceddSDavid Howells __u64 offset; 537718dceddSDavid Howells 538718dceddSDavid Howells /** 539718dceddSDavid Howells * Offset value of the target buffer that the relocation entry was last 540718dceddSDavid Howells * written as. 541718dceddSDavid Howells * 542718dceddSDavid Howells * If the buffer has the same offset as last time, we can skip syncing 543718dceddSDavid Howells * and writing the relocation. This value is written back out by 544718dceddSDavid Howells * the execbuffer ioctl when the relocation is written. 545718dceddSDavid Howells */ 546718dceddSDavid Howells __u64 presumed_offset; 547718dceddSDavid Howells 548718dceddSDavid Howells /** 549718dceddSDavid Howells * Target memory domains read by this operation. 550718dceddSDavid Howells */ 551718dceddSDavid Howells __u32 read_domains; 552718dceddSDavid Howells 553718dceddSDavid Howells /** 554718dceddSDavid Howells * Target memory domains written by this operation. 555718dceddSDavid Howells * 556718dceddSDavid Howells * Note that only one domain may be written by the whole 557718dceddSDavid Howells * execbuffer operation, so that where there are conflicts, 558718dceddSDavid Howells * the application will get -EINVAL back. 559718dceddSDavid Howells */ 560718dceddSDavid Howells __u32 write_domain; 561718dceddSDavid Howells }; 562718dceddSDavid Howells 563718dceddSDavid Howells /** @{ 564718dceddSDavid Howells * Intel memory domains 565718dceddSDavid Howells * 566718dceddSDavid Howells * Most of these just align with the various caches in 567718dceddSDavid Howells * the system and are used to flush and invalidate as 568718dceddSDavid Howells * objects end up cached in different domains. 569718dceddSDavid Howells */ 570718dceddSDavid Howells /** CPU cache */ 571718dceddSDavid Howells #define I915_GEM_DOMAIN_CPU 0x00000001 572718dceddSDavid Howells /** Render cache, used by 2D and 3D drawing */ 573718dceddSDavid Howells #define I915_GEM_DOMAIN_RENDER 0x00000002 574718dceddSDavid Howells /** Sampler cache, used by texture engine */ 575718dceddSDavid Howells #define I915_GEM_DOMAIN_SAMPLER 0x00000004 576718dceddSDavid Howells /** Command queue, used to load batch buffers */ 577718dceddSDavid Howells #define I915_GEM_DOMAIN_COMMAND 0x00000008 578718dceddSDavid Howells /** Instruction cache, used by shader programs */ 579718dceddSDavid Howells #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 580718dceddSDavid Howells /** Vertex address cache */ 581718dceddSDavid Howells #define I915_GEM_DOMAIN_VERTEX 0x00000020 582718dceddSDavid Howells /** GTT domain - aperture and scanout */ 583718dceddSDavid Howells #define I915_GEM_DOMAIN_GTT 0x00000040 584718dceddSDavid Howells /** @} */ 585718dceddSDavid Howells 586718dceddSDavid Howells struct drm_i915_gem_exec_object { 587718dceddSDavid Howells /** 588718dceddSDavid Howells * User's handle for a buffer to be bound into the GTT for this 589718dceddSDavid Howells * operation. 590718dceddSDavid Howells */ 591718dceddSDavid Howells __u32 handle; 592718dceddSDavid Howells 593718dceddSDavid Howells /** Number of relocations to be performed on this buffer */ 594718dceddSDavid Howells __u32 relocation_count; 595718dceddSDavid Howells /** 596718dceddSDavid Howells * Pointer to array of struct drm_i915_gem_relocation_entry containing 597718dceddSDavid Howells * the relocations to be performed in this buffer. 598718dceddSDavid Howells */ 599718dceddSDavid Howells __u64 relocs_ptr; 600718dceddSDavid Howells 601718dceddSDavid Howells /** Required alignment in graphics aperture */ 602718dceddSDavid Howells __u64 alignment; 603718dceddSDavid Howells 604718dceddSDavid Howells /** 605718dceddSDavid Howells * Returned value of the updated offset of the object, for future 606718dceddSDavid Howells * presumed_offset writes. 607718dceddSDavid Howells */ 608718dceddSDavid Howells __u64 offset; 609718dceddSDavid Howells }; 610718dceddSDavid Howells 611718dceddSDavid Howells struct drm_i915_gem_execbuffer { 612718dceddSDavid Howells /** 613718dceddSDavid Howells * List of buffers to be validated with their relocations to be 614718dceddSDavid Howells * performend on them. 615718dceddSDavid Howells * 616718dceddSDavid Howells * This is a pointer to an array of struct drm_i915_gem_validate_entry. 617718dceddSDavid Howells * 618718dceddSDavid Howells * These buffers must be listed in an order such that all relocations 619718dceddSDavid Howells * a buffer is performing refer to buffers that have already appeared 620718dceddSDavid Howells * in the validate list. 621718dceddSDavid Howells */ 622718dceddSDavid Howells __u64 buffers_ptr; 623718dceddSDavid Howells __u32 buffer_count; 624718dceddSDavid Howells 625718dceddSDavid Howells /** Offset in the batchbuffer to start execution from. */ 626718dceddSDavid Howells __u32 batch_start_offset; 627718dceddSDavid Howells /** Bytes used in batchbuffer from batch_start_offset */ 628718dceddSDavid Howells __u32 batch_len; 629718dceddSDavid Howells __u32 DR1; 630718dceddSDavid Howells __u32 DR4; 631718dceddSDavid Howells __u32 num_cliprects; 632718dceddSDavid Howells /** This is a struct drm_clip_rect *cliprects */ 633718dceddSDavid Howells __u64 cliprects_ptr; 634718dceddSDavid Howells }; 635718dceddSDavid Howells 636718dceddSDavid Howells struct drm_i915_gem_exec_object2 { 637718dceddSDavid Howells /** 638718dceddSDavid Howells * User's handle for a buffer to be bound into the GTT for this 639718dceddSDavid Howells * operation. 640718dceddSDavid Howells */ 641718dceddSDavid Howells __u32 handle; 642718dceddSDavid Howells 643718dceddSDavid Howells /** Number of relocations to be performed on this buffer */ 644718dceddSDavid Howells __u32 relocation_count; 645718dceddSDavid Howells /** 646718dceddSDavid Howells * Pointer to array of struct drm_i915_gem_relocation_entry containing 647718dceddSDavid Howells * the relocations to be performed in this buffer. 648718dceddSDavid Howells */ 649718dceddSDavid Howells __u64 relocs_ptr; 650718dceddSDavid Howells 651718dceddSDavid Howells /** Required alignment in graphics aperture */ 652718dceddSDavid Howells __u64 alignment; 653718dceddSDavid Howells 654718dceddSDavid Howells /** 655718dceddSDavid Howells * Returned value of the updated offset of the object, for future 656718dceddSDavid Howells * presumed_offset writes. 657718dceddSDavid Howells */ 658718dceddSDavid Howells __u64 offset; 659718dceddSDavid Howells 660718dceddSDavid Howells #define EXEC_OBJECT_NEEDS_FENCE (1<<0) 661ed5982e6SDaniel Vetter #define EXEC_OBJECT_NEEDS_GTT (1<<1) 662ed5982e6SDaniel Vetter #define EXEC_OBJECT_WRITE (1<<2) 663ed5982e6SDaniel Vetter #define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_WRITE<<1) 664718dceddSDavid Howells __u64 flags; 665ed5982e6SDaniel Vetter 666718dceddSDavid Howells __u64 rsvd1; 667718dceddSDavid Howells __u64 rsvd2; 668718dceddSDavid Howells }; 669718dceddSDavid Howells 670718dceddSDavid Howells struct drm_i915_gem_execbuffer2 { 671718dceddSDavid Howells /** 672718dceddSDavid Howells * List of gem_exec_object2 structs 673718dceddSDavid Howells */ 674718dceddSDavid Howells __u64 buffers_ptr; 675718dceddSDavid Howells __u32 buffer_count; 676718dceddSDavid Howells 677718dceddSDavid Howells /** Offset in the batchbuffer to start execution from. */ 678718dceddSDavid Howells __u32 batch_start_offset; 679718dceddSDavid Howells /** Bytes used in batchbuffer from batch_start_offset */ 680718dceddSDavid Howells __u32 batch_len; 681718dceddSDavid Howells __u32 DR1; 682718dceddSDavid Howells __u32 DR4; 683718dceddSDavid Howells __u32 num_cliprects; 684718dceddSDavid Howells /** This is a struct drm_clip_rect *cliprects */ 685718dceddSDavid Howells __u64 cliprects_ptr; 686718dceddSDavid Howells #define I915_EXEC_RING_MASK (7<<0) 687718dceddSDavid Howells #define I915_EXEC_DEFAULT (0<<0) 688718dceddSDavid Howells #define I915_EXEC_RENDER (1<<0) 689718dceddSDavid Howells #define I915_EXEC_BSD (2<<0) 690718dceddSDavid Howells #define I915_EXEC_BLT (3<<0) 69182f91b6eSXiang, Haihao #define I915_EXEC_VEBOX (4<<0) 692718dceddSDavid Howells 693718dceddSDavid Howells /* Used for switching the constants addressing mode on gen4+ RENDER ring. 694718dceddSDavid Howells * Gen6+ only supports relative addressing to dynamic state (default) and 695718dceddSDavid Howells * absolute addressing. 696718dceddSDavid Howells * 697718dceddSDavid Howells * These flags are ignored for the BSD and BLT rings. 698718dceddSDavid Howells */ 699718dceddSDavid Howells #define I915_EXEC_CONSTANTS_MASK (3<<6) 700718dceddSDavid Howells #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ 701718dceddSDavid Howells #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) 702718dceddSDavid Howells #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ 703718dceddSDavid Howells __u64 flags; 704718dceddSDavid Howells __u64 rsvd1; /* now used for context info */ 705718dceddSDavid Howells __u64 rsvd2; 706718dceddSDavid Howells }; 707718dceddSDavid Howells 708718dceddSDavid Howells /** Resets the SO write offset registers for transform feedback on gen7. */ 709718dceddSDavid Howells #define I915_EXEC_GEN7_SOL_RESET (1<<8) 710718dceddSDavid Howells 711c2fb7916SDaniel Vetter /** Request a privileged ("secure") batch buffer. Note only available for 712c2fb7916SDaniel Vetter * DRM_ROOT_ONLY | DRM_MASTER processes. 713c2fb7916SDaniel Vetter */ 714c2fb7916SDaniel Vetter #define I915_EXEC_SECURE (1<<9) 715c2fb7916SDaniel Vetter 716b45305fcSDaniel Vetter /** Inform the kernel that the batch is and will always be pinned. This 717b45305fcSDaniel Vetter * negates the requirement for a workaround to be performed to avoid 718b45305fcSDaniel Vetter * an incoherent CS (such as can be found on 830/845). If this flag is 719b45305fcSDaniel Vetter * not passed, the kernel will endeavour to make sure the batch is 720b45305fcSDaniel Vetter * coherent with the CS before execution. If this flag is passed, 721b45305fcSDaniel Vetter * userspace assumes the responsibility for ensuring the same. 722b45305fcSDaniel Vetter */ 723b45305fcSDaniel Vetter #define I915_EXEC_IS_PINNED (1<<10) 724b45305fcSDaniel Vetter 725c3d19d3cSGeert Uytterhoeven /** Provide a hint to the kernel that the command stream and auxiliary 726ed5982e6SDaniel Vetter * state buffers already holds the correct presumed addresses and so the 727ed5982e6SDaniel Vetter * relocation process may be skipped if no buffers need to be moved in 728ed5982e6SDaniel Vetter * preparation for the execbuffer. 729ed5982e6SDaniel Vetter */ 730ed5982e6SDaniel Vetter #define I915_EXEC_NO_RELOC (1<<11) 731ed5982e6SDaniel Vetter 732eef90ccbSChris Wilson /** Use the reloc.handle as an index into the exec object array rather 733eef90ccbSChris Wilson * than as the per-file handle. 734eef90ccbSChris Wilson */ 735eef90ccbSChris Wilson #define I915_EXEC_HANDLE_LUT (1<<12) 736eef90ccbSChris Wilson 737eef90ccbSChris Wilson #define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_HANDLE_LUT<<1) 738ed5982e6SDaniel Vetter 739718dceddSDavid Howells #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) 740718dceddSDavid Howells #define i915_execbuffer2_set_context_id(eb2, context) \ 741718dceddSDavid Howells (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK 742718dceddSDavid Howells #define i915_execbuffer2_get_context_id(eb2) \ 743718dceddSDavid Howells ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) 744718dceddSDavid Howells 745718dceddSDavid Howells struct drm_i915_gem_pin { 746718dceddSDavid Howells /** Handle of the buffer to be pinned. */ 747718dceddSDavid Howells __u32 handle; 748718dceddSDavid Howells __u32 pad; 749718dceddSDavid Howells 750718dceddSDavid Howells /** alignment required within the aperture */ 751718dceddSDavid Howells __u64 alignment; 752718dceddSDavid Howells 753718dceddSDavid Howells /** Returned GTT offset of the buffer. */ 754718dceddSDavid Howells __u64 offset; 755718dceddSDavid Howells }; 756718dceddSDavid Howells 757718dceddSDavid Howells struct drm_i915_gem_unpin { 758718dceddSDavid Howells /** Handle of the buffer to be unpinned. */ 759718dceddSDavid Howells __u32 handle; 760718dceddSDavid Howells __u32 pad; 761718dceddSDavid Howells }; 762718dceddSDavid Howells 763718dceddSDavid Howells struct drm_i915_gem_busy { 764718dceddSDavid Howells /** Handle of the buffer to check for busy */ 765718dceddSDavid Howells __u32 handle; 766718dceddSDavid Howells 767718dceddSDavid Howells /** Return busy status (1 if busy, 0 if idle). 768718dceddSDavid Howells * The high word is used to indicate on which rings the object 769718dceddSDavid Howells * currently resides: 770718dceddSDavid Howells * 16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc) 771718dceddSDavid Howells */ 772718dceddSDavid Howells __u32 busy; 773718dceddSDavid Howells }; 774718dceddSDavid Howells 77535c7ab42SDaniel Vetter /** 77635c7ab42SDaniel Vetter * I915_CACHING_NONE 77735c7ab42SDaniel Vetter * 77835c7ab42SDaniel Vetter * GPU access is not coherent with cpu caches. Default for machines without an 77935c7ab42SDaniel Vetter * LLC. 78035c7ab42SDaniel Vetter */ 781718dceddSDavid Howells #define I915_CACHING_NONE 0 78235c7ab42SDaniel Vetter /** 78335c7ab42SDaniel Vetter * I915_CACHING_CACHED 78435c7ab42SDaniel Vetter * 78535c7ab42SDaniel Vetter * GPU access is coherent with cpu caches and furthermore the data is cached in 78635c7ab42SDaniel Vetter * last-level caches shared between cpu cores and the gpu GT. Default on 78735c7ab42SDaniel Vetter * machines with HAS_LLC. 78835c7ab42SDaniel Vetter */ 789718dceddSDavid Howells #define I915_CACHING_CACHED 1 79035c7ab42SDaniel Vetter /** 79135c7ab42SDaniel Vetter * I915_CACHING_DISPLAY 79235c7ab42SDaniel Vetter * 79335c7ab42SDaniel Vetter * Special GPU caching mode which is coherent with the scanout engines. 79435c7ab42SDaniel Vetter * Transparently falls back to I915_CACHING_NONE on platforms where no special 79535c7ab42SDaniel Vetter * cache mode (like write-through or gfdt flushing) is available. The kernel 79635c7ab42SDaniel Vetter * automatically sets this mode when using a buffer as a scanout target. 79735c7ab42SDaniel Vetter * Userspace can manually set this mode to avoid a costly stall and clflush in 79835c7ab42SDaniel Vetter * the hotpath of drawing the first frame. 79935c7ab42SDaniel Vetter */ 80035c7ab42SDaniel Vetter #define I915_CACHING_DISPLAY 2 801718dceddSDavid Howells 802718dceddSDavid Howells struct drm_i915_gem_caching { 803718dceddSDavid Howells /** 804718dceddSDavid Howells * Handle of the buffer to set/get the caching level of. */ 805718dceddSDavid Howells __u32 handle; 806718dceddSDavid Howells 807718dceddSDavid Howells /** 808718dceddSDavid Howells * Cacheing level to apply or return value 809718dceddSDavid Howells * 810718dceddSDavid Howells * bits0-15 are for generic caching control (i.e. the above defined 811718dceddSDavid Howells * values). bits16-31 are reserved for platform-specific variations 812718dceddSDavid Howells * (e.g. l3$ caching on gen7). */ 813718dceddSDavid Howells __u32 caching; 814718dceddSDavid Howells }; 815718dceddSDavid Howells 816718dceddSDavid Howells #define I915_TILING_NONE 0 817718dceddSDavid Howells #define I915_TILING_X 1 818718dceddSDavid Howells #define I915_TILING_Y 2 819718dceddSDavid Howells 820718dceddSDavid Howells #define I915_BIT_6_SWIZZLE_NONE 0 821718dceddSDavid Howells #define I915_BIT_6_SWIZZLE_9 1 822718dceddSDavid Howells #define I915_BIT_6_SWIZZLE_9_10 2 823718dceddSDavid Howells #define I915_BIT_6_SWIZZLE_9_11 3 824718dceddSDavid Howells #define I915_BIT_6_SWIZZLE_9_10_11 4 825718dceddSDavid Howells /* Not seen by userland */ 826718dceddSDavid Howells #define I915_BIT_6_SWIZZLE_UNKNOWN 5 827718dceddSDavid Howells /* Seen by userland. */ 828718dceddSDavid Howells #define I915_BIT_6_SWIZZLE_9_17 6 829718dceddSDavid Howells #define I915_BIT_6_SWIZZLE_9_10_17 7 830718dceddSDavid Howells 831718dceddSDavid Howells struct drm_i915_gem_set_tiling { 832718dceddSDavid Howells /** Handle of the buffer to have its tiling state updated */ 833718dceddSDavid Howells __u32 handle; 834718dceddSDavid Howells 835718dceddSDavid Howells /** 836718dceddSDavid Howells * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 837718dceddSDavid Howells * I915_TILING_Y). 838718dceddSDavid Howells * 839718dceddSDavid Howells * This value is to be set on request, and will be updated by the 840718dceddSDavid Howells * kernel on successful return with the actual chosen tiling layout. 841718dceddSDavid Howells * 842718dceddSDavid Howells * The tiling mode may be demoted to I915_TILING_NONE when the system 843718dceddSDavid Howells * has bit 6 swizzling that can't be managed correctly by GEM. 844718dceddSDavid Howells * 845718dceddSDavid Howells * Buffer contents become undefined when changing tiling_mode. 846718dceddSDavid Howells */ 847718dceddSDavid Howells __u32 tiling_mode; 848718dceddSDavid Howells 849718dceddSDavid Howells /** 850718dceddSDavid Howells * Stride in bytes for the object when in I915_TILING_X or 851718dceddSDavid Howells * I915_TILING_Y. 852718dceddSDavid Howells */ 853718dceddSDavid Howells __u32 stride; 854718dceddSDavid Howells 855718dceddSDavid Howells /** 856718dceddSDavid Howells * Returned address bit 6 swizzling required for CPU access through 857718dceddSDavid Howells * mmap mapping. 858718dceddSDavid Howells */ 859718dceddSDavid Howells __u32 swizzle_mode; 860718dceddSDavid Howells }; 861718dceddSDavid Howells 862718dceddSDavid Howells struct drm_i915_gem_get_tiling { 863718dceddSDavid Howells /** Handle of the buffer to get tiling state for. */ 864718dceddSDavid Howells __u32 handle; 865718dceddSDavid Howells 866718dceddSDavid Howells /** 867718dceddSDavid Howells * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 868718dceddSDavid Howells * I915_TILING_Y). 869718dceddSDavid Howells */ 870718dceddSDavid Howells __u32 tiling_mode; 871718dceddSDavid Howells 872718dceddSDavid Howells /** 873718dceddSDavid Howells * Returned address bit 6 swizzling required for CPU access through 874718dceddSDavid Howells * mmap mapping. 875718dceddSDavid Howells */ 876718dceddSDavid Howells __u32 swizzle_mode; 877718dceddSDavid Howells }; 878718dceddSDavid Howells 879718dceddSDavid Howells struct drm_i915_gem_get_aperture { 880718dceddSDavid Howells /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ 881718dceddSDavid Howells __u64 aper_size; 882718dceddSDavid Howells 883718dceddSDavid Howells /** 884718dceddSDavid Howells * Available space in the aperture used by i915_gem_execbuffer, in 885718dceddSDavid Howells * bytes 886718dceddSDavid Howells */ 887718dceddSDavid Howells __u64 aper_available_size; 888718dceddSDavid Howells }; 889718dceddSDavid Howells 890718dceddSDavid Howells struct drm_i915_get_pipe_from_crtc_id { 891718dceddSDavid Howells /** ID of CRTC being requested **/ 892718dceddSDavid Howells __u32 crtc_id; 893718dceddSDavid Howells 894718dceddSDavid Howells /** pipe of requested CRTC **/ 895718dceddSDavid Howells __u32 pipe; 896718dceddSDavid Howells }; 897718dceddSDavid Howells 898718dceddSDavid Howells #define I915_MADV_WILLNEED 0 899718dceddSDavid Howells #define I915_MADV_DONTNEED 1 900718dceddSDavid Howells #define __I915_MADV_PURGED 2 /* internal state */ 901718dceddSDavid Howells 902718dceddSDavid Howells struct drm_i915_gem_madvise { 903718dceddSDavid Howells /** Handle of the buffer to change the backing store advice */ 904718dceddSDavid Howells __u32 handle; 905718dceddSDavid Howells 906718dceddSDavid Howells /* Advice: either the buffer will be needed again in the near future, 907718dceddSDavid Howells * or wont be and could be discarded under memory pressure. 908718dceddSDavid Howells */ 909718dceddSDavid Howells __u32 madv; 910718dceddSDavid Howells 911718dceddSDavid Howells /** Whether the backing store still exists. */ 912718dceddSDavid Howells __u32 retained; 913718dceddSDavid Howells }; 914718dceddSDavid Howells 915718dceddSDavid Howells /* flags */ 916718dceddSDavid Howells #define I915_OVERLAY_TYPE_MASK 0xff 917718dceddSDavid Howells #define I915_OVERLAY_YUV_PLANAR 0x01 918718dceddSDavid Howells #define I915_OVERLAY_YUV_PACKED 0x02 919718dceddSDavid Howells #define I915_OVERLAY_RGB 0x03 920718dceddSDavid Howells 921718dceddSDavid Howells #define I915_OVERLAY_DEPTH_MASK 0xff00 922718dceddSDavid Howells #define I915_OVERLAY_RGB24 0x1000 923718dceddSDavid Howells #define I915_OVERLAY_RGB16 0x2000 924718dceddSDavid Howells #define I915_OVERLAY_RGB15 0x3000 925718dceddSDavid Howells #define I915_OVERLAY_YUV422 0x0100 926718dceddSDavid Howells #define I915_OVERLAY_YUV411 0x0200 927718dceddSDavid Howells #define I915_OVERLAY_YUV420 0x0300 928718dceddSDavid Howells #define I915_OVERLAY_YUV410 0x0400 929718dceddSDavid Howells 930718dceddSDavid Howells #define I915_OVERLAY_SWAP_MASK 0xff0000 931718dceddSDavid Howells #define I915_OVERLAY_NO_SWAP 0x000000 932718dceddSDavid Howells #define I915_OVERLAY_UV_SWAP 0x010000 933718dceddSDavid Howells #define I915_OVERLAY_Y_SWAP 0x020000 934718dceddSDavid Howells #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 935718dceddSDavid Howells 936718dceddSDavid Howells #define I915_OVERLAY_FLAGS_MASK 0xff000000 937718dceddSDavid Howells #define I915_OVERLAY_ENABLE 0x01000000 938718dceddSDavid Howells 939718dceddSDavid Howells struct drm_intel_overlay_put_image { 940718dceddSDavid Howells /* various flags and src format description */ 941718dceddSDavid Howells __u32 flags; 942718dceddSDavid Howells /* source picture description */ 943718dceddSDavid Howells __u32 bo_handle; 944718dceddSDavid Howells /* stride values and offsets are in bytes, buffer relative */ 945718dceddSDavid Howells __u16 stride_Y; /* stride for packed formats */ 946718dceddSDavid Howells __u16 stride_UV; 947718dceddSDavid Howells __u32 offset_Y; /* offset for packet formats */ 948718dceddSDavid Howells __u32 offset_U; 949718dceddSDavid Howells __u32 offset_V; 950718dceddSDavid Howells /* in pixels */ 951718dceddSDavid Howells __u16 src_width; 952718dceddSDavid Howells __u16 src_height; 953718dceddSDavid Howells /* to compensate the scaling factors for partially covered surfaces */ 954718dceddSDavid Howells __u16 src_scan_width; 955718dceddSDavid Howells __u16 src_scan_height; 956718dceddSDavid Howells /* output crtc description */ 957718dceddSDavid Howells __u32 crtc_id; 958718dceddSDavid Howells __u16 dst_x; 959718dceddSDavid Howells __u16 dst_y; 960718dceddSDavid Howells __u16 dst_width; 961718dceddSDavid Howells __u16 dst_height; 962718dceddSDavid Howells }; 963718dceddSDavid Howells 964718dceddSDavid Howells /* flags */ 965718dceddSDavid Howells #define I915_OVERLAY_UPDATE_ATTRS (1<<0) 966718dceddSDavid Howells #define I915_OVERLAY_UPDATE_GAMMA (1<<1) 967718dceddSDavid Howells struct drm_intel_overlay_attrs { 968718dceddSDavid Howells __u32 flags; 969718dceddSDavid Howells __u32 color_key; 970718dceddSDavid Howells __s32 brightness; 971718dceddSDavid Howells __u32 contrast; 972718dceddSDavid Howells __u32 saturation; 973718dceddSDavid Howells __u32 gamma0; 974718dceddSDavid Howells __u32 gamma1; 975718dceddSDavid Howells __u32 gamma2; 976718dceddSDavid Howells __u32 gamma3; 977718dceddSDavid Howells __u32 gamma4; 978718dceddSDavid Howells __u32 gamma5; 979718dceddSDavid Howells }; 980718dceddSDavid Howells 981718dceddSDavid Howells /* 982718dceddSDavid Howells * Intel sprite handling 983718dceddSDavid Howells * 984718dceddSDavid Howells * Color keying works with a min/mask/max tuple. Both source and destination 985718dceddSDavid Howells * color keying is allowed. 986718dceddSDavid Howells * 987718dceddSDavid Howells * Source keying: 988718dceddSDavid Howells * Sprite pixels within the min & max values, masked against the color channels 989718dceddSDavid Howells * specified in the mask field, will be transparent. All other pixels will 990718dceddSDavid Howells * be displayed on top of the primary plane. For RGB surfaces, only the min 991718dceddSDavid Howells * and mask fields will be used; ranged compares are not allowed. 992718dceddSDavid Howells * 993718dceddSDavid Howells * Destination keying: 994718dceddSDavid Howells * Primary plane pixels that match the min value, masked against the color 995718dceddSDavid Howells * channels specified in the mask field, will be replaced by corresponding 996718dceddSDavid Howells * pixels from the sprite plane. 997718dceddSDavid Howells * 998718dceddSDavid Howells * Note that source & destination keying are exclusive; only one can be 999718dceddSDavid Howells * active on a given plane. 1000718dceddSDavid Howells */ 1001718dceddSDavid Howells 1002718dceddSDavid Howells #define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */ 1003718dceddSDavid Howells #define I915_SET_COLORKEY_DESTINATION (1<<1) 1004718dceddSDavid Howells #define I915_SET_COLORKEY_SOURCE (1<<2) 1005718dceddSDavid Howells struct drm_intel_sprite_colorkey { 1006718dceddSDavid Howells __u32 plane_id; 1007718dceddSDavid Howells __u32 min_value; 1008718dceddSDavid Howells __u32 channel_mask; 1009718dceddSDavid Howells __u32 max_value; 1010718dceddSDavid Howells __u32 flags; 1011718dceddSDavid Howells }; 1012718dceddSDavid Howells 1013718dceddSDavid Howells struct drm_i915_gem_wait { 1014718dceddSDavid Howells /** Handle of BO we shall wait on */ 1015718dceddSDavid Howells __u32 bo_handle; 1016718dceddSDavid Howells __u32 flags; 1017718dceddSDavid Howells /** Number of nanoseconds to wait, Returns time remaining. */ 1018718dceddSDavid Howells __s64 timeout_ns; 1019718dceddSDavid Howells }; 1020718dceddSDavid Howells 1021718dceddSDavid Howells struct drm_i915_gem_context_create { 1022718dceddSDavid Howells /* output: id of new context*/ 1023718dceddSDavid Howells __u32 ctx_id; 1024718dceddSDavid Howells __u32 pad; 1025718dceddSDavid Howells }; 1026718dceddSDavid Howells 1027718dceddSDavid Howells struct drm_i915_gem_context_destroy { 1028718dceddSDavid Howells __u32 ctx_id; 1029718dceddSDavid Howells __u32 pad; 1030718dceddSDavid Howells }; 1031718dceddSDavid Howells 1032718dceddSDavid Howells struct drm_i915_reg_read { 1033718dceddSDavid Howells __u64 offset; 1034718dceddSDavid Howells __u64 val; /* Return value */ 1035718dceddSDavid Howells }; 1036b6359918SMika Kuoppala 1037b6359918SMika Kuoppala struct drm_i915_reset_stats { 1038b6359918SMika Kuoppala __u32 ctx_id; 1039b6359918SMika Kuoppala __u32 flags; 1040b6359918SMika Kuoppala 1041b6359918SMika Kuoppala /* All resets since boot/module reload, for all contexts */ 1042b6359918SMika Kuoppala __u32 reset_count; 1043b6359918SMika Kuoppala 1044b6359918SMika Kuoppala /* Number of batches lost when active in GPU, for this context */ 1045b6359918SMika Kuoppala __u32 batch_active; 1046b6359918SMika Kuoppala 1047b6359918SMika Kuoppala /* Number of batches lost pending for execution, for this context */ 1048b6359918SMika Kuoppala __u32 batch_pending; 1049b6359918SMika Kuoppala 1050b6359918SMika Kuoppala __u32 pad; 1051b6359918SMika Kuoppala }; 1052b6359918SMika Kuoppala 1053718dceddSDavid Howells #endif /* _UAPI_I915_DRM_H_ */ 1054