1718dceddSDavid Howells /* 2718dceddSDavid Howells * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 3718dceddSDavid Howells * All Rights Reserved. 4718dceddSDavid Howells * 5718dceddSDavid Howells * Permission is hereby granted, free of charge, to any person obtaining a 6718dceddSDavid Howells * copy of this software and associated documentation files (the 7718dceddSDavid Howells * "Software"), to deal in the Software without restriction, including 8718dceddSDavid Howells * without limitation the rights to use, copy, modify, merge, publish, 9718dceddSDavid Howells * distribute, sub license, and/or sell copies of the Software, and to 10718dceddSDavid Howells * permit persons to whom the Software is furnished to do so, subject to 11718dceddSDavid Howells * the following conditions: 12718dceddSDavid Howells * 13718dceddSDavid Howells * The above copyright notice and this permission notice (including the 14718dceddSDavid Howells * next paragraph) shall be included in all copies or substantial portions 15718dceddSDavid Howells * of the Software. 16718dceddSDavid Howells * 17718dceddSDavid Howells * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18718dceddSDavid Howells * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19718dceddSDavid Howells * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20718dceddSDavid Howells * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 21718dceddSDavid Howells * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22718dceddSDavid Howells * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23718dceddSDavid Howells * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24718dceddSDavid Howells * 25718dceddSDavid Howells */ 26718dceddSDavid Howells 27718dceddSDavid Howells #ifndef _UAPI_I915_DRM_H_ 28718dceddSDavid Howells #define _UAPI_I915_DRM_H_ 29718dceddSDavid Howells 301049102fSGabriel Laskar #include "drm.h" 31718dceddSDavid Howells 32b1c1f5c4SEmil Velikov #if defined(__cplusplus) 33b1c1f5c4SEmil Velikov extern "C" { 34b1c1f5c4SEmil Velikov #endif 35b1c1f5c4SEmil Velikov 36718dceddSDavid Howells /* Please note that modifications to all structs defined here are 37718dceddSDavid Howells * subject to backwards-compatibility constraints. 38718dceddSDavid Howells */ 39718dceddSDavid Howells 40cce723edSBen Widawsky /** 41cce723edSBen Widawsky * DOC: uevents generated by i915 on it's device node 42cce723edSBen Widawsky * 43cce723edSBen Widawsky * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch 44cce723edSBen Widawsky * event from the gpu l3 cache. Additional information supplied is ROW, 4535a85ac6SBen Widawsky * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep 4635a85ac6SBen Widawsky * track of these events and if a specific cache-line seems to have a 4735a85ac6SBen Widawsky * persistent error remap it with the l3 remapping tool supplied in 4835a85ac6SBen Widawsky * intel-gpu-tools. The value supplied with the event is always 1. 49cce723edSBen Widawsky * 50cce723edSBen Widawsky * I915_ERROR_UEVENT - Generated upon error detection, currently only via 51cce723edSBen Widawsky * hangcheck. The error detection event is a good indicator of when things 52cce723edSBen Widawsky * began to go badly. The value supplied with the event is a 1 upon error 53cce723edSBen Widawsky * detection, and a 0 upon reset completion, signifying no more error 54cce723edSBen Widawsky * exists. NOTE: Disabling hangcheck or reset via module parameter will 55cce723edSBen Widawsky * cause the related events to not be seen. 56cce723edSBen Widawsky * 57cce723edSBen Widawsky * I915_RESET_UEVENT - Event is generated just before an attempt to reset the 5866137f54SRandy Dunlap * GPU. The value supplied with the event is always 1. NOTE: Disable 59cce723edSBen Widawsky * reset via module parameter will cause this event to not be seen. 60cce723edSBen Widawsky */ 61cce723edSBen Widawsky #define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR" 62cce723edSBen Widawsky #define I915_ERROR_UEVENT "ERROR" 63cce723edSBen Widawsky #define I915_RESET_UEVENT "RESET" 64718dceddSDavid Howells 6519d053d4SMatthew Auld /** 6619d053d4SMatthew Auld * struct i915_user_extension - Base class for defining a chain of extensions 679d1305efSChris Wilson * 689d1305efSChris Wilson * Many interfaces need to grow over time. In most cases we can simply 699d1305efSChris Wilson * extend the struct and have userspace pass in more data. Another option, 709d1305efSChris Wilson * as demonstrated by Vulkan's approach to providing extensions for forward 719d1305efSChris Wilson * and backward compatibility, is to use a list of optional structs to 729d1305efSChris Wilson * provide those extra details. 739d1305efSChris Wilson * 749d1305efSChris Wilson * The key advantage to using an extension chain is that it allows us to 759d1305efSChris Wilson * redefine the interface more easily than an ever growing struct of 769d1305efSChris Wilson * increasing complexity, and for large parts of that interface to be 779d1305efSChris Wilson * entirely optional. The downside is more pointer chasing; chasing across 789d1305efSChris Wilson * the __user boundary with pointers encapsulated inside u64. 7919d053d4SMatthew Auld * 8019d053d4SMatthew Auld * Example chaining: 8119d053d4SMatthew Auld * 8219d053d4SMatthew Auld * .. code-block:: C 8319d053d4SMatthew Auld * 8419d053d4SMatthew Auld * struct i915_user_extension ext3 { 8519d053d4SMatthew Auld * .next_extension = 0, // end 8619d053d4SMatthew Auld * .name = ..., 8719d053d4SMatthew Auld * }; 8819d053d4SMatthew Auld * struct i915_user_extension ext2 { 8919d053d4SMatthew Auld * .next_extension = (uintptr_t)&ext3, 9019d053d4SMatthew Auld * .name = ..., 9119d053d4SMatthew Auld * }; 9219d053d4SMatthew Auld * struct i915_user_extension ext1 { 9319d053d4SMatthew Auld * .next_extension = (uintptr_t)&ext2, 9419d053d4SMatthew Auld * .name = ..., 9519d053d4SMatthew Auld * }; 9619d053d4SMatthew Auld * 9719d053d4SMatthew Auld * Typically the struct i915_user_extension would be embedded in some uAPI 9819d053d4SMatthew Auld * struct, and in this case we would feed it the head of the chain(i.e ext1), 9919d053d4SMatthew Auld * which would then apply all of the above extensions. 10019d053d4SMatthew Auld * 1019d1305efSChris Wilson */ 1029d1305efSChris Wilson struct i915_user_extension { 10319d053d4SMatthew Auld /** 10419d053d4SMatthew Auld * @next_extension: 10519d053d4SMatthew Auld * 10619d053d4SMatthew Auld * Pointer to the next struct i915_user_extension, or zero if the end. 10719d053d4SMatthew Auld */ 1089d1305efSChris Wilson __u64 next_extension; 10919d053d4SMatthew Auld /** 11019d053d4SMatthew Auld * @name: Name of the extension. 11119d053d4SMatthew Auld * 11219d053d4SMatthew Auld * Note that the name here is just some integer. 11319d053d4SMatthew Auld * 11419d053d4SMatthew Auld * Also note that the name space for this is not global for the whole 11519d053d4SMatthew Auld * driver, but rather its scope/meaning is limited to the specific piece 11619d053d4SMatthew Auld * of uAPI which has embedded the struct i915_user_extension. 11719d053d4SMatthew Auld */ 1189d1305efSChris Wilson __u32 name; 11919d053d4SMatthew Auld /** 12019d053d4SMatthew Auld * @flags: MBZ 12119d053d4SMatthew Auld * 12219d053d4SMatthew Auld * All undefined bits must be zero. 12319d053d4SMatthew Auld */ 12419d053d4SMatthew Auld __u32 flags; 12519d053d4SMatthew Auld /** 12619d053d4SMatthew Auld * @rsvd: MBZ 12719d053d4SMatthew Auld * 12819d053d4SMatthew Auld * Reserved for future use; must be zero. 12919d053d4SMatthew Auld */ 13019d053d4SMatthew Auld __u32 rsvd[4]; 1319d1305efSChris Wilson }; 1329d1305efSChris Wilson 1339d1305efSChris Wilson /* 1343373ce2eSImre Deak * MOCS indexes used for GPU surfaces, defining the cacheability of the 1353373ce2eSImre Deak * surface data and the coherency for this data wrt. CPU vs. GPU accesses. 1363373ce2eSImre Deak */ 1373373ce2eSImre Deak enum i915_mocs_table_index { 1383373ce2eSImre Deak /* 1393373ce2eSImre Deak * Not cached anywhere, coherency between CPU and GPU accesses is 1403373ce2eSImre Deak * guaranteed. 1413373ce2eSImre Deak */ 1423373ce2eSImre Deak I915_MOCS_UNCACHED, 1433373ce2eSImre Deak /* 1443373ce2eSImre Deak * Cacheability and coherency controlled by the kernel automatically 1453373ce2eSImre Deak * based on the DRM_I915_GEM_SET_CACHING IOCTL setting and the current 1463373ce2eSImre Deak * usage of the surface (used for display scanout or not). 1473373ce2eSImre Deak */ 1483373ce2eSImre Deak I915_MOCS_PTE, 1493373ce2eSImre Deak /* 1503373ce2eSImre Deak * Cached in all GPU caches available on the platform. 1513373ce2eSImre Deak * Coherency between CPU and GPU accesses to the surface is not 1523373ce2eSImre Deak * guaranteed without extra synchronization. 1533373ce2eSImre Deak */ 1543373ce2eSImre Deak I915_MOCS_CACHED, 1553373ce2eSImre Deak }; 1563373ce2eSImre Deak 157*991b4de3SMatt Roper /** 158*991b4de3SMatt Roper * enum drm_i915_gem_engine_class - uapi engine type enumeration 159*991b4de3SMatt Roper * 1601803fcbcSTvrtko Ursulin * Different engines serve different roles, and there may be more than one 161*991b4de3SMatt Roper * engine serving each role. This enum provides a classification of the role 162*991b4de3SMatt Roper * of the engine, which may be used when requesting operations to be performed 163*991b4de3SMatt Roper * on a certain subset of engines, or for providing information about that 164*991b4de3SMatt Roper * group. 1651803fcbcSTvrtko Ursulin */ 1661803fcbcSTvrtko Ursulin enum drm_i915_gem_engine_class { 167*991b4de3SMatt Roper /** 168*991b4de3SMatt Roper * @I915_ENGINE_CLASS_RENDER: 169*991b4de3SMatt Roper * 170*991b4de3SMatt Roper * Render engines support instructions used for 3D, Compute (GPGPU), 171*991b4de3SMatt Roper * and programmable media workloads. These instructions fetch data and 172*991b4de3SMatt Roper * dispatch individual work items to threads that operate in parallel. 173*991b4de3SMatt Roper * The threads run small programs (called "kernels" or "shaders") on 174*991b4de3SMatt Roper * the GPU's execution units (EUs). 175*991b4de3SMatt Roper */ 1761803fcbcSTvrtko Ursulin I915_ENGINE_CLASS_RENDER = 0, 177*991b4de3SMatt Roper 178*991b4de3SMatt Roper /** 179*991b4de3SMatt Roper * @I915_ENGINE_CLASS_COPY: 180*991b4de3SMatt Roper * 181*991b4de3SMatt Roper * Copy engines (also referred to as "blitters") support instructions 182*991b4de3SMatt Roper * that move blocks of data from one location in memory to another, 183*991b4de3SMatt Roper * or that fill a specified location of memory with fixed data. 184*991b4de3SMatt Roper * Copy engines can perform pre-defined logical or bitwise operations 185*991b4de3SMatt Roper * on the source, destination, or pattern data. 186*991b4de3SMatt Roper */ 1871803fcbcSTvrtko Ursulin I915_ENGINE_CLASS_COPY = 1, 188*991b4de3SMatt Roper 189*991b4de3SMatt Roper /** 190*991b4de3SMatt Roper * @I915_ENGINE_CLASS_VIDEO: 191*991b4de3SMatt Roper * 192*991b4de3SMatt Roper * Video engines (also referred to as "bit stream decode" (BSD) or 193*991b4de3SMatt Roper * "vdbox") support instructions that perform fixed-function media 194*991b4de3SMatt Roper * decode and encode. 195*991b4de3SMatt Roper */ 1961803fcbcSTvrtko Ursulin I915_ENGINE_CLASS_VIDEO = 2, 197*991b4de3SMatt Roper 198*991b4de3SMatt Roper /** 199*991b4de3SMatt Roper * @I915_ENGINE_CLASS_VIDEO_ENHANCE: 200*991b4de3SMatt Roper * 201*991b4de3SMatt Roper * Video enhancement engines (also referred to as "vebox") support 202*991b4de3SMatt Roper * instructions related to image enhancement. 203*991b4de3SMatt Roper */ 2041803fcbcSTvrtko Ursulin I915_ENGINE_CLASS_VIDEO_ENHANCE = 3, 2051803fcbcSTvrtko Ursulin 206*991b4de3SMatt Roper /* Values in this enum should be kept compact. */ 207be03564bSChris Wilson 208*991b4de3SMatt Roper /** 209*991b4de3SMatt Roper * @I915_ENGINE_CLASS_INVALID: 210*991b4de3SMatt Roper * 211*991b4de3SMatt Roper * Placeholder value to represent an invalid engine class assignment. 212*991b4de3SMatt Roper */ 2131803fcbcSTvrtko Ursulin I915_ENGINE_CLASS_INVALID = -1 2141803fcbcSTvrtko Ursulin }; 2151803fcbcSTvrtko Ursulin 216c94fde8fSMatt Atwood /** 217c94fde8fSMatt Atwood * struct i915_engine_class_instance - Engine class/instance identifier 218c94fde8fSMatt Atwood * 219d1172ab3SChris Wilson * There may be more than one engine fulfilling any role within the system. 220d1172ab3SChris Wilson * Each engine of a class is given a unique instance number and therefore 221d1172ab3SChris Wilson * any engine can be specified by its class:instance tuplet. APIs that allow 222d1172ab3SChris Wilson * access to any engine in the system will use struct i915_engine_class_instance 223d1172ab3SChris Wilson * for this identification. 224d1172ab3SChris Wilson */ 225d1172ab3SChris Wilson struct i915_engine_class_instance { 226c94fde8fSMatt Atwood /** 227c94fde8fSMatt Atwood * @engine_class: 228c94fde8fSMatt Atwood * 229c94fde8fSMatt Atwood * Engine class from enum drm_i915_gem_engine_class 230c94fde8fSMatt Atwood */ 231c94fde8fSMatt Atwood __u16 engine_class; 232976b55f0SChris Wilson #define I915_ENGINE_CLASS_INVALID_NONE -1 2336d06779eSChris Wilson #define I915_ENGINE_CLASS_INVALID_VIRTUAL -2 234c94fde8fSMatt Atwood 235c94fde8fSMatt Atwood /** 236c94fde8fSMatt Atwood * @engine_instance: 237c94fde8fSMatt Atwood * 238c94fde8fSMatt Atwood * Engine instance. 239c94fde8fSMatt Atwood */ 240c94fde8fSMatt Atwood __u16 engine_instance; 241d1172ab3SChris Wilson }; 242d1172ab3SChris Wilson 243b46a33e2STvrtko Ursulin /** 244b46a33e2STvrtko Ursulin * DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915 245b46a33e2STvrtko Ursulin * 246b46a33e2STvrtko Ursulin */ 247b46a33e2STvrtko Ursulin 248b46a33e2STvrtko Ursulin enum drm_i915_pmu_engine_sample { 249b46a33e2STvrtko Ursulin I915_SAMPLE_BUSY = 0, 250b46a33e2STvrtko Ursulin I915_SAMPLE_WAIT = 1, 251b552ae44STvrtko Ursulin I915_SAMPLE_SEMA = 2 252b46a33e2STvrtko Ursulin }; 253b46a33e2STvrtko Ursulin 254b46a33e2STvrtko Ursulin #define I915_PMU_SAMPLE_BITS (4) 255b46a33e2STvrtko Ursulin #define I915_PMU_SAMPLE_MASK (0xf) 256b46a33e2STvrtko Ursulin #define I915_PMU_SAMPLE_INSTANCE_BITS (8) 257b46a33e2STvrtko Ursulin #define I915_PMU_CLASS_SHIFT \ 258b46a33e2STvrtko Ursulin (I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS) 259b46a33e2STvrtko Ursulin 260b46a33e2STvrtko Ursulin #define __I915_PMU_ENGINE(class, instance, sample) \ 261b46a33e2STvrtko Ursulin ((class) << I915_PMU_CLASS_SHIFT | \ 262b46a33e2STvrtko Ursulin (instance) << I915_PMU_SAMPLE_BITS | \ 263b46a33e2STvrtko Ursulin (sample)) 264b46a33e2STvrtko Ursulin 265b46a33e2STvrtko Ursulin #define I915_PMU_ENGINE_BUSY(class, instance) \ 266b46a33e2STvrtko Ursulin __I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY) 267b46a33e2STvrtko Ursulin 268b46a33e2STvrtko Ursulin #define I915_PMU_ENGINE_WAIT(class, instance) \ 269b46a33e2STvrtko Ursulin __I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT) 270b46a33e2STvrtko Ursulin 271b46a33e2STvrtko Ursulin #define I915_PMU_ENGINE_SEMA(class, instance) \ 272b46a33e2STvrtko Ursulin __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA) 273b46a33e2STvrtko Ursulin 274b46a33e2STvrtko Ursulin #define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x)) 275b46a33e2STvrtko Ursulin 276b46a33e2STvrtko Ursulin #define I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0) 277b46a33e2STvrtko Ursulin #define I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1) 2780cd4684dSTvrtko Ursulin #define I915_PMU_INTERRUPTS __I915_PMU_OTHER(2) 2796060b6aeSTvrtko Ursulin #define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3) 2808c3b1ba0SChris Wilson #define I915_PMU_SOFTWARE_GT_AWAKE_TIME __I915_PMU_OTHER(4) 2816060b6aeSTvrtko Ursulin 282348fb0cbSTvrtko Ursulin #define I915_PMU_LAST /* Deprecated - do not use */ I915_PMU_RC6_RESIDENCY 283b46a33e2STvrtko Ursulin 284718dceddSDavid Howells /* Each region is a minimum of 16k, and there are at most 255 of them. 285718dceddSDavid Howells */ 286718dceddSDavid Howells #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use 287718dceddSDavid Howells * of chars for next/prev indices */ 288718dceddSDavid Howells #define I915_LOG_MIN_TEX_REGION_SIZE 14 289718dceddSDavid Howells 290718dceddSDavid Howells typedef struct _drm_i915_init { 291718dceddSDavid Howells enum { 292718dceddSDavid Howells I915_INIT_DMA = 0x01, 293718dceddSDavid Howells I915_CLEANUP_DMA = 0x02, 294718dceddSDavid Howells I915_RESUME_DMA = 0x03 295718dceddSDavid Howells } func; 296718dceddSDavid Howells unsigned int mmio_offset; 297718dceddSDavid Howells int sarea_priv_offset; 298718dceddSDavid Howells unsigned int ring_start; 299718dceddSDavid Howells unsigned int ring_end; 300718dceddSDavid Howells unsigned int ring_size; 301718dceddSDavid Howells unsigned int front_offset; 302718dceddSDavid Howells unsigned int back_offset; 303718dceddSDavid Howells unsigned int depth_offset; 304718dceddSDavid Howells unsigned int w; 305718dceddSDavid Howells unsigned int h; 306718dceddSDavid Howells unsigned int pitch; 307718dceddSDavid Howells unsigned int pitch_bits; 308718dceddSDavid Howells unsigned int back_pitch; 309718dceddSDavid Howells unsigned int depth_pitch; 310718dceddSDavid Howells unsigned int cpp; 311718dceddSDavid Howells unsigned int chipset; 312718dceddSDavid Howells } drm_i915_init_t; 313718dceddSDavid Howells 314718dceddSDavid Howells typedef struct _drm_i915_sarea { 315718dceddSDavid Howells struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 316718dceddSDavid Howells int last_upload; /* last time texture was uploaded */ 317718dceddSDavid Howells int last_enqueue; /* last time a buffer was enqueued */ 318718dceddSDavid Howells int last_dispatch; /* age of the most recently dispatched buffer */ 319718dceddSDavid Howells int ctxOwner; /* last context to upload state */ 320718dceddSDavid Howells int texAge; 321718dceddSDavid Howells int pf_enabled; /* is pageflipping allowed? */ 322718dceddSDavid Howells int pf_active; 323718dceddSDavid Howells int pf_current_page; /* which buffer is being displayed? */ 324718dceddSDavid Howells int perf_boxes; /* performance boxes to be displayed */ 325718dceddSDavid Howells int width, height; /* screen size in pixels */ 326718dceddSDavid Howells 327718dceddSDavid Howells drm_handle_t front_handle; 328718dceddSDavid Howells int front_offset; 329718dceddSDavid Howells int front_size; 330718dceddSDavid Howells 331718dceddSDavid Howells drm_handle_t back_handle; 332718dceddSDavid Howells int back_offset; 333718dceddSDavid Howells int back_size; 334718dceddSDavid Howells 335718dceddSDavid Howells drm_handle_t depth_handle; 336718dceddSDavid Howells int depth_offset; 337718dceddSDavid Howells int depth_size; 338718dceddSDavid Howells 339718dceddSDavid Howells drm_handle_t tex_handle; 340718dceddSDavid Howells int tex_offset; 341718dceddSDavid Howells int tex_size; 342718dceddSDavid Howells int log_tex_granularity; 343718dceddSDavid Howells int pitch; 344718dceddSDavid Howells int rotation; /* 0, 90, 180 or 270 */ 345718dceddSDavid Howells int rotated_offset; 346718dceddSDavid Howells int rotated_size; 347718dceddSDavid Howells int rotated_pitch; 348718dceddSDavid Howells int virtualX, virtualY; 349718dceddSDavid Howells 350718dceddSDavid Howells unsigned int front_tiled; 351718dceddSDavid Howells unsigned int back_tiled; 352718dceddSDavid Howells unsigned int depth_tiled; 353718dceddSDavid Howells unsigned int rotated_tiled; 354718dceddSDavid Howells unsigned int rotated2_tiled; 355718dceddSDavid Howells 356718dceddSDavid Howells int pipeA_x; 357718dceddSDavid Howells int pipeA_y; 358718dceddSDavid Howells int pipeA_w; 359718dceddSDavid Howells int pipeA_h; 360718dceddSDavid Howells int pipeB_x; 361718dceddSDavid Howells int pipeB_y; 362718dceddSDavid Howells int pipeB_w; 363718dceddSDavid Howells int pipeB_h; 364718dceddSDavid Howells 365718dceddSDavid Howells /* fill out some space for old userspace triple buffer */ 366718dceddSDavid Howells drm_handle_t unused_handle; 367718dceddSDavid Howells __u32 unused1, unused2, unused3; 368718dceddSDavid Howells 369718dceddSDavid Howells /* buffer object handles for static buffers. May change 370718dceddSDavid Howells * over the lifetime of the client. 371718dceddSDavid Howells */ 372718dceddSDavid Howells __u32 front_bo_handle; 373718dceddSDavid Howells __u32 back_bo_handle; 374718dceddSDavid Howells __u32 unused_bo_handle; 375718dceddSDavid Howells __u32 depth_bo_handle; 376718dceddSDavid Howells 377718dceddSDavid Howells } drm_i915_sarea_t; 378718dceddSDavid Howells 379718dceddSDavid Howells /* due to userspace building against these headers we need some compat here */ 380718dceddSDavid Howells #define planeA_x pipeA_x 381718dceddSDavid Howells #define planeA_y pipeA_y 382718dceddSDavid Howells #define planeA_w pipeA_w 383718dceddSDavid Howells #define planeA_h pipeA_h 384718dceddSDavid Howells #define planeB_x pipeB_x 385718dceddSDavid Howells #define planeB_y pipeB_y 386718dceddSDavid Howells #define planeB_w pipeB_w 387718dceddSDavid Howells #define planeB_h pipeB_h 388718dceddSDavid Howells 389718dceddSDavid Howells /* Flags for perf_boxes 390718dceddSDavid Howells */ 391718dceddSDavid Howells #define I915_BOX_RING_EMPTY 0x1 392718dceddSDavid Howells #define I915_BOX_FLIP 0x2 393718dceddSDavid Howells #define I915_BOX_WAIT 0x4 394718dceddSDavid Howells #define I915_BOX_TEXTURE_LOAD 0x8 395718dceddSDavid Howells #define I915_BOX_LOST_CONTEXT 0x10 396718dceddSDavid Howells 39721631f10SDamien Lespiau /* 39821631f10SDamien Lespiau * i915 specific ioctls. 39921631f10SDamien Lespiau * 40021631f10SDamien Lespiau * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie 40121631f10SDamien Lespiau * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset 40221631f10SDamien Lespiau * against DRM_COMMAND_BASE and should be between [0x0, 0x60). 403718dceddSDavid Howells */ 404718dceddSDavid Howells #define DRM_I915_INIT 0x00 405718dceddSDavid Howells #define DRM_I915_FLUSH 0x01 406718dceddSDavid Howells #define DRM_I915_FLIP 0x02 407718dceddSDavid Howells #define DRM_I915_BATCHBUFFER 0x03 408718dceddSDavid Howells #define DRM_I915_IRQ_EMIT 0x04 409718dceddSDavid Howells #define DRM_I915_IRQ_WAIT 0x05 410718dceddSDavid Howells #define DRM_I915_GETPARAM 0x06 411718dceddSDavid Howells #define DRM_I915_SETPARAM 0x07 412718dceddSDavid Howells #define DRM_I915_ALLOC 0x08 413718dceddSDavid Howells #define DRM_I915_FREE 0x09 414718dceddSDavid Howells #define DRM_I915_INIT_HEAP 0x0a 415718dceddSDavid Howells #define DRM_I915_CMDBUFFER 0x0b 416718dceddSDavid Howells #define DRM_I915_DESTROY_HEAP 0x0c 417718dceddSDavid Howells #define DRM_I915_SET_VBLANK_PIPE 0x0d 418718dceddSDavid Howells #define DRM_I915_GET_VBLANK_PIPE 0x0e 419718dceddSDavid Howells #define DRM_I915_VBLANK_SWAP 0x0f 420718dceddSDavid Howells #define DRM_I915_HWS_ADDR 0x11 421718dceddSDavid Howells #define DRM_I915_GEM_INIT 0x13 422718dceddSDavid Howells #define DRM_I915_GEM_EXECBUFFER 0x14 423718dceddSDavid Howells #define DRM_I915_GEM_PIN 0x15 424718dceddSDavid Howells #define DRM_I915_GEM_UNPIN 0x16 425718dceddSDavid Howells #define DRM_I915_GEM_BUSY 0x17 426718dceddSDavid Howells #define DRM_I915_GEM_THROTTLE 0x18 427718dceddSDavid Howells #define DRM_I915_GEM_ENTERVT 0x19 428718dceddSDavid Howells #define DRM_I915_GEM_LEAVEVT 0x1a 429718dceddSDavid Howells #define DRM_I915_GEM_CREATE 0x1b 430718dceddSDavid Howells #define DRM_I915_GEM_PREAD 0x1c 431718dceddSDavid Howells #define DRM_I915_GEM_PWRITE 0x1d 432718dceddSDavid Howells #define DRM_I915_GEM_MMAP 0x1e 433718dceddSDavid Howells #define DRM_I915_GEM_SET_DOMAIN 0x1f 434718dceddSDavid Howells #define DRM_I915_GEM_SW_FINISH 0x20 435718dceddSDavid Howells #define DRM_I915_GEM_SET_TILING 0x21 436718dceddSDavid Howells #define DRM_I915_GEM_GET_TILING 0x22 437718dceddSDavid Howells #define DRM_I915_GEM_GET_APERTURE 0x23 438718dceddSDavid Howells #define DRM_I915_GEM_MMAP_GTT 0x24 439718dceddSDavid Howells #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 440718dceddSDavid Howells #define DRM_I915_GEM_MADVISE 0x26 441718dceddSDavid Howells #define DRM_I915_OVERLAY_PUT_IMAGE 0x27 442718dceddSDavid Howells #define DRM_I915_OVERLAY_ATTRS 0x28 443718dceddSDavid Howells #define DRM_I915_GEM_EXECBUFFER2 0x29 444fec0445cSChris Wilson #define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2 445718dceddSDavid Howells #define DRM_I915_GET_SPRITE_COLORKEY 0x2a 446718dceddSDavid Howells #define DRM_I915_SET_SPRITE_COLORKEY 0x2b 447718dceddSDavid Howells #define DRM_I915_GEM_WAIT 0x2c 448718dceddSDavid Howells #define DRM_I915_GEM_CONTEXT_CREATE 0x2d 449718dceddSDavid Howells #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e 450718dceddSDavid Howells #define DRM_I915_GEM_SET_CACHING 0x2f 451718dceddSDavid Howells #define DRM_I915_GEM_GET_CACHING 0x30 452718dceddSDavid Howells #define DRM_I915_REG_READ 0x31 453b6359918SMika Kuoppala #define DRM_I915_GET_RESET_STATS 0x32 4545cc9ed4bSChris Wilson #define DRM_I915_GEM_USERPTR 0x33 455c9dc0f35SChris Wilson #define DRM_I915_GEM_CONTEXT_GETPARAM 0x34 456c9dc0f35SChris Wilson #define DRM_I915_GEM_CONTEXT_SETPARAM 0x35 457eec688e1SRobert Bragg #define DRM_I915_PERF_OPEN 0x36 458f89823c2SLionel Landwerlin #define DRM_I915_PERF_ADD_CONFIG 0x37 459f89823c2SLionel Landwerlin #define DRM_I915_PERF_REMOVE_CONFIG 0x38 460a446ae2cSLionel Landwerlin #define DRM_I915_QUERY 0x39 4617f3f317aSChris Wilson #define DRM_I915_GEM_VM_CREATE 0x3a 4627f3f317aSChris Wilson #define DRM_I915_GEM_VM_DESTROY 0x3b 463ebcb4029SMatthew Auld #define DRM_I915_GEM_CREATE_EXT 0x3c 464be03564bSChris Wilson /* Must be kept compact -- no holes */ 465718dceddSDavid Howells 466718dceddSDavid Howells #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 467718dceddSDavid Howells #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 468718dceddSDavid Howells #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) 469718dceddSDavid Howells #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 470718dceddSDavid Howells #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 471718dceddSDavid Howells #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 472718dceddSDavid Howells #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 473718dceddSDavid Howells #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 474718dceddSDavid Howells #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 475718dceddSDavid Howells #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 476718dceddSDavid Howells #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 477718dceddSDavid Howells #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 478718dceddSDavid Howells #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 479718dceddSDavid Howells #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 480718dceddSDavid Howells #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 481718dceddSDavid Howells #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 482718dceddSDavid Howells #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) 483718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 484718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 485718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 486fec0445cSChris Wilson #define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2) 487718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 488718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 489718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 490718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) 491718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) 492718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 493718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 494718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 495718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 496ebcb4029SMatthew Auld #define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE_EXT, struct drm_i915_gem_create_ext) 497718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 498718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 499718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 500718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 501cc662126SAbdiel Janulgue #define DRM_IOCTL_I915_GEM_MMAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_offset) 502718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 503718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 504718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 505718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 506718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 507718dceddSDavid Howells #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 508718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 509718dceddSDavid Howells #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) 510718dceddSDavid Howells #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 511718dceddSDavid Howells #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 5122c60fae1STommi Rantala #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 513718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) 514718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) 515b9171541SChris Wilson #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext) 516718dceddSDavid Howells #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) 517718dceddSDavid Howells #define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) 518b6359918SMika Kuoppala #define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats) 5195cc9ed4bSChris Wilson #define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr) 520c9dc0f35SChris Wilson #define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param) 521c9dc0f35SChris Wilson #define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param) 522eec688e1SRobert Bragg #define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param) 523f89823c2SLionel Landwerlin #define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config) 524f89823c2SLionel Landwerlin #define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64) 525a446ae2cSLionel Landwerlin #define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query) 5267f3f317aSChris Wilson #define DRM_IOCTL_I915_GEM_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control) 5277f3f317aSChris Wilson #define DRM_IOCTL_I915_GEM_VM_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control) 528718dceddSDavid Howells 529718dceddSDavid Howells /* Allow drivers to submit batchbuffers directly to hardware, relying 530718dceddSDavid Howells * on the security mechanisms provided by hardware. 531718dceddSDavid Howells */ 532718dceddSDavid Howells typedef struct drm_i915_batchbuffer { 533718dceddSDavid Howells int start; /* agp offset */ 534718dceddSDavid Howells int used; /* nr bytes in use */ 535718dceddSDavid Howells int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 536718dceddSDavid Howells int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 537718dceddSDavid Howells int num_cliprects; /* mulitpass with multiple cliprects? */ 538718dceddSDavid Howells struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 539718dceddSDavid Howells } drm_i915_batchbuffer_t; 540718dceddSDavid Howells 541718dceddSDavid Howells /* As above, but pass a pointer to userspace buffer which can be 542718dceddSDavid Howells * validated by the kernel prior to sending to hardware. 543718dceddSDavid Howells */ 544718dceddSDavid Howells typedef struct _drm_i915_cmdbuffer { 545718dceddSDavid Howells char __user *buf; /* pointer to userspace command buffer */ 546718dceddSDavid Howells int sz; /* nr bytes in buf */ 547718dceddSDavid Howells int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 548718dceddSDavid Howells int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 549718dceddSDavid Howells int num_cliprects; /* mulitpass with multiple cliprects? */ 550718dceddSDavid Howells struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 551718dceddSDavid Howells } drm_i915_cmdbuffer_t; 552718dceddSDavid Howells 553718dceddSDavid Howells /* Userspace can request & wait on irq's: 554718dceddSDavid Howells */ 555718dceddSDavid Howells typedef struct drm_i915_irq_emit { 556718dceddSDavid Howells int __user *irq_seq; 557718dceddSDavid Howells } drm_i915_irq_emit_t; 558718dceddSDavid Howells 559718dceddSDavid Howells typedef struct drm_i915_irq_wait { 560718dceddSDavid Howells int irq_seq; 561718dceddSDavid Howells } drm_i915_irq_wait_t; 562718dceddSDavid Howells 5634bdafb9dSChris Wilson /* 5644bdafb9dSChris Wilson * Different modes of per-process Graphics Translation Table, 5654bdafb9dSChris Wilson * see I915_PARAM_HAS_ALIASING_PPGTT 5664bdafb9dSChris Wilson */ 5674bdafb9dSChris Wilson #define I915_GEM_PPGTT_NONE 0 5684bdafb9dSChris Wilson #define I915_GEM_PPGTT_ALIASING 1 5694bdafb9dSChris Wilson #define I915_GEM_PPGTT_FULL 2 5704bdafb9dSChris Wilson 571718dceddSDavid Howells /* Ioctl to query kernel params: 572718dceddSDavid Howells */ 573718dceddSDavid Howells #define I915_PARAM_IRQ_ACTIVE 1 574718dceddSDavid Howells #define I915_PARAM_ALLOW_BATCHBUFFER 2 575718dceddSDavid Howells #define I915_PARAM_LAST_DISPATCH 3 576718dceddSDavid Howells #define I915_PARAM_CHIPSET_ID 4 577718dceddSDavid Howells #define I915_PARAM_HAS_GEM 5 578718dceddSDavid Howells #define I915_PARAM_NUM_FENCES_AVAIL 6 579718dceddSDavid Howells #define I915_PARAM_HAS_OVERLAY 7 580718dceddSDavid Howells #define I915_PARAM_HAS_PAGEFLIPPING 8 581718dceddSDavid Howells #define I915_PARAM_HAS_EXECBUF2 9 582718dceddSDavid Howells #define I915_PARAM_HAS_BSD 10 583718dceddSDavid Howells #define I915_PARAM_HAS_BLT 11 584718dceddSDavid Howells #define I915_PARAM_HAS_RELAXED_FENCING 12 585718dceddSDavid Howells #define I915_PARAM_HAS_COHERENT_RINGS 13 586718dceddSDavid Howells #define I915_PARAM_HAS_EXEC_CONSTANTS 14 587718dceddSDavid Howells #define I915_PARAM_HAS_RELAXED_DELTA 15 588718dceddSDavid Howells #define I915_PARAM_HAS_GEN7_SOL_RESET 16 589718dceddSDavid Howells #define I915_PARAM_HAS_LLC 17 590718dceddSDavid Howells #define I915_PARAM_HAS_ALIASING_PPGTT 18 591718dceddSDavid Howells #define I915_PARAM_HAS_WAIT_TIMEOUT 19 592718dceddSDavid Howells #define I915_PARAM_HAS_SEMAPHORES 20 593718dceddSDavid Howells #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 594a1f2cc73SXiang, Haihao #define I915_PARAM_HAS_VEBOX 22 595c2fb7916SDaniel Vetter #define I915_PARAM_HAS_SECURE_BATCHES 23 596b45305fcSDaniel Vetter #define I915_PARAM_HAS_PINNED_BATCHES 24 597ed5982e6SDaniel Vetter #define I915_PARAM_HAS_EXEC_NO_RELOC 25 598eef90ccbSChris Wilson #define I915_PARAM_HAS_EXEC_HANDLE_LUT 26 599651d794fSChris Wilson #define I915_PARAM_HAS_WT 27 600d728c8efSBrad Volkin #define I915_PARAM_CMD_PARSER_VERSION 28 6016a2c4232SChris Wilson #define I915_PARAM_HAS_COHERENT_PHYS_GTT 29 6021816f923SAkash Goel #define I915_PARAM_MMAP_VERSION 30 60308e16dc8SZhipeng Gong #define I915_PARAM_HAS_BSD2 31 60427cd4461SNeil Roberts #define I915_PARAM_REVISION 32 605a1559ffeSJeff McGee #define I915_PARAM_SUBSLICE_TOTAL 33 606a1559ffeSJeff McGee #define I915_PARAM_EU_TOTAL 34 60749e4d842SChris Wilson #define I915_PARAM_HAS_GPU_RESET 35 608a9ed33caSAbdiel Janulgue #define I915_PARAM_HAS_RESOURCE_STREAMER 36 609506a8e87SChris Wilson #define I915_PARAM_HAS_EXEC_SOFTPIN 37 61037f501afSarun.siluvery@linux.intel.com #define I915_PARAM_HAS_POOLED_EU 38 61137f501afSarun.siluvery@linux.intel.com #define I915_PARAM_MIN_EU_IN_POOL 39 6124cc69075SChris Wilson #define I915_PARAM_MMAP_GTT_VERSION 40 613718dceddSDavid Howells 614bf64e0b0SChris Wilson /* 615bf64e0b0SChris Wilson * Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution 6160de9136dSChris Wilson * priorities and the driver will attempt to execute batches in priority order. 617bf64e0b0SChris Wilson * The param returns a capability bitmask, nonzero implies that the scheduler 618bf64e0b0SChris Wilson * is enabled, with different features present according to the mask. 619ac14fbd4SChris Wilson * 620ac14fbd4SChris Wilson * The initial priority for each batch is supplied by the context and is 621ac14fbd4SChris Wilson * controlled via I915_CONTEXT_PARAM_PRIORITY. 6220de9136dSChris Wilson */ 6230de9136dSChris Wilson #define I915_PARAM_HAS_SCHEDULER 41 624bf64e0b0SChris Wilson #define I915_SCHEDULER_CAP_ENABLED (1ul << 0) 625bf64e0b0SChris Wilson #define I915_SCHEDULER_CAP_PRIORITY (1ul << 1) 626bf64e0b0SChris Wilson #define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2) 627e8861964SChris Wilson #define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3) 628bf73fc0fSChris Wilson #define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4) 629ee242ca7SMatthew Brost /* 630ee242ca7SMatthew Brost * Indicates the 2k user priority levels are statically mapped into 3 buckets as 631ee242ca7SMatthew Brost * follows: 632ee242ca7SMatthew Brost * 633ee242ca7SMatthew Brost * -1k to -1 Low priority 634ee242ca7SMatthew Brost * 0 Normal priority 635ee242ca7SMatthew Brost * 1 to 1k Highest priority 636ee242ca7SMatthew Brost */ 637ee242ca7SMatthew Brost #define I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP (1ul << 5) 638bf64e0b0SChris Wilson 6395464cd65SAnusha Srivatsa #define I915_PARAM_HUC_STATUS 42 6400de9136dSChris Wilson 64177ae9957SChris Wilson /* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of 64277ae9957SChris Wilson * synchronisation with implicit fencing on individual objects. 64377ae9957SChris Wilson * See EXEC_OBJECT_ASYNC. 64477ae9957SChris Wilson */ 64577ae9957SChris Wilson #define I915_PARAM_HAS_EXEC_ASYNC 43 64677ae9957SChris Wilson 647fec0445cSChris Wilson /* Query whether DRM_I915_GEM_EXECBUFFER2 supports explicit fence support - 648fec0445cSChris Wilson * both being able to pass in a sync_file fd to wait upon before executing, 649fec0445cSChris Wilson * and being able to return a new sync_file fd that is signaled when the 650fec0445cSChris Wilson * current request is complete. See I915_EXEC_FENCE_IN and I915_EXEC_FENCE_OUT. 651fec0445cSChris Wilson */ 652fec0445cSChris Wilson #define I915_PARAM_HAS_EXEC_FENCE 44 653fec0445cSChris Wilson 654b0fd47adSChris Wilson /* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to capture 655b0fd47adSChris Wilson * user specified bufffers for post-mortem debugging of GPU hangs. See 656b0fd47adSChris Wilson * EXEC_OBJECT_CAPTURE. 657b0fd47adSChris Wilson */ 658b0fd47adSChris Wilson #define I915_PARAM_HAS_EXEC_CAPTURE 45 659b0fd47adSChris Wilson 6607fed555cSRobert Bragg #define I915_PARAM_SLICE_MASK 46 6617fed555cSRobert Bragg 662f5320233SRobert Bragg /* Assuming it's uniform for each slice, this queries the mask of subslices 663f5320233SRobert Bragg * per-slice for this system. 664f5320233SRobert Bragg */ 665f5320233SRobert Bragg #define I915_PARAM_SUBSLICE_MASK 47 666f5320233SRobert Bragg 6671a71cf2fSChris Wilson /* 6681a71cf2fSChris Wilson * Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying the batch buffer 6691a71cf2fSChris Wilson * as the first execobject as opposed to the last. See I915_EXEC_BATCH_FIRST. 6701a71cf2fSChris Wilson */ 6711a71cf2fSChris Wilson #define I915_PARAM_HAS_EXEC_BATCH_FIRST 48 6721a71cf2fSChris Wilson 673cf6e7bacSJason Ekstrand /* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of 674cf6e7bacSJason Ekstrand * drm_i915_gem_exec_fence structures. See I915_EXEC_FENCE_ARRAY. 675cf6e7bacSJason Ekstrand */ 676cf6e7bacSJason Ekstrand #define I915_PARAM_HAS_EXEC_FENCE_ARRAY 49 677cf6e7bacSJason Ekstrand 678d2b4b979SChris Wilson /* 679d2b4b979SChris Wilson * Query whether every context (both per-file default and user created) is 680d2b4b979SChris Wilson * isolated (insofar as HW supports). If this parameter is not true, then 681d2b4b979SChris Wilson * freshly created contexts may inherit values from an existing context, 682d2b4b979SChris Wilson * rather than default HW values. If true, it also ensures (insofar as HW 683d2b4b979SChris Wilson * supports) that all state set by this context will not leak to any other 684d2b4b979SChris Wilson * context. 685d2b4b979SChris Wilson * 686d2b4b979SChris Wilson * As not every engine across every gen support contexts, the returned 687d2b4b979SChris Wilson * value reports the support of context isolation for individual engines by 688d2b4b979SChris Wilson * returning a bitmask of each engine class set to true if that class supports 689d2b4b979SChris Wilson * isolation. 690d2b4b979SChris Wilson */ 691d2b4b979SChris Wilson #define I915_PARAM_HAS_CONTEXT_ISOLATION 50 692d2b4b979SChris Wilson 693dab91783SLionel Landwerlin /* Frequency of the command streamer timestamps given by the *_TIMESTAMP 694dab91783SLionel Landwerlin * registers. This used to be fixed per platform but from CNL onwards, this 695dab91783SLionel Landwerlin * might vary depending on the parts. 696dab91783SLionel Landwerlin */ 697dab91783SLionel Landwerlin #define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51 698dab91783SLionel Landwerlin 699900ccf30SChris Wilson /* 700900ccf30SChris Wilson * Once upon a time we supposed that writes through the GGTT would be 701900ccf30SChris Wilson * immediately in physical memory (once flushed out of the CPU path). However, 702900ccf30SChris Wilson * on a few different processors and chipsets, this is not necessarily the case 703900ccf30SChris Wilson * as the writes appear to be buffered internally. Thus a read of the backing 704900ccf30SChris Wilson * storage (physical memory) via a different path (with different physical tags 705900ccf30SChris Wilson * to the indirect write via the GGTT) will see stale values from before 706900ccf30SChris Wilson * the GGTT write. Inside the kernel, we can for the most part keep track of 707900ccf30SChris Wilson * the different read/write domains in use (e.g. set-domain), but the assumption 708900ccf30SChris Wilson * of coherency is baked into the ABI, hence reporting its true state in this 709900ccf30SChris Wilson * parameter. 710900ccf30SChris Wilson * 711900ccf30SChris Wilson * Reports true when writes via mmap_gtt are immediately visible following an 712900ccf30SChris Wilson * lfence to flush the WCB. 713900ccf30SChris Wilson * 714900ccf30SChris Wilson * Reports false when writes via mmap_gtt are indeterminately delayed in an in 715900ccf30SChris Wilson * internal buffer and are _not_ immediately visible to third parties accessing 716900ccf30SChris Wilson * directly via mmap_cpu/mmap_wc. Use of mmap_gtt as part of an IPC 717900ccf30SChris Wilson * communications channel when reporting false is strongly disadvised. 718900ccf30SChris Wilson */ 719900ccf30SChris Wilson #define I915_PARAM_MMAP_GTT_COHERENT 52 720900ccf30SChris Wilson 721a88b6e4cSChris Wilson /* 722a88b6e4cSChris Wilson * Query whether DRM_I915_GEM_EXECBUFFER2 supports coordination of parallel 723a88b6e4cSChris Wilson * execution through use of explicit fence support. 724a88b6e4cSChris Wilson * See I915_EXEC_FENCE_OUT and I915_EXEC_FENCE_SUBMIT. 725a88b6e4cSChris Wilson */ 726a88b6e4cSChris Wilson #define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53 727b8d49f28SLionel Landwerlin 728b8d49f28SLionel Landwerlin /* 729b8d49f28SLionel Landwerlin * Revision of the i915-perf uAPI. The value returned helps determine what 730b8d49f28SLionel Landwerlin * i915-perf features are available. See drm_i915_perf_property_id. 731b8d49f28SLionel Landwerlin */ 732b8d49f28SLionel Landwerlin #define I915_PARAM_PERF_REVISION 54 733b8d49f28SLionel Landwerlin 73413149e8bSLionel Landwerlin /* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of 73513149e8bSLionel Landwerlin * timeline syncobj through drm_i915_gem_execbuffer_ext_timeline_fences. See 73613149e8bSLionel Landwerlin * I915_EXEC_USE_EXTENSIONS. 73713149e8bSLionel Landwerlin */ 73813149e8bSLionel Landwerlin #define I915_PARAM_HAS_EXEC_TIMELINE_FENCES 55 73913149e8bSLionel Landwerlin 740b65a9489SChris Wilson /* Query if the kernel supports the I915_USERPTR_PROBE flag. */ 741b65a9489SChris Wilson #define I915_PARAM_HAS_USERPTR_PROBE 56 742b65a9489SChris Wilson 743be03564bSChris Wilson /* Must be kept compact -- no holes and well documented */ 744be03564bSChris Wilson 745718dceddSDavid Howells typedef struct drm_i915_getparam { 74616f7249dSArtem Savkov __s32 param; 747346add78SDaniel Vetter /* 748346add78SDaniel Vetter * WARNING: Using pointers instead of fixed-size u64 means we need to write 749346add78SDaniel Vetter * compat32 code. Don't repeat this mistake. 750346add78SDaniel Vetter */ 751718dceddSDavid Howells int __user *value; 752718dceddSDavid Howells } drm_i915_getparam_t; 753718dceddSDavid Howells 754718dceddSDavid Howells /* Ioctl to set kernel params: 755718dceddSDavid Howells */ 756718dceddSDavid Howells #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 757718dceddSDavid Howells #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 758718dceddSDavid Howells #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 759718dceddSDavid Howells #define I915_SETPARAM_NUM_USED_FENCES 4 760be03564bSChris Wilson /* Must be kept compact -- no holes */ 761718dceddSDavid Howells 762718dceddSDavid Howells typedef struct drm_i915_setparam { 763718dceddSDavid Howells int param; 764718dceddSDavid Howells int value; 765718dceddSDavid Howells } drm_i915_setparam_t; 766718dceddSDavid Howells 767718dceddSDavid Howells /* A memory manager for regions of shared memory: 768718dceddSDavid Howells */ 769718dceddSDavid Howells #define I915_MEM_REGION_AGP 1 770718dceddSDavid Howells 771718dceddSDavid Howells typedef struct drm_i915_mem_alloc { 772718dceddSDavid Howells int region; 773718dceddSDavid Howells int alignment; 774718dceddSDavid Howells int size; 775718dceddSDavid Howells int __user *region_offset; /* offset from start of fb or agp */ 776718dceddSDavid Howells } drm_i915_mem_alloc_t; 777718dceddSDavid Howells 778718dceddSDavid Howells typedef struct drm_i915_mem_free { 779718dceddSDavid Howells int region; 780718dceddSDavid Howells int region_offset; 781718dceddSDavid Howells } drm_i915_mem_free_t; 782718dceddSDavid Howells 783718dceddSDavid Howells typedef struct drm_i915_mem_init_heap { 784718dceddSDavid Howells int region; 785718dceddSDavid Howells int size; 786718dceddSDavid Howells int start; 787718dceddSDavid Howells } drm_i915_mem_init_heap_t; 788718dceddSDavid Howells 789718dceddSDavid Howells /* Allow memory manager to be torn down and re-initialized (eg on 790718dceddSDavid Howells * rotate): 791718dceddSDavid Howells */ 792718dceddSDavid Howells typedef struct drm_i915_mem_destroy_heap { 793718dceddSDavid Howells int region; 794718dceddSDavid Howells } drm_i915_mem_destroy_heap_t; 795718dceddSDavid Howells 796718dceddSDavid Howells /* Allow X server to configure which pipes to monitor for vblank signals 797718dceddSDavid Howells */ 798718dceddSDavid Howells #define DRM_I915_VBLANK_PIPE_A 1 799718dceddSDavid Howells #define DRM_I915_VBLANK_PIPE_B 2 800718dceddSDavid Howells 801718dceddSDavid Howells typedef struct drm_i915_vblank_pipe { 802718dceddSDavid Howells int pipe; 803718dceddSDavid Howells } drm_i915_vblank_pipe_t; 804718dceddSDavid Howells 805718dceddSDavid Howells /* Schedule buffer swap at given vertical blank: 806718dceddSDavid Howells */ 807718dceddSDavid Howells typedef struct drm_i915_vblank_swap { 808718dceddSDavid Howells drm_drawable_t drawable; 809718dceddSDavid Howells enum drm_vblank_seq_type seqtype; 810718dceddSDavid Howells unsigned int sequence; 811718dceddSDavid Howells } drm_i915_vblank_swap_t; 812718dceddSDavid Howells 813718dceddSDavid Howells typedef struct drm_i915_hws_addr { 814718dceddSDavid Howells __u64 addr; 815718dceddSDavid Howells } drm_i915_hws_addr_t; 816718dceddSDavid Howells 817718dceddSDavid Howells struct drm_i915_gem_init { 818718dceddSDavid Howells /** 819718dceddSDavid Howells * Beginning offset in the GTT to be managed by the DRM memory 820718dceddSDavid Howells * manager. 821718dceddSDavid Howells */ 822718dceddSDavid Howells __u64 gtt_start; 823718dceddSDavid Howells /** 824718dceddSDavid Howells * Ending offset in the GTT to be managed by the DRM memory 825718dceddSDavid Howells * manager. 826718dceddSDavid Howells */ 827718dceddSDavid Howells __u64 gtt_end; 828718dceddSDavid Howells }; 829718dceddSDavid Howells 830718dceddSDavid Howells struct drm_i915_gem_create { 831718dceddSDavid Howells /** 832718dceddSDavid Howells * Requested size for the object. 833718dceddSDavid Howells * 834718dceddSDavid Howells * The (page-aligned) allocated size for the object will be returned. 835718dceddSDavid Howells */ 836718dceddSDavid Howells __u64 size; 837718dceddSDavid Howells /** 838718dceddSDavid Howells * Returned handle for the object. 839718dceddSDavid Howells * 840718dceddSDavid Howells * Object handles are nonzero. 841718dceddSDavid Howells */ 842718dceddSDavid Howells __u32 handle; 843718dceddSDavid Howells __u32 pad; 844718dceddSDavid Howells }; 845718dceddSDavid Howells 846718dceddSDavid Howells struct drm_i915_gem_pread { 847718dceddSDavid Howells /** Handle for the object being read. */ 848718dceddSDavid Howells __u32 handle; 849718dceddSDavid Howells __u32 pad; 850718dceddSDavid Howells /** Offset into the object to read from */ 851718dceddSDavid Howells __u64 offset; 852718dceddSDavid Howells /** Length of data to read */ 853718dceddSDavid Howells __u64 size; 854718dceddSDavid Howells /** 855718dceddSDavid Howells * Pointer to write the data into. 856718dceddSDavid Howells * 857718dceddSDavid Howells * This is a fixed-size type for 32/64 compatibility. 858718dceddSDavid Howells */ 859718dceddSDavid Howells __u64 data_ptr; 860718dceddSDavid Howells }; 861718dceddSDavid Howells 862718dceddSDavid Howells struct drm_i915_gem_pwrite { 863718dceddSDavid Howells /** Handle for the object being written to. */ 864718dceddSDavid Howells __u32 handle; 865718dceddSDavid Howells __u32 pad; 866718dceddSDavid Howells /** Offset into the object to write to */ 867718dceddSDavid Howells __u64 offset; 868718dceddSDavid Howells /** Length of data to write */ 869718dceddSDavid Howells __u64 size; 870718dceddSDavid Howells /** 871718dceddSDavid Howells * Pointer to read the data from. 872718dceddSDavid Howells * 873718dceddSDavid Howells * This is a fixed-size type for 32/64 compatibility. 874718dceddSDavid Howells */ 875718dceddSDavid Howells __u64 data_ptr; 876718dceddSDavid Howells }; 877718dceddSDavid Howells 878718dceddSDavid Howells struct drm_i915_gem_mmap { 879718dceddSDavid Howells /** Handle for the object being mapped. */ 880718dceddSDavid Howells __u32 handle; 881718dceddSDavid Howells __u32 pad; 882718dceddSDavid Howells /** Offset in the object to map. */ 883718dceddSDavid Howells __u64 offset; 884718dceddSDavid Howells /** 885718dceddSDavid Howells * Length of data to map. 886718dceddSDavid Howells * 887718dceddSDavid Howells * The value will be page-aligned. 888718dceddSDavid Howells */ 889718dceddSDavid Howells __u64 size; 890718dceddSDavid Howells /** 891718dceddSDavid Howells * Returned pointer the data was mapped at. 892718dceddSDavid Howells * 893718dceddSDavid Howells * This is a fixed-size type for 32/64 compatibility. 894718dceddSDavid Howells */ 895718dceddSDavid Howells __u64 addr_ptr; 8961816f923SAkash Goel 8971816f923SAkash Goel /** 8981816f923SAkash Goel * Flags for extended behaviour. 8991816f923SAkash Goel * 9001816f923SAkash Goel * Added in version 2. 9011816f923SAkash Goel */ 9021816f923SAkash Goel __u64 flags; 9031816f923SAkash Goel #define I915_MMAP_WC 0x1 904718dceddSDavid Howells }; 905718dceddSDavid Howells 906718dceddSDavid Howells struct drm_i915_gem_mmap_gtt { 907718dceddSDavid Howells /** Handle for the object being mapped. */ 908718dceddSDavid Howells __u32 handle; 909718dceddSDavid Howells __u32 pad; 910718dceddSDavid Howells /** 911718dceddSDavid Howells * Fake offset to use for subsequent mmap call 912718dceddSDavid Howells * 913718dceddSDavid Howells * This is a fixed-size type for 32/64 compatibility. 914718dceddSDavid Howells */ 915718dceddSDavid Howells __u64 offset; 916718dceddSDavid Howells }; 917718dceddSDavid Howells 9187961c5b6SMaarten Lankhorst /** 9197961c5b6SMaarten Lankhorst * struct drm_i915_gem_mmap_offset - Retrieve an offset so we can mmap this buffer object. 9207961c5b6SMaarten Lankhorst * 9217961c5b6SMaarten Lankhorst * This struct is passed as argument to the `DRM_IOCTL_I915_GEM_MMAP_OFFSET` ioctl, 9227961c5b6SMaarten Lankhorst * and is used to retrieve the fake offset to mmap an object specified by &handle. 9237961c5b6SMaarten Lankhorst * 9247961c5b6SMaarten Lankhorst * The legacy way of using `DRM_IOCTL_I915_GEM_MMAP` is removed on gen12+. 9257961c5b6SMaarten Lankhorst * `DRM_IOCTL_I915_GEM_MMAP_GTT` is an older supported alias to this struct, but will behave 9267961c5b6SMaarten Lankhorst * as setting the &extensions to 0, and &flags to `I915_MMAP_OFFSET_GTT`. 9277961c5b6SMaarten Lankhorst */ 928cc662126SAbdiel Janulgue struct drm_i915_gem_mmap_offset { 9297961c5b6SMaarten Lankhorst /** @handle: Handle for the object being mapped. */ 930cc662126SAbdiel Janulgue __u32 handle; 9317961c5b6SMaarten Lankhorst /** @pad: Must be zero */ 932cc662126SAbdiel Janulgue __u32 pad; 933cc662126SAbdiel Janulgue /** 9347961c5b6SMaarten Lankhorst * @offset: The fake offset to use for subsequent mmap call 935cc662126SAbdiel Janulgue * 936cc662126SAbdiel Janulgue * This is a fixed-size type for 32/64 compatibility. 937cc662126SAbdiel Janulgue */ 938cc662126SAbdiel Janulgue __u64 offset; 939cc662126SAbdiel Janulgue 940cc662126SAbdiel Janulgue /** 9417961c5b6SMaarten Lankhorst * @flags: Flags for extended behaviour. 942cc662126SAbdiel Janulgue * 9437961c5b6SMaarten Lankhorst * It is mandatory that one of the `MMAP_OFFSET` types 9447961c5b6SMaarten Lankhorst * should be included: 9457961c5b6SMaarten Lankhorst * 9467961c5b6SMaarten Lankhorst * - `I915_MMAP_OFFSET_GTT`: Use mmap with the object bound to GTT. (Write-Combined) 9477961c5b6SMaarten Lankhorst * - `I915_MMAP_OFFSET_WC`: Use Write-Combined caching. 9487961c5b6SMaarten Lankhorst * - `I915_MMAP_OFFSET_WB`: Use Write-Back caching. 9497961c5b6SMaarten Lankhorst * - `I915_MMAP_OFFSET_FIXED`: Use object placement to determine caching. 9507961c5b6SMaarten Lankhorst * 9517961c5b6SMaarten Lankhorst * On devices with local memory `I915_MMAP_OFFSET_FIXED` is the only valid 9527961c5b6SMaarten Lankhorst * type. On devices without local memory, this caching mode is invalid. 9537961c5b6SMaarten Lankhorst * 9547961c5b6SMaarten Lankhorst * As caching mode when specifying `I915_MMAP_OFFSET_FIXED`, WC or WB will 9557961c5b6SMaarten Lankhorst * be used, depending on the object placement on creation. WB will be used 9567961c5b6SMaarten Lankhorst * when the object can only exist in system memory, WC otherwise. 957cc662126SAbdiel Janulgue */ 958cc662126SAbdiel Janulgue __u64 flags; 9597961c5b6SMaarten Lankhorst 960cc662126SAbdiel Janulgue #define I915_MMAP_OFFSET_GTT 0 961cc662126SAbdiel Janulgue #define I915_MMAP_OFFSET_WC 1 962cc662126SAbdiel Janulgue #define I915_MMAP_OFFSET_WB 2 963cc662126SAbdiel Janulgue #define I915_MMAP_OFFSET_UC 3 9647961c5b6SMaarten Lankhorst #define I915_MMAP_OFFSET_FIXED 4 965cc662126SAbdiel Janulgue 9667961c5b6SMaarten Lankhorst /** 9677961c5b6SMaarten Lankhorst * @extensions: Zero-terminated chain of extensions. 968cc662126SAbdiel Janulgue * 969cc662126SAbdiel Janulgue * No current extensions defined; mbz. 970cc662126SAbdiel Janulgue */ 971cc662126SAbdiel Janulgue __u64 extensions; 972cc662126SAbdiel Janulgue }; 973cc662126SAbdiel Janulgue 9743aa8c57fSMatthew Auld /** 9753aa8c57fSMatthew Auld * struct drm_i915_gem_set_domain - Adjust the objects write or read domain, in 9763aa8c57fSMatthew Auld * preparation for accessing the pages via some CPU domain. 9773aa8c57fSMatthew Auld * 9783aa8c57fSMatthew Auld * Specifying a new write or read domain will flush the object out of the 9793aa8c57fSMatthew Auld * previous domain(if required), before then updating the objects domain 9803aa8c57fSMatthew Auld * tracking with the new domain. 9813aa8c57fSMatthew Auld * 9823aa8c57fSMatthew Auld * Note this might involve waiting for the object first if it is still active on 9833aa8c57fSMatthew Auld * the GPU. 9843aa8c57fSMatthew Auld * 9853aa8c57fSMatthew Auld * Supported values for @read_domains and @write_domain: 9863aa8c57fSMatthew Auld * 9873aa8c57fSMatthew Auld * - I915_GEM_DOMAIN_WC: Uncached write-combined domain 9883aa8c57fSMatthew Auld * - I915_GEM_DOMAIN_CPU: CPU cache domain 9893aa8c57fSMatthew Auld * - I915_GEM_DOMAIN_GTT: Mappable aperture domain 9903aa8c57fSMatthew Auld * 9913aa8c57fSMatthew Auld * All other domains are rejected. 99281340cf3SMatthew Auld * 99381340cf3SMatthew Auld * Note that for discrete, starting from DG1, this is no longer supported, and 99481340cf3SMatthew Auld * is instead rejected. On such platforms the CPU domain is effectively static, 99581340cf3SMatthew Auld * where we also only support a single &drm_i915_gem_mmap_offset cache mode, 99681340cf3SMatthew Auld * which can't be set explicitly and instead depends on the object placements, 99781340cf3SMatthew Auld * as per the below. 99881340cf3SMatthew Auld * 99981340cf3SMatthew Auld * Implicit caching rules, starting from DG1: 100081340cf3SMatthew Auld * 100181340cf3SMatthew Auld * - If any of the object placements (see &drm_i915_gem_create_ext_memory_regions) 100281340cf3SMatthew Auld * contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and 100381340cf3SMatthew Auld * mapped as write-combined only. 100481340cf3SMatthew Auld * 100581340cf3SMatthew Auld * - Everything else is always allocated and mapped as write-back, with the 100681340cf3SMatthew Auld * guarantee that everything is also coherent with the GPU. 100781340cf3SMatthew Auld * 100881340cf3SMatthew Auld * Note that this is likely to change in the future again, where we might need 100981340cf3SMatthew Auld * more flexibility on future devices, so making this all explicit as part of a 101081340cf3SMatthew Auld * new &drm_i915_gem_create_ext extension is probable. 10113aa8c57fSMatthew Auld */ 1012718dceddSDavid Howells struct drm_i915_gem_set_domain { 10133aa8c57fSMatthew Auld /** @handle: Handle for the object. */ 1014718dceddSDavid Howells __u32 handle; 1015718dceddSDavid Howells 10163aa8c57fSMatthew Auld /** @read_domains: New read domains. */ 1017718dceddSDavid Howells __u32 read_domains; 1018718dceddSDavid Howells 10193aa8c57fSMatthew Auld /** 10203aa8c57fSMatthew Auld * @write_domain: New write domain. 10213aa8c57fSMatthew Auld * 10223aa8c57fSMatthew Auld * Note that having something in the write domain implies it's in the 10233aa8c57fSMatthew Auld * read domain, and only that read domain. 10243aa8c57fSMatthew Auld */ 1025718dceddSDavid Howells __u32 write_domain; 1026718dceddSDavid Howells }; 1027718dceddSDavid Howells 1028718dceddSDavid Howells struct drm_i915_gem_sw_finish { 1029718dceddSDavid Howells /** Handle for the object */ 1030718dceddSDavid Howells __u32 handle; 1031718dceddSDavid Howells }; 1032718dceddSDavid Howells 1033718dceddSDavid Howells struct drm_i915_gem_relocation_entry { 1034718dceddSDavid Howells /** 1035718dceddSDavid Howells * Handle of the buffer being pointed to by this relocation entry. 1036718dceddSDavid Howells * 1037718dceddSDavid Howells * It's appealing to make this be an index into the mm_validate_entry 1038718dceddSDavid Howells * list to refer to the buffer, but this allows the driver to create 1039718dceddSDavid Howells * a relocation list for state buffers and not re-write it per 1040718dceddSDavid Howells * exec using the buffer. 1041718dceddSDavid Howells */ 1042718dceddSDavid Howells __u32 target_handle; 1043718dceddSDavid Howells 1044718dceddSDavid Howells /** 1045718dceddSDavid Howells * Value to be added to the offset of the target buffer to make up 1046718dceddSDavid Howells * the relocation entry. 1047718dceddSDavid Howells */ 1048718dceddSDavid Howells __u32 delta; 1049718dceddSDavid Howells 1050718dceddSDavid Howells /** Offset in the buffer the relocation entry will be written into */ 1051718dceddSDavid Howells __u64 offset; 1052718dceddSDavid Howells 1053718dceddSDavid Howells /** 1054718dceddSDavid Howells * Offset value of the target buffer that the relocation entry was last 1055718dceddSDavid Howells * written as. 1056718dceddSDavid Howells * 1057718dceddSDavid Howells * If the buffer has the same offset as last time, we can skip syncing 1058718dceddSDavid Howells * and writing the relocation. This value is written back out by 1059718dceddSDavid Howells * the execbuffer ioctl when the relocation is written. 1060718dceddSDavid Howells */ 1061718dceddSDavid Howells __u64 presumed_offset; 1062718dceddSDavid Howells 1063718dceddSDavid Howells /** 1064718dceddSDavid Howells * Target memory domains read by this operation. 1065718dceddSDavid Howells */ 1066718dceddSDavid Howells __u32 read_domains; 1067718dceddSDavid Howells 1068718dceddSDavid Howells /** 1069718dceddSDavid Howells * Target memory domains written by this operation. 1070718dceddSDavid Howells * 1071718dceddSDavid Howells * Note that only one domain may be written by the whole 1072718dceddSDavid Howells * execbuffer operation, so that where there are conflicts, 1073718dceddSDavid Howells * the application will get -EINVAL back. 1074718dceddSDavid Howells */ 1075718dceddSDavid Howells __u32 write_domain; 1076718dceddSDavid Howells }; 1077718dceddSDavid Howells 1078718dceddSDavid Howells /** @{ 1079718dceddSDavid Howells * Intel memory domains 1080718dceddSDavid Howells * 1081718dceddSDavid Howells * Most of these just align with the various caches in 1082718dceddSDavid Howells * the system and are used to flush and invalidate as 1083718dceddSDavid Howells * objects end up cached in different domains. 1084718dceddSDavid Howells */ 1085718dceddSDavid Howells /** CPU cache */ 1086718dceddSDavid Howells #define I915_GEM_DOMAIN_CPU 0x00000001 1087718dceddSDavid Howells /** Render cache, used by 2D and 3D drawing */ 1088718dceddSDavid Howells #define I915_GEM_DOMAIN_RENDER 0x00000002 1089718dceddSDavid Howells /** Sampler cache, used by texture engine */ 1090718dceddSDavid Howells #define I915_GEM_DOMAIN_SAMPLER 0x00000004 1091718dceddSDavid Howells /** Command queue, used to load batch buffers */ 1092718dceddSDavid Howells #define I915_GEM_DOMAIN_COMMAND 0x00000008 1093718dceddSDavid Howells /** Instruction cache, used by shader programs */ 1094718dceddSDavid Howells #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 1095718dceddSDavid Howells /** Vertex address cache */ 1096718dceddSDavid Howells #define I915_GEM_DOMAIN_VERTEX 0x00000020 1097718dceddSDavid Howells /** GTT domain - aperture and scanout */ 1098718dceddSDavid Howells #define I915_GEM_DOMAIN_GTT 0x00000040 1099e22d8e3cSChris Wilson /** WC domain - uncached access */ 1100e22d8e3cSChris Wilson #define I915_GEM_DOMAIN_WC 0x00000080 1101718dceddSDavid Howells /** @} */ 1102718dceddSDavid Howells 1103718dceddSDavid Howells struct drm_i915_gem_exec_object { 1104718dceddSDavid Howells /** 1105718dceddSDavid Howells * User's handle for a buffer to be bound into the GTT for this 1106718dceddSDavid Howells * operation. 1107718dceddSDavid Howells */ 1108718dceddSDavid Howells __u32 handle; 1109718dceddSDavid Howells 1110718dceddSDavid Howells /** Number of relocations to be performed on this buffer */ 1111718dceddSDavid Howells __u32 relocation_count; 1112718dceddSDavid Howells /** 1113718dceddSDavid Howells * Pointer to array of struct drm_i915_gem_relocation_entry containing 1114718dceddSDavid Howells * the relocations to be performed in this buffer. 1115718dceddSDavid Howells */ 1116718dceddSDavid Howells __u64 relocs_ptr; 1117718dceddSDavid Howells 1118718dceddSDavid Howells /** Required alignment in graphics aperture */ 1119718dceddSDavid Howells __u64 alignment; 1120718dceddSDavid Howells 1121718dceddSDavid Howells /** 1122718dceddSDavid Howells * Returned value of the updated offset of the object, for future 1123718dceddSDavid Howells * presumed_offset writes. 1124718dceddSDavid Howells */ 1125718dceddSDavid Howells __u64 offset; 1126718dceddSDavid Howells }; 1127718dceddSDavid Howells 1128b5b6f6a6SJason Ekstrand /* DRM_IOCTL_I915_GEM_EXECBUFFER was removed in Linux 5.13 */ 1129718dceddSDavid Howells struct drm_i915_gem_execbuffer { 1130718dceddSDavid Howells /** 1131718dceddSDavid Howells * List of buffers to be validated with their relocations to be 1132718dceddSDavid Howells * performend on them. 1133718dceddSDavid Howells * 1134718dceddSDavid Howells * This is a pointer to an array of struct drm_i915_gem_validate_entry. 1135718dceddSDavid Howells * 1136718dceddSDavid Howells * These buffers must be listed in an order such that all relocations 1137718dceddSDavid Howells * a buffer is performing refer to buffers that have already appeared 1138718dceddSDavid Howells * in the validate list. 1139718dceddSDavid Howells */ 1140718dceddSDavid Howells __u64 buffers_ptr; 1141718dceddSDavid Howells __u32 buffer_count; 1142718dceddSDavid Howells 1143718dceddSDavid Howells /** Offset in the batchbuffer to start execution from. */ 1144718dceddSDavid Howells __u32 batch_start_offset; 1145718dceddSDavid Howells /** Bytes used in batchbuffer from batch_start_offset */ 1146718dceddSDavid Howells __u32 batch_len; 1147718dceddSDavid Howells __u32 DR1; 1148718dceddSDavid Howells __u32 DR4; 1149718dceddSDavid Howells __u32 num_cliprects; 1150718dceddSDavid Howells /** This is a struct drm_clip_rect *cliprects */ 1151718dceddSDavid Howells __u64 cliprects_ptr; 1152718dceddSDavid Howells }; 1153718dceddSDavid Howells 1154718dceddSDavid Howells struct drm_i915_gem_exec_object2 { 1155718dceddSDavid Howells /** 1156718dceddSDavid Howells * User's handle for a buffer to be bound into the GTT for this 1157718dceddSDavid Howells * operation. 1158718dceddSDavid Howells */ 1159718dceddSDavid Howells __u32 handle; 1160718dceddSDavid Howells 1161718dceddSDavid Howells /** Number of relocations to be performed on this buffer */ 1162718dceddSDavid Howells __u32 relocation_count; 1163718dceddSDavid Howells /** 1164718dceddSDavid Howells * Pointer to array of struct drm_i915_gem_relocation_entry containing 1165718dceddSDavid Howells * the relocations to be performed in this buffer. 1166718dceddSDavid Howells */ 1167718dceddSDavid Howells __u64 relocs_ptr; 1168718dceddSDavid Howells 1169718dceddSDavid Howells /** Required alignment in graphics aperture */ 1170718dceddSDavid Howells __u64 alignment; 1171718dceddSDavid Howells 1172718dceddSDavid Howells /** 1173506a8e87SChris Wilson * When the EXEC_OBJECT_PINNED flag is specified this is populated by 1174506a8e87SChris Wilson * the user with the GTT offset at which this object will be pinned. 1175caa574ffSMatthew Auld * 1176506a8e87SChris Wilson * When the I915_EXEC_NO_RELOC flag is specified this must contain the 1177506a8e87SChris Wilson * presumed_offset of the object. 1178caa574ffSMatthew Auld * 1179506a8e87SChris Wilson * During execbuffer2 the kernel populates it with the value of the 1180506a8e87SChris Wilson * current GTT offset of the object, for future presumed_offset writes. 1181caa574ffSMatthew Auld * 1182caa574ffSMatthew Auld * See struct drm_i915_gem_create_ext for the rules when dealing with 1183caa574ffSMatthew Auld * alignment restrictions with I915_MEMORY_CLASS_DEVICE, on devices with 1184caa574ffSMatthew Auld * minimum page sizes, like DG2. 1185718dceddSDavid Howells */ 1186718dceddSDavid Howells __u64 offset; 1187718dceddSDavid Howells 1188718dceddSDavid Howells #define EXEC_OBJECT_NEEDS_FENCE (1<<0) 1189ed5982e6SDaniel Vetter #define EXEC_OBJECT_NEEDS_GTT (1<<1) 1190ed5982e6SDaniel Vetter #define EXEC_OBJECT_WRITE (1<<2) 1191101b506aSMichel Thierry #define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3) 1192506a8e87SChris Wilson #define EXEC_OBJECT_PINNED (1<<4) 119391b2db6fSChris Wilson #define EXEC_OBJECT_PAD_TO_SIZE (1<<5) 119477ae9957SChris Wilson /* The kernel implicitly tracks GPU activity on all GEM objects, and 119577ae9957SChris Wilson * synchronises operations with outstanding rendering. This includes 119677ae9957SChris Wilson * rendering on other devices if exported via dma-buf. However, sometimes 119777ae9957SChris Wilson * this tracking is too coarse and the user knows better. For example, 119877ae9957SChris Wilson * if the object is split into non-overlapping ranges shared between different 119977ae9957SChris Wilson * clients or engines (i.e. suballocating objects), the implicit tracking 120077ae9957SChris Wilson * by kernel assumes that each operation affects the whole object rather 120177ae9957SChris Wilson * than an individual range, causing needless synchronisation between clients. 120277ae9957SChris Wilson * The kernel will also forgo any CPU cache flushes prior to rendering from 120377ae9957SChris Wilson * the object as the client is expected to be also handling such domain 120477ae9957SChris Wilson * tracking. 120577ae9957SChris Wilson * 120677ae9957SChris Wilson * The kernel maintains the implicit tracking in order to manage resources 120777ae9957SChris Wilson * used by the GPU - this flag only disables the synchronisation prior to 120877ae9957SChris Wilson * rendering with this object in this execbuf. 120977ae9957SChris Wilson * 121077ae9957SChris Wilson * Opting out of implicit synhronisation requires the user to do its own 121177ae9957SChris Wilson * explicit tracking to avoid rendering corruption. See, for example, 121277ae9957SChris Wilson * I915_PARAM_HAS_EXEC_FENCE to order execbufs and execute them asynchronously. 121377ae9957SChris Wilson */ 121477ae9957SChris Wilson #define EXEC_OBJECT_ASYNC (1<<6) 1215b0fd47adSChris Wilson /* Request that the contents of this execobject be copied into the error 1216b0fd47adSChris Wilson * state upon a GPU hang involving this batch for post-mortem debugging. 1217b0fd47adSChris Wilson * These buffers are recorded in no particular order as "user" in 1218b0fd47adSChris Wilson * /sys/class/drm/cardN/error. Query I915_PARAM_HAS_EXEC_CAPTURE to see 1219b0fd47adSChris Wilson * if the kernel supports this flag. 1220b0fd47adSChris Wilson */ 1221b0fd47adSChris Wilson #define EXEC_OBJECT_CAPTURE (1<<7) 12229e2793f6SDave Gordon /* All remaining bits are MBZ and RESERVED FOR FUTURE USE */ 1223b0fd47adSChris Wilson #define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_CAPTURE<<1) 1224718dceddSDavid Howells __u64 flags; 1225ed5982e6SDaniel Vetter 122691b2db6fSChris Wilson union { 1227718dceddSDavid Howells __u64 rsvd1; 122891b2db6fSChris Wilson __u64 pad_to_size; 122991b2db6fSChris Wilson }; 1230718dceddSDavid Howells __u64 rsvd2; 1231718dceddSDavid Howells }; 1232718dceddSDavid Howells 1233cf6e7bacSJason Ekstrand struct drm_i915_gem_exec_fence { 1234cf6e7bacSJason Ekstrand /** 1235cf6e7bacSJason Ekstrand * User's handle for a drm_syncobj to wait on or signal. 1236cf6e7bacSJason Ekstrand */ 1237cf6e7bacSJason Ekstrand __u32 handle; 1238cf6e7bacSJason Ekstrand 1239cf6e7bacSJason Ekstrand #define I915_EXEC_FENCE_WAIT (1<<0) 1240cf6e7bacSJason Ekstrand #define I915_EXEC_FENCE_SIGNAL (1<<1) 1241ebcaa1ffSTvrtko Ursulin #define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1)) 1242cf6e7bacSJason Ekstrand __u32 flags; 1243cf6e7bacSJason Ekstrand }; 1244cf6e7bacSJason Ekstrand 12452ef6a01fSMatthew Auld /* 124613149e8bSLionel Landwerlin * See drm_i915_gem_execbuffer_ext_timeline_fences. 124713149e8bSLionel Landwerlin */ 124813149e8bSLionel Landwerlin #define DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES 0 124913149e8bSLionel Landwerlin 12502ef6a01fSMatthew Auld /* 125113149e8bSLionel Landwerlin * This structure describes an array of drm_syncobj and associated points for 125213149e8bSLionel Landwerlin * timeline variants of drm_syncobj. It is invalid to append this structure to 125313149e8bSLionel Landwerlin * the execbuf if I915_EXEC_FENCE_ARRAY is set. 125413149e8bSLionel Landwerlin */ 125513149e8bSLionel Landwerlin struct drm_i915_gem_execbuffer_ext_timeline_fences { 125613149e8bSLionel Landwerlin struct i915_user_extension base; 125713149e8bSLionel Landwerlin 125813149e8bSLionel Landwerlin /** 125913149e8bSLionel Landwerlin * Number of element in the handles_ptr & value_ptr arrays. 126013149e8bSLionel Landwerlin */ 126113149e8bSLionel Landwerlin __u64 fence_count; 126213149e8bSLionel Landwerlin 126313149e8bSLionel Landwerlin /** 126413149e8bSLionel Landwerlin * Pointer to an array of struct drm_i915_gem_exec_fence of length 126513149e8bSLionel Landwerlin * fence_count. 126613149e8bSLionel Landwerlin */ 126713149e8bSLionel Landwerlin __u64 handles_ptr; 126813149e8bSLionel Landwerlin 126913149e8bSLionel Landwerlin /** 127013149e8bSLionel Landwerlin * Pointer to an array of u64 values of length fence_count. Values 127113149e8bSLionel Landwerlin * must be 0 for a binary drm_syncobj. A Value of 0 for a timeline 127213149e8bSLionel Landwerlin * drm_syncobj is invalid as it turns a drm_syncobj into a binary one. 127313149e8bSLionel Landwerlin */ 127413149e8bSLionel Landwerlin __u64 values_ptr; 1275cda9edd0SLionel Landwerlin }; 1276cda9edd0SLionel Landwerlin 1277718dceddSDavid Howells struct drm_i915_gem_execbuffer2 { 1278718dceddSDavid Howells /** 1279718dceddSDavid Howells * List of gem_exec_object2 structs 1280718dceddSDavid Howells */ 1281718dceddSDavid Howells __u64 buffers_ptr; 1282718dceddSDavid Howells __u32 buffer_count; 1283718dceddSDavid Howells 1284718dceddSDavid Howells /** Offset in the batchbuffer to start execution from. */ 1285718dceddSDavid Howells __u32 batch_start_offset; 1286718dceddSDavid Howells /** Bytes used in batchbuffer from batch_start_offset */ 1287718dceddSDavid Howells __u32 batch_len; 1288718dceddSDavid Howells __u32 DR1; 1289718dceddSDavid Howells __u32 DR4; 1290718dceddSDavid Howells __u32 num_cliprects; 1291cf6e7bacSJason Ekstrand /** 1292cf6e7bacSJason Ekstrand * This is a struct drm_clip_rect *cliprects if I915_EXEC_FENCE_ARRAY 1293cda9edd0SLionel Landwerlin * & I915_EXEC_USE_EXTENSIONS are not set. 1294cda9edd0SLionel Landwerlin * 1295cda9edd0SLionel Landwerlin * If I915_EXEC_FENCE_ARRAY is set, then this is a pointer to an array 1296cda9edd0SLionel Landwerlin * of struct drm_i915_gem_exec_fence and num_cliprects is the length 1297cda9edd0SLionel Landwerlin * of the array. 1298cda9edd0SLionel Landwerlin * 1299cda9edd0SLionel Landwerlin * If I915_EXEC_USE_EXTENSIONS is set, then this is a pointer to a 1300cda9edd0SLionel Landwerlin * single struct i915_user_extension and num_cliprects is 0. 1301cf6e7bacSJason Ekstrand */ 1302718dceddSDavid Howells __u64 cliprects_ptr; 1303d90c06d5SChris Wilson #define I915_EXEC_RING_MASK (0x3f) 1304718dceddSDavid Howells #define I915_EXEC_DEFAULT (0<<0) 1305718dceddSDavid Howells #define I915_EXEC_RENDER (1<<0) 1306718dceddSDavid Howells #define I915_EXEC_BSD (2<<0) 1307718dceddSDavid Howells #define I915_EXEC_BLT (3<<0) 130882f91b6eSXiang, Haihao #define I915_EXEC_VEBOX (4<<0) 1309718dceddSDavid Howells 1310718dceddSDavid Howells /* Used for switching the constants addressing mode on gen4+ RENDER ring. 1311718dceddSDavid Howells * Gen6+ only supports relative addressing to dynamic state (default) and 1312718dceddSDavid Howells * absolute addressing. 1313718dceddSDavid Howells * 1314718dceddSDavid Howells * These flags are ignored for the BSD and BLT rings. 1315718dceddSDavid Howells */ 1316718dceddSDavid Howells #define I915_EXEC_CONSTANTS_MASK (3<<6) 1317718dceddSDavid Howells #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ 1318718dceddSDavid Howells #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) 1319718dceddSDavid Howells #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ 1320718dceddSDavid Howells __u64 flags; 1321718dceddSDavid Howells __u64 rsvd1; /* now used for context info */ 1322718dceddSDavid Howells __u64 rsvd2; 1323718dceddSDavid Howells }; 1324718dceddSDavid Howells 1325718dceddSDavid Howells /** Resets the SO write offset registers for transform feedback on gen7. */ 1326718dceddSDavid Howells #define I915_EXEC_GEN7_SOL_RESET (1<<8) 1327718dceddSDavid Howells 1328c2fb7916SDaniel Vetter /** Request a privileged ("secure") batch buffer. Note only available for 1329c2fb7916SDaniel Vetter * DRM_ROOT_ONLY | DRM_MASTER processes. 1330c2fb7916SDaniel Vetter */ 1331c2fb7916SDaniel Vetter #define I915_EXEC_SECURE (1<<9) 1332c2fb7916SDaniel Vetter 1333b45305fcSDaniel Vetter /** Inform the kernel that the batch is and will always be pinned. This 1334b45305fcSDaniel Vetter * negates the requirement for a workaround to be performed to avoid 1335b45305fcSDaniel Vetter * an incoherent CS (such as can be found on 830/845). If this flag is 1336b45305fcSDaniel Vetter * not passed, the kernel will endeavour to make sure the batch is 1337b45305fcSDaniel Vetter * coherent with the CS before execution. If this flag is passed, 1338b45305fcSDaniel Vetter * userspace assumes the responsibility for ensuring the same. 1339b45305fcSDaniel Vetter */ 1340b45305fcSDaniel Vetter #define I915_EXEC_IS_PINNED (1<<10) 1341b45305fcSDaniel Vetter 1342c3d19d3cSGeert Uytterhoeven /** Provide a hint to the kernel that the command stream and auxiliary 1343ed5982e6SDaniel Vetter * state buffers already holds the correct presumed addresses and so the 1344ed5982e6SDaniel Vetter * relocation process may be skipped if no buffers need to be moved in 1345ed5982e6SDaniel Vetter * preparation for the execbuffer. 1346ed5982e6SDaniel Vetter */ 1347ed5982e6SDaniel Vetter #define I915_EXEC_NO_RELOC (1<<11) 1348ed5982e6SDaniel Vetter 1349eef90ccbSChris Wilson /** Use the reloc.handle as an index into the exec object array rather 1350eef90ccbSChris Wilson * than as the per-file handle. 1351eef90ccbSChris Wilson */ 1352eef90ccbSChris Wilson #define I915_EXEC_HANDLE_LUT (1<<12) 1353eef90ccbSChris Wilson 13548d360dffSZhipeng Gong /** Used for switching BSD rings on the platforms with two BSD rings */ 1355d9da6aa0STvrtko Ursulin #define I915_EXEC_BSD_SHIFT (13) 1356d9da6aa0STvrtko Ursulin #define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT) 1357d9da6aa0STvrtko Ursulin /* default ping-pong mode */ 1358d9da6aa0STvrtko Ursulin #define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT) 1359d9da6aa0STvrtko Ursulin #define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT) 1360d9da6aa0STvrtko Ursulin #define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT) 13618d360dffSZhipeng Gong 1362a9ed33caSAbdiel Janulgue /** Tell the kernel that the batchbuffer is processed by 1363a9ed33caSAbdiel Janulgue * the resource streamer. 1364a9ed33caSAbdiel Janulgue */ 1365a9ed33caSAbdiel Janulgue #define I915_EXEC_RESOURCE_STREAMER (1<<15) 1366a9ed33caSAbdiel Janulgue 1367fec0445cSChris Wilson /* Setting I915_EXEC_FENCE_IN implies that lower_32_bits(rsvd2) represent 1368fec0445cSChris Wilson * a sync_file fd to wait upon (in a nonblocking manner) prior to executing 1369fec0445cSChris Wilson * the batch. 1370fec0445cSChris Wilson * 1371fec0445cSChris Wilson * Returns -EINVAL if the sync_file fd cannot be found. 1372fec0445cSChris Wilson */ 1373fec0445cSChris Wilson #define I915_EXEC_FENCE_IN (1<<16) 1374fec0445cSChris Wilson 1375fec0445cSChris Wilson /* Setting I915_EXEC_FENCE_OUT causes the ioctl to return a sync_file fd 1376fec0445cSChris Wilson * in the upper_32_bits(rsvd2) upon success. Ownership of the fd is given 1377fec0445cSChris Wilson * to the caller, and it should be close() after use. (The fd is a regular 1378fec0445cSChris Wilson * file descriptor and will be cleaned up on process termination. It holds 1379fec0445cSChris Wilson * a reference to the request, but nothing else.) 1380fec0445cSChris Wilson * 1381fec0445cSChris Wilson * The sync_file fd can be combined with other sync_file and passed either 1382fec0445cSChris Wilson * to execbuf using I915_EXEC_FENCE_IN, to atomic KMS ioctls (so that a flip 1383fec0445cSChris Wilson * will only occur after this request completes), or to other devices. 1384fec0445cSChris Wilson * 1385fec0445cSChris Wilson * Using I915_EXEC_FENCE_OUT requires use of 1386fec0445cSChris Wilson * DRM_IOCTL_I915_GEM_EXECBUFFER2_WR ioctl so that the result is written 1387fec0445cSChris Wilson * back to userspace. Failure to do so will cause the out-fence to always 1388fec0445cSChris Wilson * be reported as zero, and the real fence fd to be leaked. 1389fec0445cSChris Wilson */ 1390fec0445cSChris Wilson #define I915_EXEC_FENCE_OUT (1<<17) 1391fec0445cSChris Wilson 13921a71cf2fSChris Wilson /* 13931a71cf2fSChris Wilson * Traditionally the execbuf ioctl has only considered the final element in 13941a71cf2fSChris Wilson * the execobject[] to be the executable batch. Often though, the client 13951a71cf2fSChris Wilson * will known the batch object prior to construction and being able to place 13961a71cf2fSChris Wilson * it into the execobject[] array first can simplify the relocation tracking. 13971a71cf2fSChris Wilson * Setting I915_EXEC_BATCH_FIRST tells execbuf to use element 0 of the 13981a71cf2fSChris Wilson * execobject[] as the * batch instead (the default is to use the last 13991a71cf2fSChris Wilson * element). 14001a71cf2fSChris Wilson */ 14011a71cf2fSChris Wilson #define I915_EXEC_BATCH_FIRST (1<<18) 1402cf6e7bacSJason Ekstrand 1403cf6e7bacSJason Ekstrand /* Setting I915_FENCE_ARRAY implies that num_cliprects and cliprects_ptr 1404cf6e7bacSJason Ekstrand * define an array of i915_gem_exec_fence structures which specify a set of 1405cf6e7bacSJason Ekstrand * dma fences to wait upon or signal. 1406cf6e7bacSJason Ekstrand */ 1407cf6e7bacSJason Ekstrand #define I915_EXEC_FENCE_ARRAY (1<<19) 1408cf6e7bacSJason Ekstrand 1409a88b6e4cSChris Wilson /* 1410a88b6e4cSChris Wilson * Setting I915_EXEC_FENCE_SUBMIT implies that lower_32_bits(rsvd2) represent 1411a88b6e4cSChris Wilson * a sync_file fd to wait upon (in a nonblocking manner) prior to executing 1412a88b6e4cSChris Wilson * the batch. 1413a88b6e4cSChris Wilson * 1414a88b6e4cSChris Wilson * Returns -EINVAL if the sync_file fd cannot be found. 1415a88b6e4cSChris Wilson */ 1416a88b6e4cSChris Wilson #define I915_EXEC_FENCE_SUBMIT (1 << 20) 1417a88b6e4cSChris Wilson 1418cda9edd0SLionel Landwerlin /* 1419cda9edd0SLionel Landwerlin * Setting I915_EXEC_USE_EXTENSIONS implies that 1420cda9edd0SLionel Landwerlin * drm_i915_gem_execbuffer2.cliprects_ptr is treated as a pointer to an linked 1421cda9edd0SLionel Landwerlin * list of i915_user_extension. Each i915_user_extension node is the base of a 1422cda9edd0SLionel Landwerlin * larger structure. The list of supported structures are listed in the 1423cda9edd0SLionel Landwerlin * drm_i915_gem_execbuffer_ext enum. 1424cda9edd0SLionel Landwerlin */ 1425cda9edd0SLionel Landwerlin #define I915_EXEC_USE_EXTENSIONS (1 << 21) 1426cda9edd0SLionel Landwerlin 1427cda9edd0SLionel Landwerlin #define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_USE_EXTENSIONS << 1)) 1428ed5982e6SDaniel Vetter 1429718dceddSDavid Howells #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) 1430718dceddSDavid Howells #define i915_execbuffer2_set_context_id(eb2, context) \ 1431718dceddSDavid Howells (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK 1432718dceddSDavid Howells #define i915_execbuffer2_get_context_id(eb2) \ 1433718dceddSDavid Howells ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) 1434718dceddSDavid Howells 1435718dceddSDavid Howells struct drm_i915_gem_pin { 1436718dceddSDavid Howells /** Handle of the buffer to be pinned. */ 1437718dceddSDavid Howells __u32 handle; 1438718dceddSDavid Howells __u32 pad; 1439718dceddSDavid Howells 1440718dceddSDavid Howells /** alignment required within the aperture */ 1441718dceddSDavid Howells __u64 alignment; 1442718dceddSDavid Howells 1443718dceddSDavid Howells /** Returned GTT offset of the buffer. */ 1444718dceddSDavid Howells __u64 offset; 1445718dceddSDavid Howells }; 1446718dceddSDavid Howells 1447718dceddSDavid Howells struct drm_i915_gem_unpin { 1448718dceddSDavid Howells /** Handle of the buffer to be unpinned. */ 1449718dceddSDavid Howells __u32 handle; 1450718dceddSDavid Howells __u32 pad; 1451718dceddSDavid Howells }; 1452718dceddSDavid Howells 1453718dceddSDavid Howells struct drm_i915_gem_busy { 1454718dceddSDavid Howells /** Handle of the buffer to check for busy */ 1455718dceddSDavid Howells __u32 handle; 1456718dceddSDavid Howells 1457426960beSChris Wilson /** Return busy status 1458426960beSChris Wilson * 1459426960beSChris Wilson * A return of 0 implies that the object is idle (after 1460426960beSChris Wilson * having flushed any pending activity), and a non-zero return that 1461426960beSChris Wilson * the object is still in-flight on the GPU. (The GPU has not yet 1462426960beSChris Wilson * signaled completion for all pending requests that reference the 14631255501dSChris Wilson * object.) An object is guaranteed to become idle eventually (so 14641255501dSChris Wilson * long as no new GPU commands are executed upon it). Due to the 14651255501dSChris Wilson * asynchronous nature of the hardware, an object reported 14661255501dSChris Wilson * as busy may become idle before the ioctl is completed. 14671255501dSChris Wilson * 14681255501dSChris Wilson * Furthermore, if the object is busy, which engine is busy is only 1469c8b50242SChris Wilson * provided as a guide and only indirectly by reporting its class 1470c8b50242SChris Wilson * (there may be more than one engine in each class). There are race 1471c8b50242SChris Wilson * conditions which prevent the report of which engines are busy from 1472c8b50242SChris Wilson * being always accurate. However, the converse is not true. If the 1473c8b50242SChris Wilson * object is idle, the result of the ioctl, that all engines are idle, 1474c8b50242SChris Wilson * is accurate. 1475426960beSChris Wilson * 1476426960beSChris Wilson * The returned dword is split into two fields to indicate both 1477c8b50242SChris Wilson * the engine classess on which the object is being read, and the 1478c8b50242SChris Wilson * engine class on which it is currently being written (if any). 1479426960beSChris Wilson * 1480426960beSChris Wilson * The low word (bits 0:15) indicate if the object is being written 1481426960beSChris Wilson * to by any engine (there can only be one, as the GEM implicit 1482426960beSChris Wilson * synchronisation rules force writes to be serialised). Only the 1483c8b50242SChris Wilson * engine class (offset by 1, I915_ENGINE_CLASS_RENDER is reported as 1484c8b50242SChris Wilson * 1 not 0 etc) for the last write is reported. 1485426960beSChris Wilson * 1486c8b50242SChris Wilson * The high word (bits 16:31) are a bitmask of which engines classes 1487c8b50242SChris Wilson * are currently reading from the object. Multiple engines may be 1488426960beSChris Wilson * reading from the object simultaneously. 1489426960beSChris Wilson * 1490c8b50242SChris Wilson * The value of each engine class is the same as specified in the 1491c649432eSTvrtko Ursulin * I915_CONTEXT_PARAM_ENGINES context parameter and via perf, i.e. 1492c8b50242SChris Wilson * I915_ENGINE_CLASS_RENDER, I915_ENGINE_CLASS_COPY, etc. 1493c649432eSTvrtko Ursulin * Some hardware may have parallel execution engines, e.g. multiple 1494c649432eSTvrtko Ursulin * media engines, which are mapped to the same class identifier and so 1495c649432eSTvrtko Ursulin * are not separately reported for busyness. 14961255501dSChris Wilson * 14971255501dSChris Wilson * Caveat emptor: 14981255501dSChris Wilson * Only the boolean result of this query is reliable; that is whether 14991255501dSChris Wilson * the object is idle or busy. The report of which engines are busy 15001255501dSChris Wilson * should be only used as a heuristic. 1501718dceddSDavid Howells */ 1502718dceddSDavid Howells __u32 busy; 1503718dceddSDavid Howells }; 1504718dceddSDavid Howells 150535c7ab42SDaniel Vetter /** 1506289f5a72SMatthew Auld * struct drm_i915_gem_caching - Set or get the caching for given object 1507289f5a72SMatthew Auld * handle. 150835c7ab42SDaniel Vetter * 1509289f5a72SMatthew Auld * Allow userspace to control the GTT caching bits for a given object when the 1510289f5a72SMatthew Auld * object is later mapped through the ppGTT(or GGTT on older platforms lacking 1511289f5a72SMatthew Auld * ppGTT support, or if the object is used for scanout). Note that this might 1512289f5a72SMatthew Auld * require unbinding the object from the GTT first, if its current caching value 1513289f5a72SMatthew Auld * doesn't match. 1514e7737b67SMatthew Auld * 1515e7737b67SMatthew Auld * Note that this all changes on discrete platforms, starting from DG1, the 1516e7737b67SMatthew Auld * set/get caching is no longer supported, and is now rejected. Instead the CPU 1517e7737b67SMatthew Auld * caching attributes(WB vs WC) will become an immutable creation time property 1518e7737b67SMatthew Auld * for the object, along with the GTT caching level. For now we don't expose any 1519e7737b67SMatthew Auld * new uAPI for this, instead on DG1 this is all implicit, although this largely 1520e7737b67SMatthew Auld * shouldn't matter since DG1 is coherent by default(without any way of 1521e7737b67SMatthew Auld * controlling it). 1522e7737b67SMatthew Auld * 1523e7737b67SMatthew Auld * Implicit caching rules, starting from DG1: 1524e7737b67SMatthew Auld * 1525e7737b67SMatthew Auld * - If any of the object placements (see &drm_i915_gem_create_ext_memory_regions) 1526e7737b67SMatthew Auld * contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and 1527e7737b67SMatthew Auld * mapped as write-combined only. 1528e7737b67SMatthew Auld * 1529e7737b67SMatthew Auld * - Everything else is always allocated and mapped as write-back, with the 1530e7737b67SMatthew Auld * guarantee that everything is also coherent with the GPU. 1531e7737b67SMatthew Auld * 1532e7737b67SMatthew Auld * Note that this is likely to change in the future again, where we might need 1533e7737b67SMatthew Auld * more flexibility on future devices, so making this all explicit as part of a 1534e7737b67SMatthew Auld * new &drm_i915_gem_create_ext extension is probable. 1535e7737b67SMatthew Auld * 1536e7737b67SMatthew Auld * Side note: Part of the reason for this is that changing the at-allocation-time CPU 1537e7737b67SMatthew Auld * caching attributes for the pages might be required(and is expensive) if we 1538e7737b67SMatthew Auld * need to then CPU map the pages later with different caching attributes. This 1539e7737b67SMatthew Auld * inconsistent caching behaviour, while supported on x86, is not universally 1540e7737b67SMatthew Auld * supported on other architectures. So for simplicity we opt for setting 1541e7737b67SMatthew Auld * everything at creation time, whilst also making it immutable, on discrete 1542e7737b67SMatthew Auld * platforms. 154335c7ab42SDaniel Vetter */ 1544718dceddSDavid Howells struct drm_i915_gem_caching { 1545718dceddSDavid Howells /** 1546289f5a72SMatthew Auld * @handle: Handle of the buffer to set/get the caching level. 1547289f5a72SMatthew Auld */ 1548718dceddSDavid Howells __u32 handle; 1549718dceddSDavid Howells 1550718dceddSDavid Howells /** 1551289f5a72SMatthew Auld * @caching: The GTT caching level to apply or possible return value. 1552718dceddSDavid Howells * 1553289f5a72SMatthew Auld * The supported @caching values: 1554289f5a72SMatthew Auld * 1555289f5a72SMatthew Auld * I915_CACHING_NONE: 1556289f5a72SMatthew Auld * 1557289f5a72SMatthew Auld * GPU access is not coherent with CPU caches. Default for machines 1558289f5a72SMatthew Auld * without an LLC. This means manual flushing might be needed, if we 1559289f5a72SMatthew Auld * want GPU access to be coherent. 1560289f5a72SMatthew Auld * 1561289f5a72SMatthew Auld * I915_CACHING_CACHED: 1562289f5a72SMatthew Auld * 1563289f5a72SMatthew Auld * GPU access is coherent with CPU caches and furthermore the data is 1564289f5a72SMatthew Auld * cached in last-level caches shared between CPU cores and the GPU GT. 1565289f5a72SMatthew Auld * 1566289f5a72SMatthew Auld * I915_CACHING_DISPLAY: 1567289f5a72SMatthew Auld * 1568289f5a72SMatthew Auld * Special GPU caching mode which is coherent with the scanout engines. 1569289f5a72SMatthew Auld * Transparently falls back to I915_CACHING_NONE on platforms where no 1570289f5a72SMatthew Auld * special cache mode (like write-through or gfdt flushing) is 1571289f5a72SMatthew Auld * available. The kernel automatically sets this mode when using a 1572289f5a72SMatthew Auld * buffer as a scanout target. Userspace can manually set this mode to 1573289f5a72SMatthew Auld * avoid a costly stall and clflush in the hotpath of drawing the first 1574289f5a72SMatthew Auld * frame. 1575289f5a72SMatthew Auld */ 1576289f5a72SMatthew Auld #define I915_CACHING_NONE 0 1577289f5a72SMatthew Auld #define I915_CACHING_CACHED 1 1578289f5a72SMatthew Auld #define I915_CACHING_DISPLAY 2 1579718dceddSDavid Howells __u32 caching; 1580718dceddSDavid Howells }; 1581718dceddSDavid Howells 1582718dceddSDavid Howells #define I915_TILING_NONE 0 1583718dceddSDavid Howells #define I915_TILING_X 1 1584718dceddSDavid Howells #define I915_TILING_Y 2 1585ea673f17SMatt Roper /* 1586ea673f17SMatt Roper * Do not add new tiling types here. The I915_TILING_* values are for 1587ea673f17SMatt Roper * de-tiling fence registers that no longer exist on modern platforms. Although 1588ea673f17SMatt Roper * the hardware may support new types of tiling in general (e.g., Tile4), we 1589ea673f17SMatt Roper * do not need to add them to the uapi that is specific to now-defunct ioctls. 1590ea673f17SMatt Roper */ 1591deeb1519SChris Wilson #define I915_TILING_LAST I915_TILING_Y 1592718dceddSDavid Howells 1593718dceddSDavid Howells #define I915_BIT_6_SWIZZLE_NONE 0 1594718dceddSDavid Howells #define I915_BIT_6_SWIZZLE_9 1 1595718dceddSDavid Howells #define I915_BIT_6_SWIZZLE_9_10 2 1596718dceddSDavid Howells #define I915_BIT_6_SWIZZLE_9_11 3 1597718dceddSDavid Howells #define I915_BIT_6_SWIZZLE_9_10_11 4 1598718dceddSDavid Howells /* Not seen by userland */ 1599718dceddSDavid Howells #define I915_BIT_6_SWIZZLE_UNKNOWN 5 1600718dceddSDavid Howells /* Seen by userland. */ 1601718dceddSDavid Howells #define I915_BIT_6_SWIZZLE_9_17 6 1602718dceddSDavid Howells #define I915_BIT_6_SWIZZLE_9_10_17 7 1603718dceddSDavid Howells 1604718dceddSDavid Howells struct drm_i915_gem_set_tiling { 1605718dceddSDavid Howells /** Handle of the buffer to have its tiling state updated */ 1606718dceddSDavid Howells __u32 handle; 1607718dceddSDavid Howells 1608718dceddSDavid Howells /** 1609718dceddSDavid Howells * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 1610718dceddSDavid Howells * I915_TILING_Y). 1611718dceddSDavid Howells * 1612718dceddSDavid Howells * This value is to be set on request, and will be updated by the 1613718dceddSDavid Howells * kernel on successful return with the actual chosen tiling layout. 1614718dceddSDavid Howells * 1615718dceddSDavid Howells * The tiling mode may be demoted to I915_TILING_NONE when the system 1616718dceddSDavid Howells * has bit 6 swizzling that can't be managed correctly by GEM. 1617718dceddSDavid Howells * 1618718dceddSDavid Howells * Buffer contents become undefined when changing tiling_mode. 1619718dceddSDavid Howells */ 1620718dceddSDavid Howells __u32 tiling_mode; 1621718dceddSDavid Howells 1622718dceddSDavid Howells /** 1623718dceddSDavid Howells * Stride in bytes for the object when in I915_TILING_X or 1624718dceddSDavid Howells * I915_TILING_Y. 1625718dceddSDavid Howells */ 1626718dceddSDavid Howells __u32 stride; 1627718dceddSDavid Howells 1628718dceddSDavid Howells /** 1629718dceddSDavid Howells * Returned address bit 6 swizzling required for CPU access through 1630718dceddSDavid Howells * mmap mapping. 1631718dceddSDavid Howells */ 1632718dceddSDavid Howells __u32 swizzle_mode; 1633718dceddSDavid Howells }; 1634718dceddSDavid Howells 1635718dceddSDavid Howells struct drm_i915_gem_get_tiling { 1636718dceddSDavid Howells /** Handle of the buffer to get tiling state for. */ 1637718dceddSDavid Howells __u32 handle; 1638718dceddSDavid Howells 1639718dceddSDavid Howells /** 1640718dceddSDavid Howells * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 1641718dceddSDavid Howells * I915_TILING_Y). 1642718dceddSDavid Howells */ 1643718dceddSDavid Howells __u32 tiling_mode; 1644718dceddSDavid Howells 1645718dceddSDavid Howells /** 1646718dceddSDavid Howells * Returned address bit 6 swizzling required for CPU access through 1647718dceddSDavid Howells * mmap mapping. 1648718dceddSDavid Howells */ 1649718dceddSDavid Howells __u32 swizzle_mode; 165070f2f5c7SChris Wilson 165170f2f5c7SChris Wilson /** 165270f2f5c7SChris Wilson * Returned address bit 6 swizzling required for CPU access through 165370f2f5c7SChris Wilson * mmap mapping whilst bound. 165470f2f5c7SChris Wilson */ 165570f2f5c7SChris Wilson __u32 phys_swizzle_mode; 1656718dceddSDavid Howells }; 1657718dceddSDavid Howells 1658718dceddSDavid Howells struct drm_i915_gem_get_aperture { 1659718dceddSDavid Howells /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ 1660718dceddSDavid Howells __u64 aper_size; 1661718dceddSDavid Howells 1662718dceddSDavid Howells /** 1663718dceddSDavid Howells * Available space in the aperture used by i915_gem_execbuffer, in 1664718dceddSDavid Howells * bytes 1665718dceddSDavid Howells */ 1666718dceddSDavid Howells __u64 aper_available_size; 1667718dceddSDavid Howells }; 1668718dceddSDavid Howells 1669718dceddSDavid Howells struct drm_i915_get_pipe_from_crtc_id { 1670718dceddSDavid Howells /** ID of CRTC being requested **/ 1671718dceddSDavid Howells __u32 crtc_id; 1672718dceddSDavid Howells 1673718dceddSDavid Howells /** pipe of requested CRTC **/ 1674718dceddSDavid Howells __u32 pipe; 1675718dceddSDavid Howells }; 1676718dceddSDavid Howells 1677718dceddSDavid Howells #define I915_MADV_WILLNEED 0 1678718dceddSDavid Howells #define I915_MADV_DONTNEED 1 1679718dceddSDavid Howells #define __I915_MADV_PURGED 2 /* internal state */ 1680718dceddSDavid Howells 1681718dceddSDavid Howells struct drm_i915_gem_madvise { 1682718dceddSDavid Howells /** Handle of the buffer to change the backing store advice */ 1683718dceddSDavid Howells __u32 handle; 1684718dceddSDavid Howells 1685718dceddSDavid Howells /* Advice: either the buffer will be needed again in the near future, 1686718dceddSDavid Howells * or wont be and could be discarded under memory pressure. 1687718dceddSDavid Howells */ 1688718dceddSDavid Howells __u32 madv; 1689718dceddSDavid Howells 1690718dceddSDavid Howells /** Whether the backing store still exists. */ 1691718dceddSDavid Howells __u32 retained; 1692718dceddSDavid Howells }; 1693718dceddSDavid Howells 1694718dceddSDavid Howells /* flags */ 1695718dceddSDavid Howells #define I915_OVERLAY_TYPE_MASK 0xff 1696718dceddSDavid Howells #define I915_OVERLAY_YUV_PLANAR 0x01 1697718dceddSDavid Howells #define I915_OVERLAY_YUV_PACKED 0x02 1698718dceddSDavid Howells #define I915_OVERLAY_RGB 0x03 1699718dceddSDavid Howells 1700718dceddSDavid Howells #define I915_OVERLAY_DEPTH_MASK 0xff00 1701718dceddSDavid Howells #define I915_OVERLAY_RGB24 0x1000 1702718dceddSDavid Howells #define I915_OVERLAY_RGB16 0x2000 1703718dceddSDavid Howells #define I915_OVERLAY_RGB15 0x3000 1704718dceddSDavid Howells #define I915_OVERLAY_YUV422 0x0100 1705718dceddSDavid Howells #define I915_OVERLAY_YUV411 0x0200 1706718dceddSDavid Howells #define I915_OVERLAY_YUV420 0x0300 1707718dceddSDavid Howells #define I915_OVERLAY_YUV410 0x0400 1708718dceddSDavid Howells 1709718dceddSDavid Howells #define I915_OVERLAY_SWAP_MASK 0xff0000 1710718dceddSDavid Howells #define I915_OVERLAY_NO_SWAP 0x000000 1711718dceddSDavid Howells #define I915_OVERLAY_UV_SWAP 0x010000 1712718dceddSDavid Howells #define I915_OVERLAY_Y_SWAP 0x020000 1713718dceddSDavid Howells #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 1714718dceddSDavid Howells 1715718dceddSDavid Howells #define I915_OVERLAY_FLAGS_MASK 0xff000000 1716718dceddSDavid Howells #define I915_OVERLAY_ENABLE 0x01000000 1717718dceddSDavid Howells 1718718dceddSDavid Howells struct drm_intel_overlay_put_image { 1719718dceddSDavid Howells /* various flags and src format description */ 1720718dceddSDavid Howells __u32 flags; 1721718dceddSDavid Howells /* source picture description */ 1722718dceddSDavid Howells __u32 bo_handle; 1723718dceddSDavid Howells /* stride values and offsets are in bytes, buffer relative */ 1724718dceddSDavid Howells __u16 stride_Y; /* stride for packed formats */ 1725718dceddSDavid Howells __u16 stride_UV; 1726718dceddSDavid Howells __u32 offset_Y; /* offset for packet formats */ 1727718dceddSDavid Howells __u32 offset_U; 1728718dceddSDavid Howells __u32 offset_V; 1729718dceddSDavid Howells /* in pixels */ 1730718dceddSDavid Howells __u16 src_width; 1731718dceddSDavid Howells __u16 src_height; 1732718dceddSDavid Howells /* to compensate the scaling factors for partially covered surfaces */ 1733718dceddSDavid Howells __u16 src_scan_width; 1734718dceddSDavid Howells __u16 src_scan_height; 1735718dceddSDavid Howells /* output crtc description */ 1736718dceddSDavid Howells __u32 crtc_id; 1737718dceddSDavid Howells __u16 dst_x; 1738718dceddSDavid Howells __u16 dst_y; 1739718dceddSDavid Howells __u16 dst_width; 1740718dceddSDavid Howells __u16 dst_height; 1741718dceddSDavid Howells }; 1742718dceddSDavid Howells 1743718dceddSDavid Howells /* flags */ 1744718dceddSDavid Howells #define I915_OVERLAY_UPDATE_ATTRS (1<<0) 1745718dceddSDavid Howells #define I915_OVERLAY_UPDATE_GAMMA (1<<1) 1746ea9da4e4SChris Wilson #define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2) 1747718dceddSDavid Howells struct drm_intel_overlay_attrs { 1748718dceddSDavid Howells __u32 flags; 1749718dceddSDavid Howells __u32 color_key; 1750718dceddSDavid Howells __s32 brightness; 1751718dceddSDavid Howells __u32 contrast; 1752718dceddSDavid Howells __u32 saturation; 1753718dceddSDavid Howells __u32 gamma0; 1754718dceddSDavid Howells __u32 gamma1; 1755718dceddSDavid Howells __u32 gamma2; 1756718dceddSDavid Howells __u32 gamma3; 1757718dceddSDavid Howells __u32 gamma4; 1758718dceddSDavid Howells __u32 gamma5; 1759718dceddSDavid Howells }; 1760718dceddSDavid Howells 1761718dceddSDavid Howells /* 1762718dceddSDavid Howells * Intel sprite handling 1763718dceddSDavid Howells * 1764718dceddSDavid Howells * Color keying works with a min/mask/max tuple. Both source and destination 1765718dceddSDavid Howells * color keying is allowed. 1766718dceddSDavid Howells * 1767718dceddSDavid Howells * Source keying: 1768718dceddSDavid Howells * Sprite pixels within the min & max values, masked against the color channels 1769718dceddSDavid Howells * specified in the mask field, will be transparent. All other pixels will 1770718dceddSDavid Howells * be displayed on top of the primary plane. For RGB surfaces, only the min 1771718dceddSDavid Howells * and mask fields will be used; ranged compares are not allowed. 1772718dceddSDavid Howells * 1773718dceddSDavid Howells * Destination keying: 1774718dceddSDavid Howells * Primary plane pixels that match the min value, masked against the color 1775718dceddSDavid Howells * channels specified in the mask field, will be replaced by corresponding 1776718dceddSDavid Howells * pixels from the sprite plane. 1777718dceddSDavid Howells * 1778718dceddSDavid Howells * Note that source & destination keying are exclusive; only one can be 1779718dceddSDavid Howells * active on a given plane. 1780718dceddSDavid Howells */ 1781718dceddSDavid Howells 17826ec5bd34SVille Syrjälä #define I915_SET_COLORKEY_NONE (1<<0) /* Deprecated. Instead set 17836ec5bd34SVille Syrjälä * flags==0 to disable colorkeying. 17846ec5bd34SVille Syrjälä */ 1785718dceddSDavid Howells #define I915_SET_COLORKEY_DESTINATION (1<<1) 1786718dceddSDavid Howells #define I915_SET_COLORKEY_SOURCE (1<<2) 1787718dceddSDavid Howells struct drm_intel_sprite_colorkey { 1788718dceddSDavid Howells __u32 plane_id; 1789718dceddSDavid Howells __u32 min_value; 1790718dceddSDavid Howells __u32 channel_mask; 1791718dceddSDavid Howells __u32 max_value; 1792718dceddSDavid Howells __u32 flags; 1793718dceddSDavid Howells }; 1794718dceddSDavid Howells 1795718dceddSDavid Howells struct drm_i915_gem_wait { 1796718dceddSDavid Howells /** Handle of BO we shall wait on */ 1797718dceddSDavid Howells __u32 bo_handle; 1798718dceddSDavid Howells __u32 flags; 1799718dceddSDavid Howells /** Number of nanoseconds to wait, Returns time remaining. */ 1800718dceddSDavid Howells __s64 timeout_ns; 1801718dceddSDavid Howells }; 1802718dceddSDavid Howells 1803718dceddSDavid Howells struct drm_i915_gem_context_create { 1804b9171541SChris Wilson __u32 ctx_id; /* output: id of new context*/ 1805718dceddSDavid Howells __u32 pad; 1806718dceddSDavid Howells }; 1807718dceddSDavid Howells 1808b9171541SChris Wilson struct drm_i915_gem_context_create_ext { 1809b9171541SChris Wilson __u32 ctx_id; /* output: id of new context*/ 1810b9171541SChris Wilson __u32 flags; 1811b9171541SChris Wilson #define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0) 18128319f44cSChris Wilson #define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE (1u << 1) 1813b9171541SChris Wilson #define I915_CONTEXT_CREATE_FLAGS_UNKNOWN \ 18148319f44cSChris Wilson (-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1)) 1815e0695db7SChris Wilson __u64 extensions; 18165cc9ed4bSChris Wilson }; 18175cc9ed4bSChris Wilson 1818c9dc0f35SChris Wilson struct drm_i915_gem_context_param { 1819c9dc0f35SChris Wilson __u32 ctx_id; 1820c9dc0f35SChris Wilson __u32 size; 1821c9dc0f35SChris Wilson __u64 param; 1822c9dc0f35SChris Wilson #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1 18236ff6d61dSJason Ekstrand /* I915_CONTEXT_PARAM_NO_ZEROMAP has been removed. On the off chance 18246ff6d61dSJason Ekstrand * someone somewhere has attempted to use it, never re-use this context 18256ff6d61dSJason Ekstrand * param number. 18266ff6d61dSJason Ekstrand */ 1827b1b38278SDavid Weinehall #define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2 1828fa8848f2SChris Wilson #define I915_CONTEXT_PARAM_GTT_SIZE 0x3 1829bc3d6744SChris Wilson #define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4 183084102171SMika Kuoppala #define I915_CONTEXT_PARAM_BANNABLE 0x5 1831ac14fbd4SChris Wilson #define I915_CONTEXT_PARAM_PRIORITY 0x6 1832ac14fbd4SChris Wilson #define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */ 1833ac14fbd4SChris Wilson #define I915_CONTEXT_DEFAULT_PRIORITY 0 1834ac14fbd4SChris Wilson #define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */ 1835e46c2e99STvrtko Ursulin /* 1836e46c2e99STvrtko Ursulin * When using the following param, value should be a pointer to 1837e46c2e99STvrtko Ursulin * drm_i915_gem_context_param_sseu. 1838e46c2e99STvrtko Ursulin */ 1839e46c2e99STvrtko Ursulin #define I915_CONTEXT_PARAM_SSEU 0x7 1840ba4fda62SChris Wilson 1841ba4fda62SChris Wilson /* 1842ba4fda62SChris Wilson * Not all clients may want to attempt automatic recover of a context after 1843ba4fda62SChris Wilson * a hang (for example, some clients may only submit very small incremental 1844ba4fda62SChris Wilson * batches relying on known logical state of previous batches which will never 1845ba4fda62SChris Wilson * recover correctly and each attempt will hang), and so would prefer that 1846ba4fda62SChris Wilson * the context is forever banned instead. 1847ba4fda62SChris Wilson * 1848ba4fda62SChris Wilson * If set to false (0), after a reset, subsequent (and in flight) rendering 1849ba4fda62SChris Wilson * from this context is discarded, and the client will need to create a new 1850ba4fda62SChris Wilson * context to use instead. 1851ba4fda62SChris Wilson * 1852ba4fda62SChris Wilson * If set to true (1), the kernel will automatically attempt to recover the 1853ba4fda62SChris Wilson * context by skipping the hanging batch and executing the next batch starting 1854ba4fda62SChris Wilson * from the default context state (discarding the incomplete logical context 1855ba4fda62SChris Wilson * state lost due to the reset). 1856ba4fda62SChris Wilson * 1857ba4fda62SChris Wilson * On creation, all new contexts are marked as recoverable. 1858ba4fda62SChris Wilson */ 1859ba4fda62SChris Wilson #define I915_CONTEXT_PARAM_RECOVERABLE 0x8 18607f3f317aSChris Wilson 18617f3f317aSChris Wilson /* 18627f3f317aSChris Wilson * The id of the associated virtual memory address space (ppGTT) of 18637f3f317aSChris Wilson * this context. Can be retrieved and passed to another context 18647f3f317aSChris Wilson * (on the same fd) for both to use the same ppGTT and so share 18657f3f317aSChris Wilson * address layouts, and avoid reloading the page tables on context 18667f3f317aSChris Wilson * switches between themselves. 18677f3f317aSChris Wilson * 18687f3f317aSChris Wilson * See DRM_I915_GEM_VM_CREATE and DRM_I915_GEM_VM_DESTROY. 18697f3f317aSChris Wilson */ 18707f3f317aSChris Wilson #define I915_CONTEXT_PARAM_VM 0x9 1871976b55f0SChris Wilson 1872976b55f0SChris Wilson /* 1873976b55f0SChris Wilson * I915_CONTEXT_PARAM_ENGINES: 1874976b55f0SChris Wilson * 1875976b55f0SChris Wilson * Bind this context to operate on this subset of available engines. Henceforth, 1876976b55f0SChris Wilson * the I915_EXEC_RING selector for DRM_IOCTL_I915_GEM_EXECBUFFER2 operates as 1877976b55f0SChris Wilson * an index into this array of engines; I915_EXEC_DEFAULT selecting engine[0] 1878976b55f0SChris Wilson * and upwards. Slots 0...N are filled in using the specified (class, instance). 1879976b55f0SChris Wilson * Use 1880976b55f0SChris Wilson * engine_class: I915_ENGINE_CLASS_INVALID, 1881976b55f0SChris Wilson * engine_instance: I915_ENGINE_CLASS_INVALID_NONE 1882976b55f0SChris Wilson * to specify a gap in the array that can be filled in later, e.g. by a 1883976b55f0SChris Wilson * virtual engine used for load balancing. 1884976b55f0SChris Wilson * 1885976b55f0SChris Wilson * Setting the number of engines bound to the context to 0, by passing a zero 1886976b55f0SChris Wilson * sized argument, will revert back to default settings. 1887976b55f0SChris Wilson * 1888976b55f0SChris Wilson * See struct i915_context_param_engines. 1889ee113690SChris Wilson * 1890ee113690SChris Wilson * Extensions: 1891ee113690SChris Wilson * i915_context_engines_load_balance (I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE) 1892ee113690SChris Wilson * i915_context_engines_bond (I915_CONTEXT_ENGINES_EXT_BOND) 1893e5e32171SMatthew Brost * i915_context_engines_parallel_submit (I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT) 1894976b55f0SChris Wilson */ 1895976b55f0SChris Wilson #define I915_CONTEXT_PARAM_ENGINES 0xa 1896a0e04715SChris Wilson 1897a0e04715SChris Wilson /* 1898a0e04715SChris Wilson * I915_CONTEXT_PARAM_PERSISTENCE: 1899a0e04715SChris Wilson * 1900a0e04715SChris Wilson * Allow the context and active rendering to survive the process until 1901a0e04715SChris Wilson * completion. Persistence allows fire-and-forget clients to queue up a 1902a0e04715SChris Wilson * bunch of work, hand the output over to a display server and then quit. 1903a0e04715SChris Wilson * If the context is marked as not persistent, upon closing (either via 1904a0e04715SChris Wilson * an explicit DRM_I915_GEM_CONTEXT_DESTROY or implicitly from file closure 1905a0e04715SChris Wilson * or process termination), the context and any outstanding requests will be 1906a0e04715SChris Wilson * cancelled (and exported fences for cancelled requests marked as -EIO). 1907a0e04715SChris Wilson * 1908a0e04715SChris Wilson * By default, new contexts allow persistence. 1909a0e04715SChris Wilson */ 1910a0e04715SChris Wilson #define I915_CONTEXT_PARAM_PERSISTENCE 0xb 191188be76cdSChris Wilson 1912fe4751c3SJason Ekstrand /* This API has been removed. On the off chance someone somewhere has 1913fe4751c3SJason Ekstrand * attempted to use it, never re-use this context param number. 191488be76cdSChris Wilson */ 191588be76cdSChris Wilson #define I915_CONTEXT_PARAM_RINGSIZE 0xc 1916d3ac8d42SDaniele Ceraolo Spurio 1917d3ac8d42SDaniele Ceraolo Spurio /* 1918d3ac8d42SDaniele Ceraolo Spurio * I915_CONTEXT_PARAM_PROTECTED_CONTENT: 1919d3ac8d42SDaniele Ceraolo Spurio * 1920d3ac8d42SDaniele Ceraolo Spurio * Mark that the context makes use of protected content, which will result 1921d3ac8d42SDaniele Ceraolo Spurio * in the context being invalidated when the protected content session is. 1922d3ac8d42SDaniele Ceraolo Spurio * Given that the protected content session is killed on suspend, the device 1923d3ac8d42SDaniele Ceraolo Spurio * is kept awake for the lifetime of a protected context, so the user should 1924d3ac8d42SDaniele Ceraolo Spurio * make sure to dispose of them once done. 1925d3ac8d42SDaniele Ceraolo Spurio * This flag can only be set at context creation time and, when set to true, 1926d3ac8d42SDaniele Ceraolo Spurio * must be preceded by an explicit setting of I915_CONTEXT_PARAM_RECOVERABLE 1927d3ac8d42SDaniele Ceraolo Spurio * to false. This flag can't be set to true in conjunction with setting the 1928d3ac8d42SDaniele Ceraolo Spurio * I915_CONTEXT_PARAM_BANNABLE flag to false. Creation example: 1929d3ac8d42SDaniele Ceraolo Spurio * 1930d3ac8d42SDaniele Ceraolo Spurio * .. code-block:: C 1931d3ac8d42SDaniele Ceraolo Spurio * 1932d3ac8d42SDaniele Ceraolo Spurio * struct drm_i915_gem_context_create_ext_setparam p_protected = { 1933d3ac8d42SDaniele Ceraolo Spurio * .base = { 1934d3ac8d42SDaniele Ceraolo Spurio * .name = I915_CONTEXT_CREATE_EXT_SETPARAM, 1935d3ac8d42SDaniele Ceraolo Spurio * }, 1936d3ac8d42SDaniele Ceraolo Spurio * .param = { 1937d3ac8d42SDaniele Ceraolo Spurio * .param = I915_CONTEXT_PARAM_PROTECTED_CONTENT, 1938d3ac8d42SDaniele Ceraolo Spurio * .value = 1, 1939d3ac8d42SDaniele Ceraolo Spurio * } 1940d3ac8d42SDaniele Ceraolo Spurio * }; 1941d3ac8d42SDaniele Ceraolo Spurio * struct drm_i915_gem_context_create_ext_setparam p_norecover = { 1942d3ac8d42SDaniele Ceraolo Spurio * .base = { 1943d3ac8d42SDaniele Ceraolo Spurio * .name = I915_CONTEXT_CREATE_EXT_SETPARAM, 1944d3ac8d42SDaniele Ceraolo Spurio * .next_extension = to_user_pointer(&p_protected), 1945d3ac8d42SDaniele Ceraolo Spurio * }, 1946d3ac8d42SDaniele Ceraolo Spurio * .param = { 1947d3ac8d42SDaniele Ceraolo Spurio * .param = I915_CONTEXT_PARAM_RECOVERABLE, 1948d3ac8d42SDaniele Ceraolo Spurio * .value = 0, 1949d3ac8d42SDaniele Ceraolo Spurio * } 1950d3ac8d42SDaniele Ceraolo Spurio * }; 1951d3ac8d42SDaniele Ceraolo Spurio * struct drm_i915_gem_context_create_ext create = { 1952d3ac8d42SDaniele Ceraolo Spurio * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS, 1953d3ac8d42SDaniele Ceraolo Spurio * .extensions = to_user_pointer(&p_norecover); 1954d3ac8d42SDaniele Ceraolo Spurio * }; 1955d3ac8d42SDaniele Ceraolo Spurio * 1956d3ac8d42SDaniele Ceraolo Spurio * ctx_id = gem_context_create_ext(drm_fd, &create); 1957d3ac8d42SDaniele Ceraolo Spurio * 1958d3ac8d42SDaniele Ceraolo Spurio * In addition to the normal failure cases, setting this flag during context 1959d3ac8d42SDaniele Ceraolo Spurio * creation can result in the following errors: 1960d3ac8d42SDaniele Ceraolo Spurio * 1961d3ac8d42SDaniele Ceraolo Spurio * -ENODEV: feature not available 1962d3ac8d42SDaniele Ceraolo Spurio * -EPERM: trying to mark a recoverable or not bannable context as protected 1963d3ac8d42SDaniele Ceraolo Spurio */ 1964d3ac8d42SDaniele Ceraolo Spurio #define I915_CONTEXT_PARAM_PROTECTED_CONTENT 0xd 1965be03564bSChris Wilson /* Must be kept compact -- no holes and well documented */ 1966e0695db7SChris Wilson 1967c9dc0f35SChris Wilson __u64 value; 1968c9dc0f35SChris Wilson }; 1969c9dc0f35SChris Wilson 19702ef6a01fSMatthew Auld /* 1971e46c2e99STvrtko Ursulin * Context SSEU programming 1972e46c2e99STvrtko Ursulin * 1973e46c2e99STvrtko Ursulin * It may be necessary for either functional or performance reason to configure 1974e46c2e99STvrtko Ursulin * a context to run with a reduced number of SSEU (where SSEU stands for Slice/ 1975e46c2e99STvrtko Ursulin * Sub-slice/EU). 1976e46c2e99STvrtko Ursulin * 1977e46c2e99STvrtko Ursulin * This is done by configuring SSEU configuration using the below 1978e46c2e99STvrtko Ursulin * @struct drm_i915_gem_context_param_sseu for every supported engine which 1979e46c2e99STvrtko Ursulin * userspace intends to use. 1980e46c2e99STvrtko Ursulin * 1981e46c2e99STvrtko Ursulin * Not all GPUs or engines support this functionality in which case an error 1982e46c2e99STvrtko Ursulin * code -ENODEV will be returned. 1983e46c2e99STvrtko Ursulin * 1984e46c2e99STvrtko Ursulin * Also, flexibility of possible SSEU configuration permutations varies between 1985e46c2e99STvrtko Ursulin * GPU generations and software imposed limitations. Requesting such a 1986e46c2e99STvrtko Ursulin * combination will return an error code of -EINVAL. 1987e46c2e99STvrtko Ursulin * 1988e46c2e99STvrtko Ursulin * NOTE: When perf/OA is active the context's SSEU configuration is ignored in 1989e46c2e99STvrtko Ursulin * favour of a single global setting. 1990e46c2e99STvrtko Ursulin */ 1991e46c2e99STvrtko Ursulin struct drm_i915_gem_context_param_sseu { 1992e46c2e99STvrtko Ursulin /* 1993e46c2e99STvrtko Ursulin * Engine class & instance to be configured or queried. 1994e46c2e99STvrtko Ursulin */ 1995d1172ab3SChris Wilson struct i915_engine_class_instance engine; 1996e46c2e99STvrtko Ursulin 1997e46c2e99STvrtko Ursulin /* 1998e620f7b3SChris Wilson * Unknown flags must be cleared to zero. 1999e46c2e99STvrtko Ursulin */ 2000e46c2e99STvrtko Ursulin __u32 flags; 2001e620f7b3SChris Wilson #define I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX (1u << 0) 2002e46c2e99STvrtko Ursulin 2003e46c2e99STvrtko Ursulin /* 2004e46c2e99STvrtko Ursulin * Mask of slices to enable for the context. Valid values are a subset 2005e46c2e99STvrtko Ursulin * of the bitmask value returned for I915_PARAM_SLICE_MASK. 2006e46c2e99STvrtko Ursulin */ 2007e46c2e99STvrtko Ursulin __u64 slice_mask; 2008e46c2e99STvrtko Ursulin 2009e46c2e99STvrtko Ursulin /* 2010e46c2e99STvrtko Ursulin * Mask of subslices to enable for the context. Valid values are a 2011e46c2e99STvrtko Ursulin * subset of the bitmask value return by I915_PARAM_SUBSLICE_MASK. 2012e46c2e99STvrtko Ursulin */ 2013e46c2e99STvrtko Ursulin __u64 subslice_mask; 2014e46c2e99STvrtko Ursulin 2015e46c2e99STvrtko Ursulin /* 2016e46c2e99STvrtko Ursulin * Minimum/Maximum number of EUs to enable per subslice for the 2017e46c2e99STvrtko Ursulin * context. min_eus_per_subslice must be inferior or equal to 2018e46c2e99STvrtko Ursulin * max_eus_per_subslice. 2019e46c2e99STvrtko Ursulin */ 2020e46c2e99STvrtko Ursulin __u16 min_eus_per_subslice; 2021e46c2e99STvrtko Ursulin __u16 max_eus_per_subslice; 2022e46c2e99STvrtko Ursulin 2023e46c2e99STvrtko Ursulin /* 2024e46c2e99STvrtko Ursulin * Unused for now. Must be cleared to zero. 2025e46c2e99STvrtko Ursulin */ 2026e46c2e99STvrtko Ursulin __u32 rsvd; 2027e46c2e99STvrtko Ursulin }; 2028e46c2e99STvrtko Ursulin 202957772953STvrtko Ursulin /** 203057772953STvrtko Ursulin * DOC: Virtual Engine uAPI 203157772953STvrtko Ursulin * 203257772953STvrtko Ursulin * Virtual engine is a concept where userspace is able to configure a set of 203357772953STvrtko Ursulin * physical engines, submit a batch buffer, and let the driver execute it on any 203457772953STvrtko Ursulin * engine from the set as it sees fit. 203557772953STvrtko Ursulin * 203657772953STvrtko Ursulin * This is primarily useful on parts which have multiple instances of a same 203757772953STvrtko Ursulin * class engine, like for example GT3+ Skylake parts with their two VCS engines. 203857772953STvrtko Ursulin * 203957772953STvrtko Ursulin * For instance userspace can enumerate all engines of a certain class using the 204057772953STvrtko Ursulin * previously described `Engine Discovery uAPI`_. After that userspace can 204157772953STvrtko Ursulin * create a GEM context with a placeholder slot for the virtual engine (using 204257772953STvrtko Ursulin * `I915_ENGINE_CLASS_INVALID` and `I915_ENGINE_CLASS_INVALID_NONE` for class 204357772953STvrtko Ursulin * and instance respectively) and finally using the 204457772953STvrtko Ursulin * `I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE` extension place a virtual engine in 204557772953STvrtko Ursulin * the same reserved slot. 204657772953STvrtko Ursulin * 204757772953STvrtko Ursulin * Example of creating a virtual engine and submitting a batch buffer to it: 204857772953STvrtko Ursulin * 204957772953STvrtko Ursulin * .. code-block:: C 205057772953STvrtko Ursulin * 205157772953STvrtko Ursulin * I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(virtual, 2) = { 205257772953STvrtko Ursulin * .base.name = I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE, 205357772953STvrtko Ursulin * .engine_index = 0, // Place this virtual engine into engine map slot 0 205457772953STvrtko Ursulin * .num_siblings = 2, 205557772953STvrtko Ursulin * .engines = { { I915_ENGINE_CLASS_VIDEO, 0 }, 205657772953STvrtko Ursulin * { I915_ENGINE_CLASS_VIDEO, 1 }, }, 205757772953STvrtko Ursulin * }; 205857772953STvrtko Ursulin * I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = { 205957772953STvrtko Ursulin * .engines = { { I915_ENGINE_CLASS_INVALID, 206057772953STvrtko Ursulin * I915_ENGINE_CLASS_INVALID_NONE } }, 206157772953STvrtko Ursulin * .extensions = to_user_pointer(&virtual), // Chains after load_balance extension 206257772953STvrtko Ursulin * }; 206357772953STvrtko Ursulin * struct drm_i915_gem_context_create_ext_setparam p_engines = { 206457772953STvrtko Ursulin * .base = { 206557772953STvrtko Ursulin * .name = I915_CONTEXT_CREATE_EXT_SETPARAM, 206657772953STvrtko Ursulin * }, 206757772953STvrtko Ursulin * .param = { 206857772953STvrtko Ursulin * .param = I915_CONTEXT_PARAM_ENGINES, 206957772953STvrtko Ursulin * .value = to_user_pointer(&engines), 207057772953STvrtko Ursulin * .size = sizeof(engines), 207157772953STvrtko Ursulin * }, 207257772953STvrtko Ursulin * }; 207357772953STvrtko Ursulin * struct drm_i915_gem_context_create_ext create = { 207457772953STvrtko Ursulin * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS, 207557772953STvrtko Ursulin * .extensions = to_user_pointer(&p_engines); 207657772953STvrtko Ursulin * }; 207757772953STvrtko Ursulin * 207857772953STvrtko Ursulin * ctx_id = gem_context_create_ext(drm_fd, &create); 207957772953STvrtko Ursulin * 208057772953STvrtko Ursulin * // Now we have created a GEM context with its engine map containing a 208157772953STvrtko Ursulin * // single virtual engine. Submissions to this slot can go either to 208257772953STvrtko Ursulin * // vcs0 or vcs1, depending on the load balancing algorithm used inside 208357772953STvrtko Ursulin * // the driver. The load balancing is dynamic from one batch buffer to 208457772953STvrtko Ursulin * // another and transparent to userspace. 208557772953STvrtko Ursulin * 208657772953STvrtko Ursulin * ... 208757772953STvrtko Ursulin * execbuf.rsvd1 = ctx_id; 208857772953STvrtko Ursulin * execbuf.flags = 0; // Submits to index 0 which is the virtual engine 208957772953STvrtko Ursulin * gem_execbuf(drm_fd, &execbuf); 209057772953STvrtko Ursulin */ 209157772953STvrtko Ursulin 20926d06779eSChris Wilson /* 20936d06779eSChris Wilson * i915_context_engines_load_balance: 20946d06779eSChris Wilson * 20956d06779eSChris Wilson * Enable load balancing across this set of engines. 20966d06779eSChris Wilson * 20976d06779eSChris Wilson * Into the I915_EXEC_DEFAULT slot [0], a virtual engine is created that when 20986d06779eSChris Wilson * used will proxy the execbuffer request onto one of the set of engines 20996d06779eSChris Wilson * in such a way as to distribute the load evenly across the set. 21006d06779eSChris Wilson * 21016d06779eSChris Wilson * The set of engines must be compatible (e.g. the same HW class) as they 21026d06779eSChris Wilson * will share the same logical GPU context and ring. 21036d06779eSChris Wilson * 21046d06779eSChris Wilson * To intermix rendering with the virtual engine and direct rendering onto 21056d06779eSChris Wilson * the backing engines (bypassing the load balancing proxy), the context must 21066d06779eSChris Wilson * be defined to use a single timeline for all engines. 21076d06779eSChris Wilson */ 21086d06779eSChris Wilson struct i915_context_engines_load_balance { 21096d06779eSChris Wilson struct i915_user_extension base; 21106d06779eSChris Wilson 21116d06779eSChris Wilson __u16 engine_index; 21126d06779eSChris Wilson __u16 num_siblings; 21136d06779eSChris Wilson __u32 flags; /* all undefined flags must be zero */ 21146d06779eSChris Wilson 21156d06779eSChris Wilson __u64 mbz64; /* reserved for future use; must be zero */ 21166d06779eSChris Wilson 21176d06779eSChris Wilson struct i915_engine_class_instance engines[0]; 21186d06779eSChris Wilson } __attribute__((packed)); 21196d06779eSChris Wilson 21206d06779eSChris Wilson #define I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(name__, N__) struct { \ 21216d06779eSChris Wilson struct i915_user_extension base; \ 21226d06779eSChris Wilson __u16 engine_index; \ 21236d06779eSChris Wilson __u16 num_siblings; \ 21246d06779eSChris Wilson __u32 flags; \ 21256d06779eSChris Wilson __u64 mbz64; \ 21266d06779eSChris Wilson struct i915_engine_class_instance engines[N__]; \ 21276d06779eSChris Wilson } __attribute__((packed)) name__ 21286d06779eSChris Wilson 2129ee113690SChris Wilson /* 2130ee113690SChris Wilson * i915_context_engines_bond: 2131ee113690SChris Wilson * 2132ee113690SChris Wilson * Constructed bonded pairs for execution within a virtual engine. 2133ee113690SChris Wilson * 2134ee113690SChris Wilson * All engines are equal, but some are more equal than others. Given 2135ee113690SChris Wilson * the distribution of resources in the HW, it may be preferable to run 2136ee113690SChris Wilson * a request on a given subset of engines in parallel to a request on a 2137ee113690SChris Wilson * specific engine. We enable this selection of engines within a virtual 2138ee113690SChris Wilson * engine by specifying bonding pairs, for any given master engine we will 2139ee113690SChris Wilson * only execute on one of the corresponding siblings within the virtual engine. 2140ee113690SChris Wilson * 2141ee113690SChris Wilson * To execute a request in parallel on the master engine and a sibling requires 2142ee113690SChris Wilson * coordination with a I915_EXEC_FENCE_SUBMIT. 2143ee113690SChris Wilson */ 2144ee113690SChris Wilson struct i915_context_engines_bond { 2145ee113690SChris Wilson struct i915_user_extension base; 2146ee113690SChris Wilson 2147ee113690SChris Wilson struct i915_engine_class_instance master; 2148ee113690SChris Wilson 2149ee113690SChris Wilson __u16 virtual_index; /* index of virtual engine in ctx->engines[] */ 2150ee113690SChris Wilson __u16 num_bonds; 2151ee113690SChris Wilson 2152ee113690SChris Wilson __u64 flags; /* all undefined flags must be zero */ 2153ee113690SChris Wilson __u64 mbz64[4]; /* reserved for future use; must be zero */ 2154ee113690SChris Wilson 2155ee113690SChris Wilson struct i915_engine_class_instance engines[0]; 2156ee113690SChris Wilson } __attribute__((packed)); 2157ee113690SChris Wilson 2158ee113690SChris Wilson #define I915_DEFINE_CONTEXT_ENGINES_BOND(name__, N__) struct { \ 2159ee113690SChris Wilson struct i915_user_extension base; \ 2160ee113690SChris Wilson struct i915_engine_class_instance master; \ 2161ee113690SChris Wilson __u16 virtual_index; \ 2162ee113690SChris Wilson __u16 num_bonds; \ 2163ee113690SChris Wilson __u64 flags; \ 2164ee113690SChris Wilson __u64 mbz64[4]; \ 2165ee113690SChris Wilson struct i915_engine_class_instance engines[N__]; \ 2166ee113690SChris Wilson } __attribute__((packed)) name__ 2167ee113690SChris Wilson 216857772953STvrtko Ursulin /** 2169e5e32171SMatthew Brost * struct i915_context_engines_parallel_submit - Configure engine for 2170e5e32171SMatthew Brost * parallel submission. 2171e5e32171SMatthew Brost * 2172e5e32171SMatthew Brost * Setup a slot in the context engine map to allow multiple BBs to be submitted 2173e5e32171SMatthew Brost * in a single execbuf IOCTL. Those BBs will then be scheduled to run on the GPU 2174e5e32171SMatthew Brost * in parallel. Multiple hardware contexts are created internally in the i915 to 2175e5e32171SMatthew Brost * run these BBs. Once a slot is configured for N BBs only N BBs can be 2176e5e32171SMatthew Brost * submitted in each execbuf IOCTL and this is implicit behavior e.g. The user 2177e5e32171SMatthew Brost * doesn't tell the execbuf IOCTL there are N BBs, the execbuf IOCTL knows how 2178e5e32171SMatthew Brost * many BBs there are based on the slot's configuration. The N BBs are the last 2179e5e32171SMatthew Brost * N buffer objects or first N if I915_EXEC_BATCH_FIRST is set. 2180e5e32171SMatthew Brost * 2181e5e32171SMatthew Brost * The default placement behavior is to create implicit bonds between each 2182e5e32171SMatthew Brost * context if each context maps to more than 1 physical engine (e.g. context is 2183e5e32171SMatthew Brost * a virtual engine). Also we only allow contexts of same engine class and these 2184e5e32171SMatthew Brost * contexts must be in logically contiguous order. Examples of the placement 2185e5e32171SMatthew Brost * behavior are described below. Lastly, the default is to not allow BBs to be 2186e5e32171SMatthew Brost * preempted mid-batch. Rather insert coordinated preemption points on all 2187e5e32171SMatthew Brost * hardware contexts between each set of BBs. Flags could be added in the future 2188e5e32171SMatthew Brost * to change both of these default behaviors. 2189e5e32171SMatthew Brost * 2190e5e32171SMatthew Brost * Returns -EINVAL if hardware context placement configuration is invalid or if 2191e5e32171SMatthew Brost * the placement configuration isn't supported on the platform / submission 2192e5e32171SMatthew Brost * interface. 2193e5e32171SMatthew Brost * Returns -ENODEV if extension isn't supported on the platform / submission 2194e5e32171SMatthew Brost * interface. 2195e5e32171SMatthew Brost * 2196e5e32171SMatthew Brost * .. code-block:: none 2197e5e32171SMatthew Brost * 2198e5e32171SMatthew Brost * Examples syntax: 2199e5e32171SMatthew Brost * CS[X] = generic engine of same class, logical instance X 2200e5e32171SMatthew Brost * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE 2201e5e32171SMatthew Brost * 2202e5e32171SMatthew Brost * Example 1 pseudo code: 2203e5e32171SMatthew Brost * set_engines(INVALID) 2204e5e32171SMatthew Brost * set_parallel(engine_index=0, width=2, num_siblings=1, 2205e5e32171SMatthew Brost * engines=CS[0],CS[1]) 2206e5e32171SMatthew Brost * 2207e5e32171SMatthew Brost * Results in the following valid placement: 2208e5e32171SMatthew Brost * CS[0], CS[1] 2209e5e32171SMatthew Brost * 2210e5e32171SMatthew Brost * Example 2 pseudo code: 2211e5e32171SMatthew Brost * set_engines(INVALID) 2212e5e32171SMatthew Brost * set_parallel(engine_index=0, width=2, num_siblings=2, 2213e5e32171SMatthew Brost * engines=CS[0],CS[2],CS[1],CS[3]) 2214e5e32171SMatthew Brost * 2215e5e32171SMatthew Brost * Results in the following valid placements: 2216e5e32171SMatthew Brost * CS[0], CS[1] 2217e5e32171SMatthew Brost * CS[2], CS[3] 2218e5e32171SMatthew Brost * 2219e5e32171SMatthew Brost * This can be thought of as two virtual engines, each containing two 2220e5e32171SMatthew Brost * engines thereby making a 2D array. However, there are bonds tying the 2221e5e32171SMatthew Brost * entries together and placing restrictions on how they can be scheduled. 2222e5e32171SMatthew Brost * Specifically, the scheduler can choose only vertical columns from the 2D 2223e5e32171SMatthew Brost * array. That is, CS[0] is bonded to CS[1] and CS[2] to CS[3]. So if the 2224e5e32171SMatthew Brost * scheduler wants to submit to CS[0], it must also choose CS[1] and vice 2225e5e32171SMatthew Brost * versa. Same for CS[2] requires also using CS[3]. 2226e5e32171SMatthew Brost * VE[0] = CS[0], CS[2] 2227e5e32171SMatthew Brost * VE[1] = CS[1], CS[3] 2228e5e32171SMatthew Brost * 2229e5e32171SMatthew Brost * Example 3 pseudo code: 2230e5e32171SMatthew Brost * set_engines(INVALID) 2231e5e32171SMatthew Brost * set_parallel(engine_index=0, width=2, num_siblings=2, 2232e5e32171SMatthew Brost * engines=CS[0],CS[1],CS[1],CS[3]) 2233e5e32171SMatthew Brost * 2234e5e32171SMatthew Brost * Results in the following valid and invalid placements: 2235e5e32171SMatthew Brost * CS[0], CS[1] 2236e5e32171SMatthew Brost * CS[1], CS[3] - Not logically contiguous, return -EINVAL 2237e5e32171SMatthew Brost */ 2238e5e32171SMatthew Brost struct i915_context_engines_parallel_submit { 2239e5e32171SMatthew Brost /** 2240e5e32171SMatthew Brost * @base: base user extension. 2241e5e32171SMatthew Brost */ 2242e5e32171SMatthew Brost struct i915_user_extension base; 2243e5e32171SMatthew Brost 2244e5e32171SMatthew Brost /** 2245e5e32171SMatthew Brost * @engine_index: slot for parallel engine 2246e5e32171SMatthew Brost */ 2247e5e32171SMatthew Brost __u16 engine_index; 2248e5e32171SMatthew Brost 2249e5e32171SMatthew Brost /** 2250e5e32171SMatthew Brost * @width: number of contexts per parallel engine or in other words the 2251e5e32171SMatthew Brost * number of batches in each submission 2252e5e32171SMatthew Brost */ 2253e5e32171SMatthew Brost __u16 width; 2254e5e32171SMatthew Brost 2255e5e32171SMatthew Brost /** 2256e5e32171SMatthew Brost * @num_siblings: number of siblings per context or in other words the 2257e5e32171SMatthew Brost * number of possible placements for each submission 2258e5e32171SMatthew Brost */ 2259e5e32171SMatthew Brost __u16 num_siblings; 2260e5e32171SMatthew Brost 2261e5e32171SMatthew Brost /** 2262e5e32171SMatthew Brost * @mbz16: reserved for future use; must be zero 2263e5e32171SMatthew Brost */ 2264e5e32171SMatthew Brost __u16 mbz16; 2265e5e32171SMatthew Brost 2266e5e32171SMatthew Brost /** 2267e5e32171SMatthew Brost * @flags: all undefined flags must be zero, currently not defined flags 2268e5e32171SMatthew Brost */ 2269e5e32171SMatthew Brost __u64 flags; 2270e5e32171SMatthew Brost 2271e5e32171SMatthew Brost /** 2272e5e32171SMatthew Brost * @mbz64: reserved for future use; must be zero 2273e5e32171SMatthew Brost */ 2274e5e32171SMatthew Brost __u64 mbz64[3]; 2275e5e32171SMatthew Brost 2276e5e32171SMatthew Brost /** 2277e5e32171SMatthew Brost * @engines: 2-d array of engine instances to configure parallel engine 2278e5e32171SMatthew Brost * 2279e5e32171SMatthew Brost * length = width (i) * num_siblings (j) 2280e5e32171SMatthew Brost * index = j + i * num_siblings 2281e5e32171SMatthew Brost */ 2282e5e32171SMatthew Brost struct i915_engine_class_instance engines[0]; 2283e5e32171SMatthew Brost 2284e5e32171SMatthew Brost } __packed; 2285e5e32171SMatthew Brost 2286e5e32171SMatthew Brost #define I915_DEFINE_CONTEXT_ENGINES_PARALLEL_SUBMIT(name__, N__) struct { \ 2287e5e32171SMatthew Brost struct i915_user_extension base; \ 2288e5e32171SMatthew Brost __u16 engine_index; \ 2289e5e32171SMatthew Brost __u16 width; \ 2290e5e32171SMatthew Brost __u16 num_siblings; \ 2291e5e32171SMatthew Brost __u16 mbz16; \ 2292e5e32171SMatthew Brost __u64 flags; \ 2293e5e32171SMatthew Brost __u64 mbz64[3]; \ 2294e5e32171SMatthew Brost struct i915_engine_class_instance engines[N__]; \ 2295e5e32171SMatthew Brost } __attribute__((packed)) name__ 2296e5e32171SMatthew Brost 2297e5e32171SMatthew Brost /** 229857772953STvrtko Ursulin * DOC: Context Engine Map uAPI 229957772953STvrtko Ursulin * 230057772953STvrtko Ursulin * Context engine map is a new way of addressing engines when submitting batch- 230157772953STvrtko Ursulin * buffers, replacing the existing way of using identifiers like `I915_EXEC_BLT` 230257772953STvrtko Ursulin * inside the flags field of `struct drm_i915_gem_execbuffer2`. 230357772953STvrtko Ursulin * 230457772953STvrtko Ursulin * To use it created GEM contexts need to be configured with a list of engines 230557772953STvrtko Ursulin * the user is intending to submit to. This is accomplished using the 230657772953STvrtko Ursulin * `I915_CONTEXT_PARAM_ENGINES` parameter and `struct 230757772953STvrtko Ursulin * i915_context_param_engines`. 230857772953STvrtko Ursulin * 230957772953STvrtko Ursulin * For such contexts the `I915_EXEC_RING_MASK` field becomes an index into the 231057772953STvrtko Ursulin * configured map. 231157772953STvrtko Ursulin * 231257772953STvrtko Ursulin * Example of creating such context and submitting against it: 231357772953STvrtko Ursulin * 231457772953STvrtko Ursulin * .. code-block:: C 231557772953STvrtko Ursulin * 231657772953STvrtko Ursulin * I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 2) = { 231757772953STvrtko Ursulin * .engines = { { I915_ENGINE_CLASS_RENDER, 0 }, 231857772953STvrtko Ursulin * { I915_ENGINE_CLASS_COPY, 0 } } 231957772953STvrtko Ursulin * }; 232057772953STvrtko Ursulin * struct drm_i915_gem_context_create_ext_setparam p_engines = { 232157772953STvrtko Ursulin * .base = { 232257772953STvrtko Ursulin * .name = I915_CONTEXT_CREATE_EXT_SETPARAM, 232357772953STvrtko Ursulin * }, 232457772953STvrtko Ursulin * .param = { 232557772953STvrtko Ursulin * .param = I915_CONTEXT_PARAM_ENGINES, 232657772953STvrtko Ursulin * .value = to_user_pointer(&engines), 232757772953STvrtko Ursulin * .size = sizeof(engines), 232857772953STvrtko Ursulin * }, 232957772953STvrtko Ursulin * }; 233057772953STvrtko Ursulin * struct drm_i915_gem_context_create_ext create = { 233157772953STvrtko Ursulin * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS, 233257772953STvrtko Ursulin * .extensions = to_user_pointer(&p_engines); 233357772953STvrtko Ursulin * }; 233457772953STvrtko Ursulin * 233557772953STvrtko Ursulin * ctx_id = gem_context_create_ext(drm_fd, &create); 233657772953STvrtko Ursulin * 233757772953STvrtko Ursulin * // We have now created a GEM context with two engines in the map: 233857772953STvrtko Ursulin * // Index 0 points to rcs0 while index 1 points to bcs0. Other engines 233957772953STvrtko Ursulin * // will not be accessible from this context. 234057772953STvrtko Ursulin * 234157772953STvrtko Ursulin * ... 234257772953STvrtko Ursulin * execbuf.rsvd1 = ctx_id; 234357772953STvrtko Ursulin * execbuf.flags = 0; // Submits to index 0, which is rcs0 for this context 234457772953STvrtko Ursulin * gem_execbuf(drm_fd, &execbuf); 234557772953STvrtko Ursulin * 234657772953STvrtko Ursulin * ... 234757772953STvrtko Ursulin * execbuf.rsvd1 = ctx_id; 234857772953STvrtko Ursulin * execbuf.flags = 1; // Submits to index 0, which is bcs0 for this context 234957772953STvrtko Ursulin * gem_execbuf(drm_fd, &execbuf); 235057772953STvrtko Ursulin */ 235157772953STvrtko Ursulin 2352976b55f0SChris Wilson struct i915_context_param_engines { 2353976b55f0SChris Wilson __u64 extensions; /* linked chain of extension blocks, 0 terminates */ 23546d06779eSChris Wilson #define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */ 2355ee113690SChris Wilson #define I915_CONTEXT_ENGINES_EXT_BOND 1 /* see i915_context_engines_bond */ 2356e5e32171SMatthew Brost #define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */ 2357976b55f0SChris Wilson struct i915_engine_class_instance engines[0]; 2358976b55f0SChris Wilson } __attribute__((packed)); 2359976b55f0SChris Wilson 2360976b55f0SChris Wilson #define I915_DEFINE_CONTEXT_PARAM_ENGINES(name__, N__) struct { \ 2361976b55f0SChris Wilson __u64 extensions; \ 2362976b55f0SChris Wilson struct i915_engine_class_instance engines[N__]; \ 2363976b55f0SChris Wilson } __attribute__((packed)) name__ 2364976b55f0SChris Wilson 2365b9171541SChris Wilson struct drm_i915_gem_context_create_ext_setparam { 2366b9171541SChris Wilson #define I915_CONTEXT_CREATE_EXT_SETPARAM 0 2367b9171541SChris Wilson struct i915_user_extension base; 2368b9171541SChris Wilson struct drm_i915_gem_context_param param; 2369b9171541SChris Wilson }; 2370b9171541SChris Wilson 23714a766ae4SJason Ekstrand /* This API has been removed. On the off chance someone somewhere has 23724a766ae4SJason Ekstrand * attempted to use it, never re-use this extension number. 23734a766ae4SJason Ekstrand */ 2374b81dde71SChris Wilson #define I915_CONTEXT_CREATE_EXT_CLONE 1 2375b81dde71SChris Wilson 2376b9171541SChris Wilson struct drm_i915_gem_context_destroy { 2377b9171541SChris Wilson __u32 ctx_id; 2378b9171541SChris Wilson __u32 pad; 2379b9171541SChris Wilson }; 2380b9171541SChris Wilson 2381b9171541SChris Wilson /* 2382b9171541SChris Wilson * DRM_I915_GEM_VM_CREATE - 2383b9171541SChris Wilson * 2384b9171541SChris Wilson * Create a new virtual memory address space (ppGTT) for use within a context 2385b9171541SChris Wilson * on the same file. Extensions can be provided to configure exactly how the 2386b9171541SChris Wilson * address space is setup upon creation. 2387b9171541SChris Wilson * 2388b9171541SChris Wilson * The id of new VM (bound to the fd) for use with I915_CONTEXT_PARAM_VM is 2389b9171541SChris Wilson * returned in the outparam @id. 2390b9171541SChris Wilson * 2391b9171541SChris Wilson * No flags are defined, with all bits reserved and must be zero. 2392b9171541SChris Wilson * 2393b9171541SChris Wilson * An extension chain maybe provided, starting with @extensions, and terminated 2394b9171541SChris Wilson * by the @next_extension being 0. Currently, no extensions are defined. 2395b9171541SChris Wilson * 2396b9171541SChris Wilson * DRM_I915_GEM_VM_DESTROY - 2397b9171541SChris Wilson * 2398b9171541SChris Wilson * Destroys a previously created VM id, specified in @id. 2399b9171541SChris Wilson * 2400b9171541SChris Wilson * No extensions or flags are allowed currently, and so must be zero. 2401b9171541SChris Wilson */ 2402b9171541SChris Wilson struct drm_i915_gem_vm_control { 2403b9171541SChris Wilson __u64 extensions; 2404b9171541SChris Wilson __u32 flags; 2405b9171541SChris Wilson __u32 vm_id; 2406b9171541SChris Wilson }; 2407b9171541SChris Wilson 2408b9171541SChris Wilson struct drm_i915_reg_read { 2409b9171541SChris Wilson /* 2410b9171541SChris Wilson * Register offset. 2411b9171541SChris Wilson * For 64bit wide registers where the upper 32bits don't immediately 2412b9171541SChris Wilson * follow the lower 32bits, the offset of the lower 32bits must 2413b9171541SChris Wilson * be specified 2414b9171541SChris Wilson */ 2415b9171541SChris Wilson __u64 offset; 2416b9171541SChris Wilson #define I915_REG_READ_8B_WA (1ul << 0) 2417b9171541SChris Wilson 2418b9171541SChris Wilson __u64 val; /* Return value */ 2419b9171541SChris Wilson }; 2420b9171541SChris Wilson 2421b9171541SChris Wilson /* Known registers: 2422b9171541SChris Wilson * 2423b9171541SChris Wilson * Render engine timestamp - 0x2358 + 64bit - gen7+ 2424b9171541SChris Wilson * - Note this register returns an invalid value if using the default 2425b9171541SChris Wilson * single instruction 8byte read, in order to workaround that pass 2426b9171541SChris Wilson * flag I915_REG_READ_8B_WA in offset field. 2427b9171541SChris Wilson * 2428b9171541SChris Wilson */ 2429b9171541SChris Wilson 2430b9171541SChris Wilson struct drm_i915_reset_stats { 2431b9171541SChris Wilson __u32 ctx_id; 2432b9171541SChris Wilson __u32 flags; 2433b9171541SChris Wilson 2434b9171541SChris Wilson /* All resets since boot/module reload, for all contexts */ 2435b9171541SChris Wilson __u32 reset_count; 2436b9171541SChris Wilson 2437b9171541SChris Wilson /* Number of batches lost when active in GPU, for this context */ 2438b9171541SChris Wilson __u32 batch_active; 2439b9171541SChris Wilson 2440b9171541SChris Wilson /* Number of batches lost pending for execution, for this context */ 2441b9171541SChris Wilson __u32 batch_pending; 2442b9171541SChris Wilson 2443b9171541SChris Wilson __u32 pad; 2444b9171541SChris Wilson }; 2445b9171541SChris Wilson 2446aef7b67aSMatthew Auld /** 2447aef7b67aSMatthew Auld * struct drm_i915_gem_userptr - Create GEM object from user allocated memory. 2448aef7b67aSMatthew Auld * 2449aef7b67aSMatthew Auld * Userptr objects have several restrictions on what ioctls can be used with the 2450aef7b67aSMatthew Auld * object handle. 2451aef7b67aSMatthew Auld */ 2452b9171541SChris Wilson struct drm_i915_gem_userptr { 2453aef7b67aSMatthew Auld /** 2454aef7b67aSMatthew Auld * @user_ptr: The pointer to the allocated memory. 2455aef7b67aSMatthew Auld * 2456aef7b67aSMatthew Auld * Needs to be aligned to PAGE_SIZE. 2457aef7b67aSMatthew Auld */ 2458b9171541SChris Wilson __u64 user_ptr; 2459aef7b67aSMatthew Auld 2460aef7b67aSMatthew Auld /** 2461aef7b67aSMatthew Auld * @user_size: 2462aef7b67aSMatthew Auld * 2463aef7b67aSMatthew Auld * The size in bytes for the allocated memory. This will also become the 2464aef7b67aSMatthew Auld * object size. 2465aef7b67aSMatthew Auld * 2466aef7b67aSMatthew Auld * Needs to be aligned to PAGE_SIZE, and should be at least PAGE_SIZE, 2467aef7b67aSMatthew Auld * or larger. 2468aef7b67aSMatthew Auld */ 2469b9171541SChris Wilson __u64 user_size; 2470aef7b67aSMatthew Auld 2471aef7b67aSMatthew Auld /** 2472aef7b67aSMatthew Auld * @flags: 2473aef7b67aSMatthew Auld * 2474aef7b67aSMatthew Auld * Supported flags: 2475aef7b67aSMatthew Auld * 2476aef7b67aSMatthew Auld * I915_USERPTR_READ_ONLY: 2477aef7b67aSMatthew Auld * 2478aef7b67aSMatthew Auld * Mark the object as readonly, this also means GPU access can only be 2479aef7b67aSMatthew Auld * readonly. This is only supported on HW which supports readonly access 2480aef7b67aSMatthew Auld * through the GTT. If the HW can't support readonly access, an error is 2481aef7b67aSMatthew Auld * returned. 2482aef7b67aSMatthew Auld * 2483b65a9489SChris Wilson * I915_USERPTR_PROBE: 2484b65a9489SChris Wilson * 2485b65a9489SChris Wilson * Probe the provided @user_ptr range and validate that the @user_ptr is 2486b65a9489SChris Wilson * indeed pointing to normal memory and that the range is also valid. 2487b65a9489SChris Wilson * For example if some garbage address is given to the kernel, then this 2488b65a9489SChris Wilson * should complain. 2489b65a9489SChris Wilson * 2490b65a9489SChris Wilson * Returns -EFAULT if the probe failed. 2491b65a9489SChris Wilson * 2492b65a9489SChris Wilson * Note that this doesn't populate the backing pages, and also doesn't 2493b65a9489SChris Wilson * guarantee that the object will remain valid when the object is 2494b65a9489SChris Wilson * eventually used. 2495b65a9489SChris Wilson * 2496b65a9489SChris Wilson * The kernel supports this feature if I915_PARAM_HAS_USERPTR_PROBE 2497b65a9489SChris Wilson * returns a non-zero value. 2498b65a9489SChris Wilson * 2499aef7b67aSMatthew Auld * I915_USERPTR_UNSYNCHRONIZED: 2500aef7b67aSMatthew Auld * 2501aef7b67aSMatthew Auld * NOT USED. Setting this flag will result in an error. 2502aef7b67aSMatthew Auld */ 2503b9171541SChris Wilson __u32 flags; 2504b9171541SChris Wilson #define I915_USERPTR_READ_ONLY 0x1 2505b65a9489SChris Wilson #define I915_USERPTR_PROBE 0x2 2506b9171541SChris Wilson #define I915_USERPTR_UNSYNCHRONIZED 0x80000000 2507b9171541SChris Wilson /** 2508aef7b67aSMatthew Auld * @handle: Returned handle for the object. 2509b9171541SChris Wilson * 2510b9171541SChris Wilson * Object handles are nonzero. 2511b9171541SChris Wilson */ 2512b9171541SChris Wilson __u32 handle; 2513b9171541SChris Wilson }; 2514b9171541SChris Wilson 2515d7965152SRobert Bragg enum drm_i915_oa_format { 251619f81df2SRobert Bragg I915_OA_FORMAT_A13 = 1, /* HSW only */ 251719f81df2SRobert Bragg I915_OA_FORMAT_A29, /* HSW only */ 251819f81df2SRobert Bragg I915_OA_FORMAT_A13_B8_C8, /* HSW only */ 251919f81df2SRobert Bragg I915_OA_FORMAT_B4_C8, /* HSW only */ 252019f81df2SRobert Bragg I915_OA_FORMAT_A45_B8_C8, /* HSW only */ 252119f81df2SRobert Bragg I915_OA_FORMAT_B4_C8_A16, /* HSW only */ 252219f81df2SRobert Bragg I915_OA_FORMAT_C4_B8, /* HSW+ */ 252319f81df2SRobert Bragg 252419f81df2SRobert Bragg /* Gen8+ */ 252519f81df2SRobert Bragg I915_OA_FORMAT_A12, 252619f81df2SRobert Bragg I915_OA_FORMAT_A12_B8_C8, 252719f81df2SRobert Bragg I915_OA_FORMAT_A32u40_A4u32_B8_C8, 2528d7965152SRobert Bragg 2529d7965152SRobert Bragg I915_OA_FORMAT_MAX /* non-ABI */ 2530d7965152SRobert Bragg }; 2531d7965152SRobert Bragg 2532eec688e1SRobert Bragg enum drm_i915_perf_property_id { 2533eec688e1SRobert Bragg /** 2534eec688e1SRobert Bragg * Open the stream for a specific context handle (as used with 2535eec688e1SRobert Bragg * execbuffer2). A stream opened for a specific context this way 2536eec688e1SRobert Bragg * won't typically require root privileges. 2537b8d49f28SLionel Landwerlin * 2538b8d49f28SLionel Landwerlin * This property is available in perf revision 1. 2539eec688e1SRobert Bragg */ 2540eec688e1SRobert Bragg DRM_I915_PERF_PROP_CTX_HANDLE = 1, 2541eec688e1SRobert Bragg 2542d7965152SRobert Bragg /** 2543d7965152SRobert Bragg * A value of 1 requests the inclusion of raw OA unit reports as 2544d7965152SRobert Bragg * part of stream samples. 2545b8d49f28SLionel Landwerlin * 2546b8d49f28SLionel Landwerlin * This property is available in perf revision 1. 2547d7965152SRobert Bragg */ 2548d7965152SRobert Bragg DRM_I915_PERF_PROP_SAMPLE_OA, 2549d7965152SRobert Bragg 2550d7965152SRobert Bragg /** 2551d7965152SRobert Bragg * The value specifies which set of OA unit metrics should be 255266137f54SRandy Dunlap * configured, defining the contents of any OA unit reports. 2553b8d49f28SLionel Landwerlin * 2554b8d49f28SLionel Landwerlin * This property is available in perf revision 1. 2555d7965152SRobert Bragg */ 2556d7965152SRobert Bragg DRM_I915_PERF_PROP_OA_METRICS_SET, 2557d7965152SRobert Bragg 2558d7965152SRobert Bragg /** 2559d7965152SRobert Bragg * The value specifies the size and layout of OA unit reports. 2560b8d49f28SLionel Landwerlin * 2561b8d49f28SLionel Landwerlin * This property is available in perf revision 1. 2562d7965152SRobert Bragg */ 2563d7965152SRobert Bragg DRM_I915_PERF_PROP_OA_FORMAT, 2564d7965152SRobert Bragg 2565d7965152SRobert Bragg /** 2566d7965152SRobert Bragg * Specifying this property implicitly requests periodic OA unit 2567d7965152SRobert Bragg * sampling and (at least on Haswell) the sampling frequency is derived 2568d7965152SRobert Bragg * from this exponent as follows: 2569d7965152SRobert Bragg * 2570d7965152SRobert Bragg * 80ns * 2^(period_exponent + 1) 2571b8d49f28SLionel Landwerlin * 2572b8d49f28SLionel Landwerlin * This property is available in perf revision 1. 2573d7965152SRobert Bragg */ 2574d7965152SRobert Bragg DRM_I915_PERF_PROP_OA_EXPONENT, 2575d7965152SRobert Bragg 25769cd20ef7SLionel Landwerlin /** 25779cd20ef7SLionel Landwerlin * Specifying this property is only valid when specify a context to 25789cd20ef7SLionel Landwerlin * filter with DRM_I915_PERF_PROP_CTX_HANDLE. Specifying this property 25799cd20ef7SLionel Landwerlin * will hold preemption of the particular context we want to gather 25809cd20ef7SLionel Landwerlin * performance data about. The execbuf2 submissions must include a 25819cd20ef7SLionel Landwerlin * drm_i915_gem_execbuffer_ext_perf parameter for this to apply. 25829cd20ef7SLionel Landwerlin * 25839cd20ef7SLionel Landwerlin * This property is available in perf revision 3. 25849cd20ef7SLionel Landwerlin */ 25859cd20ef7SLionel Landwerlin DRM_I915_PERF_PROP_HOLD_PREEMPTION, 25869cd20ef7SLionel Landwerlin 258711ecbdddSLionel Landwerlin /** 258811ecbdddSLionel Landwerlin * Specifying this pins all contexts to the specified SSEU power 258911ecbdddSLionel Landwerlin * configuration for the duration of the recording. 259011ecbdddSLionel Landwerlin * 259111ecbdddSLionel Landwerlin * This parameter's value is a pointer to a struct 259211ecbdddSLionel Landwerlin * drm_i915_gem_context_param_sseu. 259311ecbdddSLionel Landwerlin * 259411ecbdddSLionel Landwerlin * This property is available in perf revision 4. 259511ecbdddSLionel Landwerlin */ 259611ecbdddSLionel Landwerlin DRM_I915_PERF_PROP_GLOBAL_SSEU, 259711ecbdddSLionel Landwerlin 25984ef10fe0SLionel Landwerlin /** 25994ef10fe0SLionel Landwerlin * This optional parameter specifies the timer interval in nanoseconds 26004ef10fe0SLionel Landwerlin * at which the i915 driver will check the OA buffer for available data. 26014ef10fe0SLionel Landwerlin * Minimum allowed value is 100 microseconds. A default value is used by 26024ef10fe0SLionel Landwerlin * the driver if this parameter is not specified. Note that larger timer 26034ef10fe0SLionel Landwerlin * values will reduce cpu consumption during OA perf captures. However, 26044ef10fe0SLionel Landwerlin * excessively large values would potentially result in OA buffer 26054ef10fe0SLionel Landwerlin * overwrites as captures reach end of the OA buffer. 26064ef10fe0SLionel Landwerlin * 26074ef10fe0SLionel Landwerlin * This property is available in perf revision 5. 26084ef10fe0SLionel Landwerlin */ 26094ef10fe0SLionel Landwerlin DRM_I915_PERF_PROP_POLL_OA_PERIOD, 26104ef10fe0SLionel Landwerlin 2611eec688e1SRobert Bragg DRM_I915_PERF_PROP_MAX /* non-ABI */ 2612eec688e1SRobert Bragg }; 2613eec688e1SRobert Bragg 2614eec688e1SRobert Bragg struct drm_i915_perf_open_param { 2615eec688e1SRobert Bragg __u32 flags; 2616eec688e1SRobert Bragg #define I915_PERF_FLAG_FD_CLOEXEC (1<<0) 2617eec688e1SRobert Bragg #define I915_PERF_FLAG_FD_NONBLOCK (1<<1) 2618eec688e1SRobert Bragg #define I915_PERF_FLAG_DISABLED (1<<2) 2619eec688e1SRobert Bragg 2620eec688e1SRobert Bragg /** The number of u64 (id, value) pairs */ 2621eec688e1SRobert Bragg __u32 num_properties; 2622eec688e1SRobert Bragg 2623eec688e1SRobert Bragg /** 2624eec688e1SRobert Bragg * Pointer to array of u64 (id, value) pairs configuring the stream 2625eec688e1SRobert Bragg * to open. 2626eec688e1SRobert Bragg */ 2627cd8bddc4SChris Wilson __u64 properties_ptr; 2628eec688e1SRobert Bragg }; 2629eec688e1SRobert Bragg 26302ef6a01fSMatthew Auld /* 2631d7965152SRobert Bragg * Enable data capture for a stream that was either opened in a disabled state 2632d7965152SRobert Bragg * via I915_PERF_FLAG_DISABLED or was later disabled via 2633d7965152SRobert Bragg * I915_PERF_IOCTL_DISABLE. 2634d7965152SRobert Bragg * 2635d7965152SRobert Bragg * It is intended to be cheaper to disable and enable a stream than it may be 2636d7965152SRobert Bragg * to close and re-open a stream with the same configuration. 2637d7965152SRobert Bragg * 2638d7965152SRobert Bragg * It's undefined whether any pending data for the stream will be lost. 2639b8d49f28SLionel Landwerlin * 2640b8d49f28SLionel Landwerlin * This ioctl is available in perf revision 1. 2641d7965152SRobert Bragg */ 2642eec688e1SRobert Bragg #define I915_PERF_IOCTL_ENABLE _IO('i', 0x0) 2643d7965152SRobert Bragg 26442ef6a01fSMatthew Auld /* 2645d7965152SRobert Bragg * Disable data capture for a stream. 2646d7965152SRobert Bragg * 2647d7965152SRobert Bragg * It is an error to try and read a stream that is disabled. 2648b8d49f28SLionel Landwerlin * 2649b8d49f28SLionel Landwerlin * This ioctl is available in perf revision 1. 2650d7965152SRobert Bragg */ 2651eec688e1SRobert Bragg #define I915_PERF_IOCTL_DISABLE _IO('i', 0x1) 2652eec688e1SRobert Bragg 26532ef6a01fSMatthew Auld /* 26547831e9a9SChris Wilson * Change metrics_set captured by a stream. 26557831e9a9SChris Wilson * 26567831e9a9SChris Wilson * If the stream is bound to a specific context, the configuration change 26577831e9a9SChris Wilson * will performed inline with that context such that it takes effect before 26587831e9a9SChris Wilson * the next execbuf submission. 26597831e9a9SChris Wilson * 26607831e9a9SChris Wilson * Returns the previously bound metrics set id, or a negative error code. 26617831e9a9SChris Wilson * 26627831e9a9SChris Wilson * This ioctl is available in perf revision 2. 26637831e9a9SChris Wilson */ 26647831e9a9SChris Wilson #define I915_PERF_IOCTL_CONFIG _IO('i', 0x2) 26657831e9a9SChris Wilson 26662ef6a01fSMatthew Auld /* 2667eec688e1SRobert Bragg * Common to all i915 perf records 2668eec688e1SRobert Bragg */ 2669eec688e1SRobert Bragg struct drm_i915_perf_record_header { 2670eec688e1SRobert Bragg __u32 type; 2671eec688e1SRobert Bragg __u16 pad; 2672eec688e1SRobert Bragg __u16 size; 2673eec688e1SRobert Bragg }; 2674eec688e1SRobert Bragg 2675eec688e1SRobert Bragg enum drm_i915_perf_record_type { 2676eec688e1SRobert Bragg 2677eec688e1SRobert Bragg /** 2678eec688e1SRobert Bragg * Samples are the work horse record type whose contents are extensible 2679eec688e1SRobert Bragg * and defined when opening an i915 perf stream based on the given 2680eec688e1SRobert Bragg * properties. 2681eec688e1SRobert Bragg * 2682eec688e1SRobert Bragg * Boolean properties following the naming convention 2683eec688e1SRobert Bragg * DRM_I915_PERF_SAMPLE_xyz_PROP request the inclusion of 'xyz' data in 2684eec688e1SRobert Bragg * every sample. 2685eec688e1SRobert Bragg * 2686eec688e1SRobert Bragg * The order of these sample properties given by userspace has no 2687d7965152SRobert Bragg * affect on the ordering of data within a sample. The order is 2688eec688e1SRobert Bragg * documented here. 2689eec688e1SRobert Bragg * 2690eec688e1SRobert Bragg * struct { 2691eec688e1SRobert Bragg * struct drm_i915_perf_record_header header; 2692eec688e1SRobert Bragg * 2693d7965152SRobert Bragg * { u32 oa_report[]; } && DRM_I915_PERF_PROP_SAMPLE_OA 2694eec688e1SRobert Bragg * }; 2695eec688e1SRobert Bragg */ 2696eec688e1SRobert Bragg DRM_I915_PERF_RECORD_SAMPLE = 1, 2697eec688e1SRobert Bragg 2698d7965152SRobert Bragg /* 2699d7965152SRobert Bragg * Indicates that one or more OA reports were not written by the 2700d7965152SRobert Bragg * hardware. This can happen for example if an MI_REPORT_PERF_COUNT 2701d7965152SRobert Bragg * command collides with periodic sampling - which would be more likely 2702d7965152SRobert Bragg * at higher sampling frequencies. 2703d7965152SRobert Bragg */ 2704d7965152SRobert Bragg DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2, 2705d7965152SRobert Bragg 2706d7965152SRobert Bragg /** 2707d7965152SRobert Bragg * An error occurred that resulted in all pending OA reports being lost. 2708d7965152SRobert Bragg */ 2709d7965152SRobert Bragg DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3, 2710d7965152SRobert Bragg 2711eec688e1SRobert Bragg DRM_I915_PERF_RECORD_MAX /* non-ABI */ 2712eec688e1SRobert Bragg }; 2713eec688e1SRobert Bragg 2714a2e54026SMatt Roper /** 2715a2e54026SMatt Roper * struct drm_i915_perf_oa_config 2716a2e54026SMatt Roper * 2717f89823c2SLionel Landwerlin * Structure to upload perf dynamic configuration into the kernel. 2718f89823c2SLionel Landwerlin */ 2719f89823c2SLionel Landwerlin struct drm_i915_perf_oa_config { 2720a2e54026SMatt Roper /** 2721a2e54026SMatt Roper * @uuid: 2722a2e54026SMatt Roper * 2723a2e54026SMatt Roper * String formatted like "%\08x-%\04x-%\04x-%\04x-%\012x" 2724a2e54026SMatt Roper */ 2725f89823c2SLionel Landwerlin char uuid[36]; 2726f89823c2SLionel Landwerlin 2727a2e54026SMatt Roper /** 2728a2e54026SMatt Roper * @n_mux_regs: 2729a2e54026SMatt Roper * 2730a2e54026SMatt Roper * Number of mux regs in &mux_regs_ptr. 2731a2e54026SMatt Roper */ 2732f89823c2SLionel Landwerlin __u32 n_mux_regs; 2733a2e54026SMatt Roper 2734a2e54026SMatt Roper /** 2735a2e54026SMatt Roper * @n_boolean_regs: 2736a2e54026SMatt Roper * 2737a2e54026SMatt Roper * Number of boolean regs in &boolean_regs_ptr. 2738a2e54026SMatt Roper */ 2739f89823c2SLionel Landwerlin __u32 n_boolean_regs; 2740a2e54026SMatt Roper 2741a2e54026SMatt Roper /** 2742a2e54026SMatt Roper * @n_flex_regs: 2743a2e54026SMatt Roper * 2744a2e54026SMatt Roper * Number of flex regs in &flex_regs_ptr. 2745a2e54026SMatt Roper */ 2746f89823c2SLionel Landwerlin __u32 n_flex_regs; 2747f89823c2SLionel Landwerlin 2748a2e54026SMatt Roper /** 2749a2e54026SMatt Roper * @mux_regs_ptr: 2750a2e54026SMatt Roper * 2751a2e54026SMatt Roper * Pointer to tuples of u32 values (register address, value) for mux 2752a2e54026SMatt Roper * registers. Expected length of buffer is (2 * sizeof(u32) * 2753a2e54026SMatt Roper * &n_mux_regs). 2754ee427e25SLionel Landwerlin */ 275517ad4fddSChris Wilson __u64 mux_regs_ptr; 2756a2e54026SMatt Roper 2757a2e54026SMatt Roper /** 2758a2e54026SMatt Roper * @boolean_regs_ptr: 2759a2e54026SMatt Roper * 2760a2e54026SMatt Roper * Pointer to tuples of u32 values (register address, value) for mux 2761a2e54026SMatt Roper * registers. Expected length of buffer is (2 * sizeof(u32) * 2762a2e54026SMatt Roper * &n_boolean_regs). 2763a2e54026SMatt Roper */ 276417ad4fddSChris Wilson __u64 boolean_regs_ptr; 2765a2e54026SMatt Roper 2766a2e54026SMatt Roper /** 2767a2e54026SMatt Roper * @flex_regs_ptr: 2768a2e54026SMatt Roper * 2769a2e54026SMatt Roper * Pointer to tuples of u32 values (register address, value) for mux 2770a2e54026SMatt Roper * registers. Expected length of buffer is (2 * sizeof(u32) * 2771a2e54026SMatt Roper * &n_flex_regs). 2772a2e54026SMatt Roper */ 277317ad4fddSChris Wilson __u64 flex_regs_ptr; 2774f89823c2SLionel Landwerlin }; 2775f89823c2SLionel Landwerlin 2776e3bdccafSMatthew Auld /** 2777e3bdccafSMatthew Auld * struct drm_i915_query_item - An individual query for the kernel to process. 2778e3bdccafSMatthew Auld * 2779e3bdccafSMatthew Auld * The behaviour is determined by the @query_id. Note that exactly what 2780e3bdccafSMatthew Auld * @data_ptr is also depends on the specific @query_id. 2781e3bdccafSMatthew Auld */ 2782a446ae2cSLionel Landwerlin struct drm_i915_query_item { 27831c671ad7SMatt Roper /** 27841c671ad7SMatt Roper * @query_id: 27851c671ad7SMatt Roper * 27861c671ad7SMatt Roper * The id for this query. Currently accepted query IDs are: 27871c671ad7SMatt Roper * - %DRM_I915_QUERY_TOPOLOGY_INFO (see struct drm_i915_query_topology_info) 27881c671ad7SMatt Roper * - %DRM_I915_QUERY_ENGINE_INFO (see struct drm_i915_engine_info) 27891c671ad7SMatt Roper * - %DRM_I915_QUERY_PERF_CONFIG (see struct drm_i915_query_perf_config) 27901c671ad7SMatt Roper * - %DRM_I915_QUERY_MEMORY_REGIONS (see struct drm_i915_query_memory_regions) 27911c671ad7SMatt Roper * - %DRM_I915_QUERY_HWCONFIG_BLOB (see `GuC HWCONFIG blob uAPI`) 2792c94fde8fSMatt Atwood * - %DRM_I915_QUERY_GEOMETRY_SUBSLICES (see struct drm_i915_query_topology_info) 27931c671ad7SMatt Roper */ 2794a446ae2cSLionel Landwerlin __u64 query_id; 2795c822e059SLionel Landwerlin #define DRM_I915_QUERY_TOPOLOGY_INFO 1 2796c5d3e39cSTvrtko Ursulin #define DRM_I915_QUERY_ENGINE_INFO 2 27974f6ccc74SLionel Landwerlin #define DRM_I915_QUERY_PERF_CONFIG 3 279871021729SAbdiel Janulgue #define DRM_I915_QUERY_MEMORY_REGIONS 4 279978e1fb31SRodrigo Vivi #define DRM_I915_QUERY_HWCONFIG_BLOB 5 2800c94fde8fSMatt Atwood #define DRM_I915_QUERY_GEOMETRY_SUBSLICES 6 2801be03564bSChris Wilson /* Must be kept compact -- no holes and well documented */ 2802a446ae2cSLionel Landwerlin 2803e3bdccafSMatthew Auld /** 2804e3bdccafSMatthew Auld * @length: 2805e3bdccafSMatthew Auld * 2806a446ae2cSLionel Landwerlin * When set to zero by userspace, this is filled with the size of the 2807e3bdccafSMatthew Auld * data to be written at the @data_ptr pointer. The kernel sets this 2808a446ae2cSLionel Landwerlin * value to a negative value to signal an error on a particular query 2809a446ae2cSLionel Landwerlin * item. 2810a446ae2cSLionel Landwerlin */ 2811a446ae2cSLionel Landwerlin __s32 length; 2812a446ae2cSLionel Landwerlin 2813e3bdccafSMatthew Auld /** 2814e3bdccafSMatthew Auld * @flags: 2815e3bdccafSMatthew Auld * 28161c671ad7SMatt Roper * When &query_id == %DRM_I915_QUERY_TOPOLOGY_INFO, must be 0. 28174f6ccc74SLionel Landwerlin * 28181c671ad7SMatt Roper * When &query_id == %DRM_I915_QUERY_PERF_CONFIG, must be one of the 28194f6ccc74SLionel Landwerlin * following: 2820e3bdccafSMatthew Auld * 28211c671ad7SMatt Roper * - %DRM_I915_QUERY_PERF_CONFIG_LIST 28221c671ad7SMatt Roper * - %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID 28231c671ad7SMatt Roper * - %DRM_I915_QUERY_PERF_CONFIG_FOR_UUID 2824c94fde8fSMatt Atwood * 2825c94fde8fSMatt Atwood * When &query_id == %DRM_I915_QUERY_GEOMETRY_SUBSLICES must contain 2826c94fde8fSMatt Atwood * a struct i915_engine_class_instance that references a render engine. 2827a446ae2cSLionel Landwerlin */ 2828a446ae2cSLionel Landwerlin __u32 flags; 28294f6ccc74SLionel Landwerlin #define DRM_I915_QUERY_PERF_CONFIG_LIST 1 28304f6ccc74SLionel Landwerlin #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID 2 28314f6ccc74SLionel Landwerlin #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID 3 2832a446ae2cSLionel Landwerlin 2833e3bdccafSMatthew Auld /** 2834e3bdccafSMatthew Auld * @data_ptr: 2835e3bdccafSMatthew Auld * 2836e3bdccafSMatthew Auld * Data will be written at the location pointed by @data_ptr when the 2837e3bdccafSMatthew Auld * value of @length matches the length of the data to be written by the 2838a446ae2cSLionel Landwerlin * kernel. 2839a446ae2cSLionel Landwerlin */ 2840a446ae2cSLionel Landwerlin __u64 data_ptr; 2841a446ae2cSLionel Landwerlin }; 2842a446ae2cSLionel Landwerlin 2843e3bdccafSMatthew Auld /** 2844e3bdccafSMatthew Auld * struct drm_i915_query - Supply an array of struct drm_i915_query_item for the 2845e3bdccafSMatthew Auld * kernel to fill out. 2846e3bdccafSMatthew Auld * 2847e3bdccafSMatthew Auld * Note that this is generally a two step process for each struct 2848e3bdccafSMatthew Auld * drm_i915_query_item in the array: 2849e3bdccafSMatthew Auld * 2850e3bdccafSMatthew Auld * 1. Call the DRM_IOCTL_I915_QUERY, giving it our array of struct 2851e3bdccafSMatthew Auld * drm_i915_query_item, with &drm_i915_query_item.length set to zero. The 2852e3bdccafSMatthew Auld * kernel will then fill in the size, in bytes, which tells userspace how 2853e3bdccafSMatthew Auld * memory it needs to allocate for the blob(say for an array of properties). 2854e3bdccafSMatthew Auld * 2855e3bdccafSMatthew Auld * 2. Next we call DRM_IOCTL_I915_QUERY again, this time with the 2856e3bdccafSMatthew Auld * &drm_i915_query_item.data_ptr equal to our newly allocated blob. Note that 2857e3bdccafSMatthew Auld * the &drm_i915_query_item.length should still be the same as what the 2858e3bdccafSMatthew Auld * kernel previously set. At this point the kernel can fill in the blob. 2859e3bdccafSMatthew Auld * 2860e3bdccafSMatthew Auld * Note that for some query items it can make sense for userspace to just pass 2861e3bdccafSMatthew Auld * in a buffer/blob equal to or larger than the required size. In this case only 2862e3bdccafSMatthew Auld * a single ioctl call is needed. For some smaller query items this can work 2863e3bdccafSMatthew Auld * quite well. 2864e3bdccafSMatthew Auld * 2865e3bdccafSMatthew Auld */ 2866a446ae2cSLionel Landwerlin struct drm_i915_query { 2867e3bdccafSMatthew Auld /** @num_items: The number of elements in the @items_ptr array */ 2868a446ae2cSLionel Landwerlin __u32 num_items; 2869a446ae2cSLionel Landwerlin 2870e3bdccafSMatthew Auld /** 2871e3bdccafSMatthew Auld * @flags: Unused for now. Must be cleared to zero. 2872a446ae2cSLionel Landwerlin */ 2873a446ae2cSLionel Landwerlin __u32 flags; 2874a446ae2cSLionel Landwerlin 2875e3bdccafSMatthew Auld /** 2876e3bdccafSMatthew Auld * @items_ptr: 2877e3bdccafSMatthew Auld * 2878e3bdccafSMatthew Auld * Pointer to an array of struct drm_i915_query_item. The number of 2879e3bdccafSMatthew Auld * array elements is @num_items. 2880a446ae2cSLionel Landwerlin */ 2881a446ae2cSLionel Landwerlin __u64 items_ptr; 2882a446ae2cSLionel Landwerlin }; 2883a446ae2cSLionel Landwerlin 2884462ac1cdSMatt Roper /** 2885462ac1cdSMatt Roper * struct drm_i915_query_topology_info 2886c822e059SLionel Landwerlin * 2887462ac1cdSMatt Roper * Describes slice/subslice/EU information queried by 2888462ac1cdSMatt Roper * %DRM_I915_QUERY_TOPOLOGY_INFO 2889c822e059SLionel Landwerlin */ 2890c822e059SLionel Landwerlin struct drm_i915_query_topology_info { 2891462ac1cdSMatt Roper /** 2892462ac1cdSMatt Roper * @flags: 2893462ac1cdSMatt Roper * 2894c822e059SLionel Landwerlin * Unused for now. Must be cleared to zero. 2895c822e059SLionel Landwerlin */ 2896c822e059SLionel Landwerlin __u16 flags; 2897c822e059SLionel Landwerlin 2898462ac1cdSMatt Roper /** 2899462ac1cdSMatt Roper * @max_slices: 2900462ac1cdSMatt Roper * 2901462ac1cdSMatt Roper * The number of bits used to express the slice mask. 2902462ac1cdSMatt Roper */ 2903c822e059SLionel Landwerlin __u16 max_slices; 2904462ac1cdSMatt Roper 2905462ac1cdSMatt Roper /** 2906462ac1cdSMatt Roper * @max_subslices: 2907462ac1cdSMatt Roper * 2908462ac1cdSMatt Roper * The number of bits used to express the subslice mask. 2909462ac1cdSMatt Roper */ 2910c822e059SLionel Landwerlin __u16 max_subslices; 2911462ac1cdSMatt Roper 2912462ac1cdSMatt Roper /** 2913462ac1cdSMatt Roper * @max_eus_per_subslice: 2914462ac1cdSMatt Roper * 2915462ac1cdSMatt Roper * The number of bits in the EU mask that correspond to a single 2916462ac1cdSMatt Roper * subslice's EUs. 2917462ac1cdSMatt Roper */ 2918c822e059SLionel Landwerlin __u16 max_eus_per_subslice; 2919c822e059SLionel Landwerlin 2920462ac1cdSMatt Roper /** 2921462ac1cdSMatt Roper * @subslice_offset: 2922462ac1cdSMatt Roper * 2923c822e059SLionel Landwerlin * Offset in data[] at which the subslice masks are stored. 2924c822e059SLionel Landwerlin */ 2925c822e059SLionel Landwerlin __u16 subslice_offset; 2926c822e059SLionel Landwerlin 2927462ac1cdSMatt Roper /** 2928462ac1cdSMatt Roper * @subslice_stride: 2929462ac1cdSMatt Roper * 2930c822e059SLionel Landwerlin * Stride at which each of the subslice masks for each slice are 2931c822e059SLionel Landwerlin * stored. 2932c822e059SLionel Landwerlin */ 2933c822e059SLionel Landwerlin __u16 subslice_stride; 2934c822e059SLionel Landwerlin 2935462ac1cdSMatt Roper /** 2936462ac1cdSMatt Roper * @eu_offset: 2937462ac1cdSMatt Roper * 2938c822e059SLionel Landwerlin * Offset in data[] at which the EU masks are stored. 2939c822e059SLionel Landwerlin */ 2940c822e059SLionel Landwerlin __u16 eu_offset; 2941c822e059SLionel Landwerlin 2942462ac1cdSMatt Roper /** 2943462ac1cdSMatt Roper * @eu_stride: 2944462ac1cdSMatt Roper * 2945c822e059SLionel Landwerlin * Stride at which each of the EU masks for each subslice are stored. 2946c822e059SLionel Landwerlin */ 2947c822e059SLionel Landwerlin __u16 eu_stride; 2948c822e059SLionel Landwerlin 2949462ac1cdSMatt Roper /** 2950462ac1cdSMatt Roper * @data: 2951462ac1cdSMatt Roper * 2952462ac1cdSMatt Roper * Contains 3 pieces of information : 2953462ac1cdSMatt Roper * 2954462ac1cdSMatt Roper * - The slice mask with one bit per slice telling whether a slice is 2955462ac1cdSMatt Roper * available. The availability of slice X can be queried with the 2956462ac1cdSMatt Roper * following formula : 2957462ac1cdSMatt Roper * 2958462ac1cdSMatt Roper * .. code:: c 2959462ac1cdSMatt Roper * 2960462ac1cdSMatt Roper * (data[X / 8] >> (X % 8)) & 1 2961462ac1cdSMatt Roper * 2962462ac1cdSMatt Roper * Starting with Xe_HP platforms, Intel hardware no longer has 2963462ac1cdSMatt Roper * traditional slices so i915 will always report a single slice 2964462ac1cdSMatt Roper * (hardcoded slicemask = 0x1) which contains all of the platform's 2965462ac1cdSMatt Roper * subslices. I.e., the mask here does not reflect any of the newer 2966462ac1cdSMatt Roper * hardware concepts such as "gslices" or "cslices" since userspace 2967462ac1cdSMatt Roper * is capable of inferring those from the subslice mask. 2968462ac1cdSMatt Roper * 2969462ac1cdSMatt Roper * - The subslice mask for each slice with one bit per subslice telling 2970462ac1cdSMatt Roper * whether a subslice is available. Starting with Gen12 we use the 2971462ac1cdSMatt Roper * term "subslice" to refer to what the hardware documentation 2972462ac1cdSMatt Roper * describes as a "dual-subslices." The availability of subslice Y 2973462ac1cdSMatt Roper * in slice X can be queried with the following formula : 2974462ac1cdSMatt Roper * 2975462ac1cdSMatt Roper * .. code:: c 2976462ac1cdSMatt Roper * 2977462ac1cdSMatt Roper * (data[subslice_offset + X * subslice_stride + Y / 8] >> (Y % 8)) & 1 2978462ac1cdSMatt Roper * 2979462ac1cdSMatt Roper * - The EU mask for each subslice in each slice, with one bit per EU 2980462ac1cdSMatt Roper * telling whether an EU is available. The availability of EU Z in 2981462ac1cdSMatt Roper * subslice Y in slice X can be queried with the following formula : 2982462ac1cdSMatt Roper * 2983462ac1cdSMatt Roper * .. code:: c 2984462ac1cdSMatt Roper * 2985462ac1cdSMatt Roper * (data[eu_offset + 2986462ac1cdSMatt Roper * (X * max_subslices + Y) * eu_stride + 2987462ac1cdSMatt Roper * Z / 8 2988462ac1cdSMatt Roper * ] >> (Z % 8)) & 1 2989462ac1cdSMatt Roper */ 2990c822e059SLionel Landwerlin __u8 data[]; 2991c822e059SLionel Landwerlin }; 2992c822e059SLionel Landwerlin 2993c5d3e39cSTvrtko Ursulin /** 299457772953STvrtko Ursulin * DOC: Engine Discovery uAPI 299557772953STvrtko Ursulin * 299657772953STvrtko Ursulin * Engine discovery uAPI is a way of enumerating physical engines present in a 299757772953STvrtko Ursulin * GPU associated with an open i915 DRM file descriptor. This supersedes the old 299857772953STvrtko Ursulin * way of using `DRM_IOCTL_I915_GETPARAM` and engine identifiers like 299957772953STvrtko Ursulin * `I915_PARAM_HAS_BLT`. 300057772953STvrtko Ursulin * 300157772953STvrtko Ursulin * The need for this interface came starting with Icelake and newer GPUs, which 300257772953STvrtko Ursulin * started to establish a pattern of having multiple engines of a same class, 300357772953STvrtko Ursulin * where not all instances were always completely functionally equivalent. 300457772953STvrtko Ursulin * 300557772953STvrtko Ursulin * Entry point for this uapi is `DRM_IOCTL_I915_QUERY` with the 300657772953STvrtko Ursulin * `DRM_I915_QUERY_ENGINE_INFO` as the queried item id. 300757772953STvrtko Ursulin * 300857772953STvrtko Ursulin * Example for getting the list of engines: 300957772953STvrtko Ursulin * 301057772953STvrtko Ursulin * .. code-block:: C 301157772953STvrtko Ursulin * 301257772953STvrtko Ursulin * struct drm_i915_query_engine_info *info; 301357772953STvrtko Ursulin * struct drm_i915_query_item item = { 301457772953STvrtko Ursulin * .query_id = DRM_I915_QUERY_ENGINE_INFO; 301557772953STvrtko Ursulin * }; 301657772953STvrtko Ursulin * struct drm_i915_query query = { 301757772953STvrtko Ursulin * .num_items = 1, 301857772953STvrtko Ursulin * .items_ptr = (uintptr_t)&item, 301957772953STvrtko Ursulin * }; 302057772953STvrtko Ursulin * int err, i; 302157772953STvrtko Ursulin * 302257772953STvrtko Ursulin * // First query the size of the blob we need, this needs to be large 302357772953STvrtko Ursulin * // enough to hold our array of engines. The kernel will fill out the 302457772953STvrtko Ursulin * // item.length for us, which is the number of bytes we need. 302557772953STvrtko Ursulin * // 302657772953STvrtko Ursulin * // Alternatively a large buffer can be allocated straight away enabling 302757772953STvrtko Ursulin * // querying in one pass, in which case item.length should contain the 302857772953STvrtko Ursulin * // length of the provided buffer. 302957772953STvrtko Ursulin * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); 303057772953STvrtko Ursulin * if (err) ... 303157772953STvrtko Ursulin * 303257772953STvrtko Ursulin * info = calloc(1, item.length); 303357772953STvrtko Ursulin * // Now that we allocated the required number of bytes, we call the ioctl 303457772953STvrtko Ursulin * // again, this time with the data_ptr pointing to our newly allocated 303557772953STvrtko Ursulin * // blob, which the kernel can then populate with info on all engines. 303657772953STvrtko Ursulin * item.data_ptr = (uintptr_t)&info, 303757772953STvrtko Ursulin * 303857772953STvrtko Ursulin * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); 303957772953STvrtko Ursulin * if (err) ... 304057772953STvrtko Ursulin * 304157772953STvrtko Ursulin * // We can now access each engine in the array 304257772953STvrtko Ursulin * for (i = 0; i < info->num_engines; i++) { 304357772953STvrtko Ursulin * struct drm_i915_engine_info einfo = info->engines[i]; 304457772953STvrtko Ursulin * u16 class = einfo.engine.class; 304557772953STvrtko Ursulin * u16 instance = einfo.engine.instance; 304657772953STvrtko Ursulin * .... 304757772953STvrtko Ursulin * } 304857772953STvrtko Ursulin * 304957772953STvrtko Ursulin * free(info); 305057772953STvrtko Ursulin * 305157772953STvrtko Ursulin * Each of the enumerated engines, apart from being defined by its class and 305257772953STvrtko Ursulin * instance (see `struct i915_engine_class_instance`), also can have flags and 305357772953STvrtko Ursulin * capabilities defined as documented in i915_drm.h. 305457772953STvrtko Ursulin * 305557772953STvrtko Ursulin * For instance video engines which support HEVC encoding will have the 305657772953STvrtko Ursulin * `I915_VIDEO_CLASS_CAPABILITY_HEVC` capability bit set. 305757772953STvrtko Ursulin * 305857772953STvrtko Ursulin * Engine discovery only fully comes to its own when combined with the new way 305957772953STvrtko Ursulin * of addressing engines when submitting batch buffers using contexts with 306057772953STvrtko Ursulin * engine maps configured. 306157772953STvrtko Ursulin */ 306257772953STvrtko Ursulin 306357772953STvrtko Ursulin /** 3064c5d3e39cSTvrtko Ursulin * struct drm_i915_engine_info 3065c5d3e39cSTvrtko Ursulin * 3066c5d3e39cSTvrtko Ursulin * Describes one engine and it's capabilities as known to the driver. 3067c5d3e39cSTvrtko Ursulin */ 3068c5d3e39cSTvrtko Ursulin struct drm_i915_engine_info { 30692ef6a01fSMatthew Auld /** @engine: Engine class and instance. */ 3070c5d3e39cSTvrtko Ursulin struct i915_engine_class_instance engine; 3071c5d3e39cSTvrtko Ursulin 30722ef6a01fSMatthew Auld /** @rsvd0: Reserved field. */ 3073c5d3e39cSTvrtko Ursulin __u32 rsvd0; 3074c5d3e39cSTvrtko Ursulin 30752ef6a01fSMatthew Auld /** @flags: Engine flags. */ 3076c5d3e39cSTvrtko Ursulin __u64 flags; 30779409eb35SMatthew Brost #define I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE (1 << 0) 3078c5d3e39cSTvrtko Ursulin 30792ef6a01fSMatthew Auld /** @capabilities: Capabilities of this engine. */ 3080c5d3e39cSTvrtko Ursulin __u64 capabilities; 3081c5d3e39cSTvrtko Ursulin #define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0) 3082c5d3e39cSTvrtko Ursulin #define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1) 3083c5d3e39cSTvrtko Ursulin 30849409eb35SMatthew Brost /** @logical_instance: Logical instance of engine */ 30859409eb35SMatthew Brost __u16 logical_instance; 30869409eb35SMatthew Brost 30872ef6a01fSMatthew Auld /** @rsvd1: Reserved fields. */ 30889409eb35SMatthew Brost __u16 rsvd1[3]; 30899409eb35SMatthew Brost /** @rsvd2: Reserved fields. */ 30909409eb35SMatthew Brost __u64 rsvd2[3]; 3091c5d3e39cSTvrtko Ursulin }; 3092c5d3e39cSTvrtko Ursulin 3093c5d3e39cSTvrtko Ursulin /** 3094c5d3e39cSTvrtko Ursulin * struct drm_i915_query_engine_info 3095c5d3e39cSTvrtko Ursulin * 3096c5d3e39cSTvrtko Ursulin * Engine info query enumerates all engines known to the driver by filling in 3097c5d3e39cSTvrtko Ursulin * an array of struct drm_i915_engine_info structures. 3098c5d3e39cSTvrtko Ursulin */ 3099c5d3e39cSTvrtko Ursulin struct drm_i915_query_engine_info { 31002ef6a01fSMatthew Auld /** @num_engines: Number of struct drm_i915_engine_info structs following. */ 3101c5d3e39cSTvrtko Ursulin __u32 num_engines; 3102c5d3e39cSTvrtko Ursulin 31032ef6a01fSMatthew Auld /** @rsvd: MBZ */ 3104c5d3e39cSTvrtko Ursulin __u32 rsvd[3]; 3105c5d3e39cSTvrtko Ursulin 31062ef6a01fSMatthew Auld /** @engines: Marker for drm_i915_engine_info structures. */ 3107c5d3e39cSTvrtko Ursulin struct drm_i915_engine_info engines[]; 3108c5d3e39cSTvrtko Ursulin }; 3109c5d3e39cSTvrtko Ursulin 3110a2e54026SMatt Roper /** 3111a2e54026SMatt Roper * struct drm_i915_query_perf_config 3112a2e54026SMatt Roper * 3113c94fde8fSMatt Atwood * Data written by the kernel with query %DRM_I915_QUERY_PERF_CONFIG and 3114c94fde8fSMatt Atwood * %DRM_I915_QUERY_GEOMETRY_SUBSLICES. 31154f6ccc74SLionel Landwerlin */ 31164f6ccc74SLionel Landwerlin struct drm_i915_query_perf_config { 31174f6ccc74SLionel Landwerlin union { 3118a2e54026SMatt Roper /** 3119a2e54026SMatt Roper * @n_configs: 3120a2e54026SMatt Roper * 3121a2e54026SMatt Roper * When &drm_i915_query_item.flags == 3122a2e54026SMatt Roper * %DRM_I915_QUERY_PERF_CONFIG_LIST, i915 sets this fields to 3123a2e54026SMatt Roper * the number of configurations available. 31244f6ccc74SLionel Landwerlin */ 31254f6ccc74SLionel Landwerlin __u64 n_configs; 31264f6ccc74SLionel Landwerlin 3127a2e54026SMatt Roper /** 3128a2e54026SMatt Roper * @config: 3129a2e54026SMatt Roper * 3130a2e54026SMatt Roper * When &drm_i915_query_item.flags == 3131a2e54026SMatt Roper * %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID, i915 will use the 3132a2e54026SMatt Roper * value in this field as configuration identifier to decide 3133a2e54026SMatt Roper * what data to write into config_ptr. 31344f6ccc74SLionel Landwerlin */ 31354f6ccc74SLionel Landwerlin __u64 config; 31364f6ccc74SLionel Landwerlin 3137a2e54026SMatt Roper /** 3138a2e54026SMatt Roper * @uuid: 3139a2e54026SMatt Roper * 3140a2e54026SMatt Roper * When &drm_i915_query_item.flags == 3141a2e54026SMatt Roper * %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID, i915 will use the 3142a2e54026SMatt Roper * value in this field as configuration identifier to decide 3143a2e54026SMatt Roper * what data to write into config_ptr. 31444f6ccc74SLionel Landwerlin * 31454f6ccc74SLionel Landwerlin * String formatted like "%08x-%04x-%04x-%04x-%012x" 31464f6ccc74SLionel Landwerlin */ 31474f6ccc74SLionel Landwerlin char uuid[36]; 31484f6ccc74SLionel Landwerlin }; 31494f6ccc74SLionel Landwerlin 3150a2e54026SMatt Roper /** 3151a2e54026SMatt Roper * @flags: 3152a2e54026SMatt Roper * 31534f6ccc74SLionel Landwerlin * Unused for now. Must be cleared to zero. 31544f6ccc74SLionel Landwerlin */ 31554f6ccc74SLionel Landwerlin __u32 flags; 31564f6ccc74SLionel Landwerlin 3157a2e54026SMatt Roper /** 3158a2e54026SMatt Roper * @data: 31594f6ccc74SLionel Landwerlin * 3160a2e54026SMatt Roper * When &drm_i915_query_item.flags == %DRM_I915_QUERY_PERF_CONFIG_LIST, 3161a2e54026SMatt Roper * i915 will write an array of __u64 of configuration identifiers. 3162a2e54026SMatt Roper * 3163a2e54026SMatt Roper * When &drm_i915_query_item.flags == %DRM_I915_QUERY_PERF_CONFIG_DATA, 3164a2e54026SMatt Roper * i915 will write a struct drm_i915_perf_oa_config. If the following 3165a2e54026SMatt Roper * fields of struct drm_i915_perf_oa_config are not set to 0, i915 will 3166a2e54026SMatt Roper * write into the associated pointers the values of submitted when the 31674f6ccc74SLionel Landwerlin * configuration was created : 31684f6ccc74SLionel Landwerlin * 3169a2e54026SMatt Roper * - &drm_i915_perf_oa_config.n_mux_regs 3170a2e54026SMatt Roper * - &drm_i915_perf_oa_config.n_boolean_regs 3171a2e54026SMatt Roper * - &drm_i915_perf_oa_config.n_flex_regs 31724f6ccc74SLionel Landwerlin */ 31734f6ccc74SLionel Landwerlin __u8 data[]; 31744f6ccc74SLionel Landwerlin }; 31754f6ccc74SLionel Landwerlin 317671021729SAbdiel Janulgue /** 317771021729SAbdiel Janulgue * enum drm_i915_gem_memory_class - Supported memory classes 317871021729SAbdiel Janulgue */ 317971021729SAbdiel Janulgue enum drm_i915_gem_memory_class { 318071021729SAbdiel Janulgue /** @I915_MEMORY_CLASS_SYSTEM: System memory */ 318171021729SAbdiel Janulgue I915_MEMORY_CLASS_SYSTEM = 0, 318271021729SAbdiel Janulgue /** @I915_MEMORY_CLASS_DEVICE: Device local-memory */ 318371021729SAbdiel Janulgue I915_MEMORY_CLASS_DEVICE, 318471021729SAbdiel Janulgue }; 318571021729SAbdiel Janulgue 318671021729SAbdiel Janulgue /** 318771021729SAbdiel Janulgue * struct drm_i915_gem_memory_class_instance - Identify particular memory region 318871021729SAbdiel Janulgue */ 318971021729SAbdiel Janulgue struct drm_i915_gem_memory_class_instance { 319071021729SAbdiel Janulgue /** @memory_class: See enum drm_i915_gem_memory_class */ 319171021729SAbdiel Janulgue __u16 memory_class; 319271021729SAbdiel Janulgue 319371021729SAbdiel Janulgue /** @memory_instance: Which instance */ 319471021729SAbdiel Janulgue __u16 memory_instance; 319571021729SAbdiel Janulgue }; 319671021729SAbdiel Janulgue 319771021729SAbdiel Janulgue /** 319871021729SAbdiel Janulgue * struct drm_i915_memory_region_info - Describes one region as known to the 319971021729SAbdiel Janulgue * driver. 320071021729SAbdiel Janulgue * 320171021729SAbdiel Janulgue * Note that we reserve some stuff here for potential future work. As an example 320271021729SAbdiel Janulgue * we might want expose the capabilities for a given region, which could include 320371021729SAbdiel Janulgue * things like if the region is CPU mappable/accessible, what are the supported 320471021729SAbdiel Janulgue * mapping types etc. 320571021729SAbdiel Janulgue * 320671021729SAbdiel Janulgue * Note that to extend struct drm_i915_memory_region_info and struct 320771021729SAbdiel Janulgue * drm_i915_query_memory_regions in the future the plan is to do the following: 320871021729SAbdiel Janulgue * 320971021729SAbdiel Janulgue * .. code-block:: C 321071021729SAbdiel Janulgue * 321171021729SAbdiel Janulgue * struct drm_i915_memory_region_info { 321271021729SAbdiel Janulgue * struct drm_i915_gem_memory_class_instance region; 321371021729SAbdiel Janulgue * union { 321471021729SAbdiel Janulgue * __u32 rsvd0; 321571021729SAbdiel Janulgue * __u32 new_thing1; 321671021729SAbdiel Janulgue * }; 321771021729SAbdiel Janulgue * ... 321871021729SAbdiel Janulgue * union { 321971021729SAbdiel Janulgue * __u64 rsvd1[8]; 322071021729SAbdiel Janulgue * struct { 322171021729SAbdiel Janulgue * __u64 new_thing2; 322271021729SAbdiel Janulgue * __u64 new_thing3; 322371021729SAbdiel Janulgue * ... 322471021729SAbdiel Janulgue * }; 322571021729SAbdiel Janulgue * }; 322671021729SAbdiel Janulgue * }; 322771021729SAbdiel Janulgue * 322871021729SAbdiel Janulgue * With this things should remain source compatible between versions for 322971021729SAbdiel Janulgue * userspace, even as we add new fields. 323071021729SAbdiel Janulgue * 323171021729SAbdiel Janulgue * Note this is using both struct drm_i915_query_item and struct drm_i915_query. 323271021729SAbdiel Janulgue * For this new query we are adding the new query id DRM_I915_QUERY_MEMORY_REGIONS 323371021729SAbdiel Janulgue * at &drm_i915_query_item.query_id. 323471021729SAbdiel Janulgue */ 323571021729SAbdiel Janulgue struct drm_i915_memory_region_info { 323671021729SAbdiel Janulgue /** @region: The class:instance pair encoding */ 323771021729SAbdiel Janulgue struct drm_i915_gem_memory_class_instance region; 323871021729SAbdiel Janulgue 323971021729SAbdiel Janulgue /** @rsvd0: MBZ */ 324071021729SAbdiel Janulgue __u32 rsvd0; 324171021729SAbdiel Janulgue 324271021729SAbdiel Janulgue /** @probed_size: Memory probed by the driver (-1 = unknown) */ 324371021729SAbdiel Janulgue __u64 probed_size; 324471021729SAbdiel Janulgue 324571021729SAbdiel Janulgue /** @unallocated_size: Estimate of memory remaining (-1 = unknown) */ 324671021729SAbdiel Janulgue __u64 unallocated_size; 324771021729SAbdiel Janulgue 324871021729SAbdiel Janulgue /** @rsvd1: MBZ */ 324971021729SAbdiel Janulgue __u64 rsvd1[8]; 325071021729SAbdiel Janulgue }; 325171021729SAbdiel Janulgue 325271021729SAbdiel Janulgue /** 325371021729SAbdiel Janulgue * struct drm_i915_query_memory_regions 325471021729SAbdiel Janulgue * 325571021729SAbdiel Janulgue * The region info query enumerates all regions known to the driver by filling 325671021729SAbdiel Janulgue * in an array of struct drm_i915_memory_region_info structures. 325771021729SAbdiel Janulgue * 325871021729SAbdiel Janulgue * Example for getting the list of supported regions: 325971021729SAbdiel Janulgue * 326071021729SAbdiel Janulgue * .. code-block:: C 326171021729SAbdiel Janulgue * 326271021729SAbdiel Janulgue * struct drm_i915_query_memory_regions *info; 326371021729SAbdiel Janulgue * struct drm_i915_query_item item = { 326471021729SAbdiel Janulgue * .query_id = DRM_I915_QUERY_MEMORY_REGIONS; 326571021729SAbdiel Janulgue * }; 326671021729SAbdiel Janulgue * struct drm_i915_query query = { 326771021729SAbdiel Janulgue * .num_items = 1, 326871021729SAbdiel Janulgue * .items_ptr = (uintptr_t)&item, 326971021729SAbdiel Janulgue * }; 327071021729SAbdiel Janulgue * int err, i; 327171021729SAbdiel Janulgue * 327271021729SAbdiel Janulgue * // First query the size of the blob we need, this needs to be large 327371021729SAbdiel Janulgue * // enough to hold our array of regions. The kernel will fill out the 327471021729SAbdiel Janulgue * // item.length for us, which is the number of bytes we need. 327571021729SAbdiel Janulgue * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); 327671021729SAbdiel Janulgue * if (err) ... 327771021729SAbdiel Janulgue * 327871021729SAbdiel Janulgue * info = calloc(1, item.length); 327971021729SAbdiel Janulgue * // Now that we allocated the required number of bytes, we call the ioctl 328071021729SAbdiel Janulgue * // again, this time with the data_ptr pointing to our newly allocated 328171021729SAbdiel Janulgue * // blob, which the kernel can then populate with the all the region info. 328271021729SAbdiel Janulgue * item.data_ptr = (uintptr_t)&info, 328371021729SAbdiel Janulgue * 328471021729SAbdiel Janulgue * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); 328571021729SAbdiel Janulgue * if (err) ... 328671021729SAbdiel Janulgue * 328771021729SAbdiel Janulgue * // We can now access each region in the array 328871021729SAbdiel Janulgue * for (i = 0; i < info->num_regions; i++) { 328971021729SAbdiel Janulgue * struct drm_i915_memory_region_info mr = info->regions[i]; 329071021729SAbdiel Janulgue * u16 class = mr.region.class; 329171021729SAbdiel Janulgue * u16 instance = mr.region.instance; 329271021729SAbdiel Janulgue * 329371021729SAbdiel Janulgue * .... 329471021729SAbdiel Janulgue * } 329571021729SAbdiel Janulgue * 329671021729SAbdiel Janulgue * free(info); 329771021729SAbdiel Janulgue */ 329871021729SAbdiel Janulgue struct drm_i915_query_memory_regions { 329971021729SAbdiel Janulgue /** @num_regions: Number of supported regions */ 330071021729SAbdiel Janulgue __u32 num_regions; 330171021729SAbdiel Janulgue 330271021729SAbdiel Janulgue /** @rsvd: MBZ */ 330371021729SAbdiel Janulgue __u32 rsvd[3]; 330471021729SAbdiel Janulgue 330571021729SAbdiel Janulgue /** @regions: Info about each supported region */ 330671021729SAbdiel Janulgue struct drm_i915_memory_region_info regions[]; 330771021729SAbdiel Janulgue }; 330871021729SAbdiel Janulgue 3309ebcb4029SMatthew Auld /** 3310034d47b2STvrtko Ursulin * DOC: GuC HWCONFIG blob uAPI 3311034d47b2STvrtko Ursulin * 3312034d47b2STvrtko Ursulin * The GuC produces a blob with information about the current device. 3313034d47b2STvrtko Ursulin * i915 reads this blob from GuC and makes it available via this uAPI. 3314034d47b2STvrtko Ursulin * 3315034d47b2STvrtko Ursulin * The format and meaning of the blob content are documented in the 3316034d47b2STvrtko Ursulin * Programmer's Reference Manual. 3317034d47b2STvrtko Ursulin */ 3318034d47b2STvrtko Ursulin 3319034d47b2STvrtko Ursulin /** 3320ebcb4029SMatthew Auld * struct drm_i915_gem_create_ext - Existing gem_create behaviour, with added 3321ebcb4029SMatthew Auld * extension support using struct i915_user_extension. 3322ebcb4029SMatthew Auld * 3323ebcb4029SMatthew Auld * Note that in the future we want to have our buffer flags here, at least for 3324ebcb4029SMatthew Auld * the stuff that is immutable. Previously we would have two ioctls, one to 3325ebcb4029SMatthew Auld * create the object with gem_create, and another to apply various parameters, 3326ebcb4029SMatthew Auld * however this creates some ambiguity for the params which are considered 3327ebcb4029SMatthew Auld * immutable. Also in general we're phasing out the various SET/GET ioctls. 3328ebcb4029SMatthew Auld */ 3329ebcb4029SMatthew Auld struct drm_i915_gem_create_ext { 3330ebcb4029SMatthew Auld /** 3331ebcb4029SMatthew Auld * @size: Requested size for the object. 3332ebcb4029SMatthew Auld * 3333ebcb4029SMatthew Auld * The (page-aligned) allocated size for the object will be returned. 3334ebcb4029SMatthew Auld * 3335caa574ffSMatthew Auld * 3336caa574ffSMatthew Auld * DG2 64K min page size implications: 3337caa574ffSMatthew Auld * 3338caa574ffSMatthew Auld * On discrete platforms, starting from DG2, we have to contend with GTT 3339caa574ffSMatthew Auld * page size restrictions when dealing with I915_MEMORY_CLASS_DEVICE 3340caa574ffSMatthew Auld * objects. Specifically the hardware only supports 64K or larger GTT 3341caa574ffSMatthew Auld * page sizes for such memory. The kernel will already ensure that all 3342caa574ffSMatthew Auld * I915_MEMORY_CLASS_DEVICE memory is allocated using 64K or larger page 3343caa574ffSMatthew Auld * sizes underneath. 3344caa574ffSMatthew Auld * 3345caa574ffSMatthew Auld * Note that the returned size here will always reflect any required 3346caa574ffSMatthew Auld * rounding up done by the kernel, i.e 4K will now become 64K on devices 3347caa574ffSMatthew Auld * such as DG2. 3348caa574ffSMatthew Auld * 3349caa574ffSMatthew Auld * Special DG2 GTT address alignment requirement: 3350caa574ffSMatthew Auld * 3351caa574ffSMatthew Auld * The GTT alignment will also need to be at least 2M for such objects. 3352caa574ffSMatthew Auld * 3353caa574ffSMatthew Auld * Note that due to how the hardware implements 64K GTT page support, we 3354caa574ffSMatthew Auld * have some further complications: 3355caa574ffSMatthew Auld * 3356caa574ffSMatthew Auld * 1) The entire PDE (which covers a 2MB virtual address range), must 3357caa574ffSMatthew Auld * contain only 64K PTEs, i.e mixing 4K and 64K PTEs in the same 3358caa574ffSMatthew Auld * PDE is forbidden by the hardware. 3359caa574ffSMatthew Auld * 3360caa574ffSMatthew Auld * 2) We still need to support 4K PTEs for I915_MEMORY_CLASS_SYSTEM 3361caa574ffSMatthew Auld * objects. 3362caa574ffSMatthew Auld * 3363caa574ffSMatthew Auld * To keep things simple for userland, we mandate that any GTT mappings 3364caa574ffSMatthew Auld * must be aligned to and rounded up to 2MB. The kernel will internally 3365caa574ffSMatthew Auld * pad them out to the next 2MB boundary. As this only wastes virtual 3366caa574ffSMatthew Auld * address space and avoids userland having to copy any needlessly 3367caa574ffSMatthew Auld * complicated PDE sharing scheme (coloring) and only affects DG2, this 3368caa574ffSMatthew Auld * is deemed to be a good compromise. 3369ebcb4029SMatthew Auld */ 3370ebcb4029SMatthew Auld __u64 size; 3371ebcb4029SMatthew Auld /** 3372ebcb4029SMatthew Auld * @handle: Returned handle for the object. 3373ebcb4029SMatthew Auld * 3374ebcb4029SMatthew Auld * Object handles are nonzero. 3375ebcb4029SMatthew Auld */ 3376ebcb4029SMatthew Auld __u32 handle; 3377ebcb4029SMatthew Auld /** @flags: MBZ */ 3378ebcb4029SMatthew Auld __u32 flags; 3379ebcb4029SMatthew Auld /** 3380ebcb4029SMatthew Auld * @extensions: The chain of extensions to apply to this object. 3381ebcb4029SMatthew Auld * 3382ebcb4029SMatthew Auld * This will be useful in the future when we need to support several 3383ebcb4029SMatthew Auld * different extensions, and we need to apply more than one when 3384ebcb4029SMatthew Auld * creating the object. See struct i915_user_extension. 3385ebcb4029SMatthew Auld * 3386ebcb4029SMatthew Auld * If we don't supply any extensions then we get the same old gem_create 3387ebcb4029SMatthew Auld * behaviour. 3388ebcb4029SMatthew Auld * 33892459e56fSMatthew Auld * For I915_GEM_CREATE_EXT_MEMORY_REGIONS usage see 33902459e56fSMatthew Auld * struct drm_i915_gem_create_ext_memory_regions. 3391d3ac8d42SDaniele Ceraolo Spurio * 3392d3ac8d42SDaniele Ceraolo Spurio * For I915_GEM_CREATE_EXT_PROTECTED_CONTENT usage see 3393d3ac8d42SDaniele Ceraolo Spurio * struct drm_i915_gem_create_ext_protected_content. 3394ebcb4029SMatthew Auld */ 33952459e56fSMatthew Auld #define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0 3396d3ac8d42SDaniele Ceraolo Spurio #define I915_GEM_CREATE_EXT_PROTECTED_CONTENT 1 3397ebcb4029SMatthew Auld __u64 extensions; 3398ebcb4029SMatthew Auld }; 3399ebcb4029SMatthew Auld 34002459e56fSMatthew Auld /** 34012459e56fSMatthew Auld * struct drm_i915_gem_create_ext_memory_regions - The 34022459e56fSMatthew Auld * I915_GEM_CREATE_EXT_MEMORY_REGIONS extension. 34032459e56fSMatthew Auld * 34042459e56fSMatthew Auld * Set the object with the desired set of placements/regions in priority 34052459e56fSMatthew Auld * order. Each entry must be unique and supported by the device. 34062459e56fSMatthew Auld * 34072459e56fSMatthew Auld * This is provided as an array of struct drm_i915_gem_memory_class_instance, or 34082459e56fSMatthew Auld * an equivalent layout of class:instance pair encodings. See struct 34092459e56fSMatthew Auld * drm_i915_query_memory_regions and DRM_I915_QUERY_MEMORY_REGIONS for how to 34102459e56fSMatthew Auld * query the supported regions for a device. 34112459e56fSMatthew Auld * 34122459e56fSMatthew Auld * As an example, on discrete devices, if we wish to set the placement as 34132459e56fSMatthew Auld * device local-memory we can do something like: 34142459e56fSMatthew Auld * 34152459e56fSMatthew Auld * .. code-block:: C 34162459e56fSMatthew Auld * 34172459e56fSMatthew Auld * struct drm_i915_gem_memory_class_instance region_lmem = { 34182459e56fSMatthew Auld * .memory_class = I915_MEMORY_CLASS_DEVICE, 34192459e56fSMatthew Auld * .memory_instance = 0, 34202459e56fSMatthew Auld * }; 34212459e56fSMatthew Auld * struct drm_i915_gem_create_ext_memory_regions regions = { 34222459e56fSMatthew Auld * .base = { .name = I915_GEM_CREATE_EXT_MEMORY_REGIONS }, 34232459e56fSMatthew Auld * .regions = (uintptr_t)®ion_lmem, 34242459e56fSMatthew Auld * .num_regions = 1, 34252459e56fSMatthew Auld * }; 34262459e56fSMatthew Auld * struct drm_i915_gem_create_ext create_ext = { 34272459e56fSMatthew Auld * .size = 16 * PAGE_SIZE, 34282459e56fSMatthew Auld * .extensions = (uintptr_t)®ions, 34292459e56fSMatthew Auld * }; 34302459e56fSMatthew Auld * 34312459e56fSMatthew Auld * int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext); 34322459e56fSMatthew Auld * if (err) ... 34332459e56fSMatthew Auld * 34342459e56fSMatthew Auld * At which point we get the object handle in &drm_i915_gem_create_ext.handle, 34352459e56fSMatthew Auld * along with the final object size in &drm_i915_gem_create_ext.size, which 34362459e56fSMatthew Auld * should account for any rounding up, if required. 34372459e56fSMatthew Auld */ 34382459e56fSMatthew Auld struct drm_i915_gem_create_ext_memory_regions { 34392459e56fSMatthew Auld /** @base: Extension link. See struct i915_user_extension. */ 34402459e56fSMatthew Auld struct i915_user_extension base; 34412459e56fSMatthew Auld 34422459e56fSMatthew Auld /** @pad: MBZ */ 34432459e56fSMatthew Auld __u32 pad; 34442459e56fSMatthew Auld /** @num_regions: Number of elements in the @regions array. */ 34452459e56fSMatthew Auld __u32 num_regions; 34462459e56fSMatthew Auld /** 34472459e56fSMatthew Auld * @regions: The regions/placements array. 34482459e56fSMatthew Auld * 34492459e56fSMatthew Auld * An array of struct drm_i915_gem_memory_class_instance. 34502459e56fSMatthew Auld */ 34512459e56fSMatthew Auld __u64 regions; 34522459e56fSMatthew Auld }; 34532459e56fSMatthew Auld 3454d3ac8d42SDaniele Ceraolo Spurio /** 3455d3ac8d42SDaniele Ceraolo Spurio * struct drm_i915_gem_create_ext_protected_content - The 3456d3ac8d42SDaniele Ceraolo Spurio * I915_OBJECT_PARAM_PROTECTED_CONTENT extension. 3457d3ac8d42SDaniele Ceraolo Spurio * 3458d3ac8d42SDaniele Ceraolo Spurio * If this extension is provided, buffer contents are expected to be protected 3459d3ac8d42SDaniele Ceraolo Spurio * by PXP encryption and require decryption for scan out and processing. This 3460d3ac8d42SDaniele Ceraolo Spurio * is only possible on platforms that have PXP enabled, on all other scenarios 3461d3ac8d42SDaniele Ceraolo Spurio * using this extension will cause the ioctl to fail and return -ENODEV. The 3462d3ac8d42SDaniele Ceraolo Spurio * flags parameter is reserved for future expansion and must currently be set 3463d3ac8d42SDaniele Ceraolo Spurio * to zero. 3464d3ac8d42SDaniele Ceraolo Spurio * 3465d3ac8d42SDaniele Ceraolo Spurio * The buffer contents are considered invalid after a PXP session teardown. 3466d3ac8d42SDaniele Ceraolo Spurio * 3467d3ac8d42SDaniele Ceraolo Spurio * The encryption is guaranteed to be processed correctly only if the object 3468d3ac8d42SDaniele Ceraolo Spurio * is submitted with a context created using the 3469d3ac8d42SDaniele Ceraolo Spurio * I915_CONTEXT_PARAM_PROTECTED_CONTENT flag. This will also enable extra checks 3470d3ac8d42SDaniele Ceraolo Spurio * at submission time on the validity of the objects involved. 3471d3ac8d42SDaniele Ceraolo Spurio * 3472d3ac8d42SDaniele Ceraolo Spurio * Below is an example on how to create a protected object: 3473d3ac8d42SDaniele Ceraolo Spurio * 3474d3ac8d42SDaniele Ceraolo Spurio * .. code-block:: C 3475d3ac8d42SDaniele Ceraolo Spurio * 3476d3ac8d42SDaniele Ceraolo Spurio * struct drm_i915_gem_create_ext_protected_content protected_ext = { 3477d3ac8d42SDaniele Ceraolo Spurio * .base = { .name = I915_GEM_CREATE_EXT_PROTECTED_CONTENT }, 3478d3ac8d42SDaniele Ceraolo Spurio * .flags = 0, 3479d3ac8d42SDaniele Ceraolo Spurio * }; 3480d3ac8d42SDaniele Ceraolo Spurio * struct drm_i915_gem_create_ext create_ext = { 3481d3ac8d42SDaniele Ceraolo Spurio * .size = PAGE_SIZE, 3482d3ac8d42SDaniele Ceraolo Spurio * .extensions = (uintptr_t)&protected_ext, 3483d3ac8d42SDaniele Ceraolo Spurio * }; 3484d3ac8d42SDaniele Ceraolo Spurio * 3485d3ac8d42SDaniele Ceraolo Spurio * int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext); 3486d3ac8d42SDaniele Ceraolo Spurio * if (err) ... 3487d3ac8d42SDaniele Ceraolo Spurio */ 3488d3ac8d42SDaniele Ceraolo Spurio struct drm_i915_gem_create_ext_protected_content { 3489d3ac8d42SDaniele Ceraolo Spurio /** @base: Extension link. See struct i915_user_extension. */ 3490d3ac8d42SDaniele Ceraolo Spurio struct i915_user_extension base; 3491d3ac8d42SDaniele Ceraolo Spurio /** @flags: reserved for future usage, currently MBZ */ 3492d3ac8d42SDaniele Ceraolo Spurio __u32 flags; 3493d3ac8d42SDaniele Ceraolo Spurio }; 3494d3ac8d42SDaniele Ceraolo Spurio 3495cbbd3764SHuang, Sean Z /* ID of the protected content session managed by i915 when PXP is active */ 3496cbbd3764SHuang, Sean Z #define I915_PROTECTED_CONTENT_DEFAULT_SESSION 0xf 3497cbbd3764SHuang, Sean Z 3498b1c1f5c4SEmil Velikov #if defined(__cplusplus) 3499b1c1f5c4SEmil Velikov } 3500b1c1f5c4SEmil Velikov #endif 3501b1c1f5c4SEmil Velikov 3502718dceddSDavid Howells #endif /* _UAPI_I915_DRM_H_ */ 3503