1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note 2 * 3 * Copyright 2016-2022 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 #ifndef HABANALABS_H_ 9 #define HABANALABS_H_ 10 11 #include <linux/types.h> 12 #include <linux/ioctl.h> 13 14 /* 15 * Defines that are asic-specific but constitutes as ABI between kernel driver 16 * and userspace 17 */ 18 #define GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START 0x8000 /* 32KB */ 19 #define GAUDI_DRIVER_SRAM_RESERVED_SIZE_FROM_START 0x80 /* 128 bytes */ 20 21 /* 22 * 128 SOBs reserved for collective wait 23 * 16 SOBs reserved for sync stream 24 */ 25 #define GAUDI_FIRST_AVAILABLE_W_S_SYNC_OBJECT 144 26 27 /* 28 * 64 monitors reserved for collective wait 29 * 8 monitors reserved for sync stream 30 */ 31 #define GAUDI_FIRST_AVAILABLE_W_S_MONITOR 72 32 33 /* Max number of elements in timestamps registration buffers */ 34 #define TS_MAX_ELEMENTS_NUM (1 << 20) /* 1MB */ 35 36 /* 37 * Goya queue Numbering 38 * 39 * The external queues (PCI DMA channels) MUST be before the internal queues 40 * and each group (PCI DMA channels and internal) must be contiguous inside 41 * itself but there can be a gap between the two groups (although not 42 * recommended) 43 */ 44 45 enum goya_queue_id { 46 GOYA_QUEUE_ID_DMA_0 = 0, 47 GOYA_QUEUE_ID_DMA_1 = 1, 48 GOYA_QUEUE_ID_DMA_2 = 2, 49 GOYA_QUEUE_ID_DMA_3 = 3, 50 GOYA_QUEUE_ID_DMA_4 = 4, 51 GOYA_QUEUE_ID_CPU_PQ = 5, 52 GOYA_QUEUE_ID_MME = 6, /* Internal queues start here */ 53 GOYA_QUEUE_ID_TPC0 = 7, 54 GOYA_QUEUE_ID_TPC1 = 8, 55 GOYA_QUEUE_ID_TPC2 = 9, 56 GOYA_QUEUE_ID_TPC3 = 10, 57 GOYA_QUEUE_ID_TPC4 = 11, 58 GOYA_QUEUE_ID_TPC5 = 12, 59 GOYA_QUEUE_ID_TPC6 = 13, 60 GOYA_QUEUE_ID_TPC7 = 14, 61 GOYA_QUEUE_ID_SIZE 62 }; 63 64 /* 65 * Gaudi queue Numbering 66 * External queues (PCI DMA channels) are DMA_0_*, DMA_1_* and DMA_5_*. 67 * Except one CPU queue, all the rest are internal queues. 68 */ 69 70 enum gaudi_queue_id { 71 GAUDI_QUEUE_ID_DMA_0_0 = 0, /* external */ 72 GAUDI_QUEUE_ID_DMA_0_1 = 1, /* external */ 73 GAUDI_QUEUE_ID_DMA_0_2 = 2, /* external */ 74 GAUDI_QUEUE_ID_DMA_0_3 = 3, /* external */ 75 GAUDI_QUEUE_ID_DMA_1_0 = 4, /* external */ 76 GAUDI_QUEUE_ID_DMA_1_1 = 5, /* external */ 77 GAUDI_QUEUE_ID_DMA_1_2 = 6, /* external */ 78 GAUDI_QUEUE_ID_DMA_1_3 = 7, /* external */ 79 GAUDI_QUEUE_ID_CPU_PQ = 8, /* CPU */ 80 GAUDI_QUEUE_ID_DMA_2_0 = 9, /* internal */ 81 GAUDI_QUEUE_ID_DMA_2_1 = 10, /* internal */ 82 GAUDI_QUEUE_ID_DMA_2_2 = 11, /* internal */ 83 GAUDI_QUEUE_ID_DMA_2_3 = 12, /* internal */ 84 GAUDI_QUEUE_ID_DMA_3_0 = 13, /* internal */ 85 GAUDI_QUEUE_ID_DMA_3_1 = 14, /* internal */ 86 GAUDI_QUEUE_ID_DMA_3_2 = 15, /* internal */ 87 GAUDI_QUEUE_ID_DMA_3_3 = 16, /* internal */ 88 GAUDI_QUEUE_ID_DMA_4_0 = 17, /* internal */ 89 GAUDI_QUEUE_ID_DMA_4_1 = 18, /* internal */ 90 GAUDI_QUEUE_ID_DMA_4_2 = 19, /* internal */ 91 GAUDI_QUEUE_ID_DMA_4_3 = 20, /* internal */ 92 GAUDI_QUEUE_ID_DMA_5_0 = 21, /* internal */ 93 GAUDI_QUEUE_ID_DMA_5_1 = 22, /* internal */ 94 GAUDI_QUEUE_ID_DMA_5_2 = 23, /* internal */ 95 GAUDI_QUEUE_ID_DMA_5_3 = 24, /* internal */ 96 GAUDI_QUEUE_ID_DMA_6_0 = 25, /* internal */ 97 GAUDI_QUEUE_ID_DMA_6_1 = 26, /* internal */ 98 GAUDI_QUEUE_ID_DMA_6_2 = 27, /* internal */ 99 GAUDI_QUEUE_ID_DMA_6_3 = 28, /* internal */ 100 GAUDI_QUEUE_ID_DMA_7_0 = 29, /* internal */ 101 GAUDI_QUEUE_ID_DMA_7_1 = 30, /* internal */ 102 GAUDI_QUEUE_ID_DMA_7_2 = 31, /* internal */ 103 GAUDI_QUEUE_ID_DMA_7_3 = 32, /* internal */ 104 GAUDI_QUEUE_ID_MME_0_0 = 33, /* internal */ 105 GAUDI_QUEUE_ID_MME_0_1 = 34, /* internal */ 106 GAUDI_QUEUE_ID_MME_0_2 = 35, /* internal */ 107 GAUDI_QUEUE_ID_MME_0_3 = 36, /* internal */ 108 GAUDI_QUEUE_ID_MME_1_0 = 37, /* internal */ 109 GAUDI_QUEUE_ID_MME_1_1 = 38, /* internal */ 110 GAUDI_QUEUE_ID_MME_1_2 = 39, /* internal */ 111 GAUDI_QUEUE_ID_MME_1_3 = 40, /* internal */ 112 GAUDI_QUEUE_ID_TPC_0_0 = 41, /* internal */ 113 GAUDI_QUEUE_ID_TPC_0_1 = 42, /* internal */ 114 GAUDI_QUEUE_ID_TPC_0_2 = 43, /* internal */ 115 GAUDI_QUEUE_ID_TPC_0_3 = 44, /* internal */ 116 GAUDI_QUEUE_ID_TPC_1_0 = 45, /* internal */ 117 GAUDI_QUEUE_ID_TPC_1_1 = 46, /* internal */ 118 GAUDI_QUEUE_ID_TPC_1_2 = 47, /* internal */ 119 GAUDI_QUEUE_ID_TPC_1_3 = 48, /* internal */ 120 GAUDI_QUEUE_ID_TPC_2_0 = 49, /* internal */ 121 GAUDI_QUEUE_ID_TPC_2_1 = 50, /* internal */ 122 GAUDI_QUEUE_ID_TPC_2_2 = 51, /* internal */ 123 GAUDI_QUEUE_ID_TPC_2_3 = 52, /* internal */ 124 GAUDI_QUEUE_ID_TPC_3_0 = 53, /* internal */ 125 GAUDI_QUEUE_ID_TPC_3_1 = 54, /* internal */ 126 GAUDI_QUEUE_ID_TPC_3_2 = 55, /* internal */ 127 GAUDI_QUEUE_ID_TPC_3_3 = 56, /* internal */ 128 GAUDI_QUEUE_ID_TPC_4_0 = 57, /* internal */ 129 GAUDI_QUEUE_ID_TPC_4_1 = 58, /* internal */ 130 GAUDI_QUEUE_ID_TPC_4_2 = 59, /* internal */ 131 GAUDI_QUEUE_ID_TPC_4_3 = 60, /* internal */ 132 GAUDI_QUEUE_ID_TPC_5_0 = 61, /* internal */ 133 GAUDI_QUEUE_ID_TPC_5_1 = 62, /* internal */ 134 GAUDI_QUEUE_ID_TPC_5_2 = 63, /* internal */ 135 GAUDI_QUEUE_ID_TPC_5_3 = 64, /* internal */ 136 GAUDI_QUEUE_ID_TPC_6_0 = 65, /* internal */ 137 GAUDI_QUEUE_ID_TPC_6_1 = 66, /* internal */ 138 GAUDI_QUEUE_ID_TPC_6_2 = 67, /* internal */ 139 GAUDI_QUEUE_ID_TPC_6_3 = 68, /* internal */ 140 GAUDI_QUEUE_ID_TPC_7_0 = 69, /* internal */ 141 GAUDI_QUEUE_ID_TPC_7_1 = 70, /* internal */ 142 GAUDI_QUEUE_ID_TPC_7_2 = 71, /* internal */ 143 GAUDI_QUEUE_ID_TPC_7_3 = 72, /* internal */ 144 GAUDI_QUEUE_ID_NIC_0_0 = 73, /* internal */ 145 GAUDI_QUEUE_ID_NIC_0_1 = 74, /* internal */ 146 GAUDI_QUEUE_ID_NIC_0_2 = 75, /* internal */ 147 GAUDI_QUEUE_ID_NIC_0_3 = 76, /* internal */ 148 GAUDI_QUEUE_ID_NIC_1_0 = 77, /* internal */ 149 GAUDI_QUEUE_ID_NIC_1_1 = 78, /* internal */ 150 GAUDI_QUEUE_ID_NIC_1_2 = 79, /* internal */ 151 GAUDI_QUEUE_ID_NIC_1_3 = 80, /* internal */ 152 GAUDI_QUEUE_ID_NIC_2_0 = 81, /* internal */ 153 GAUDI_QUEUE_ID_NIC_2_1 = 82, /* internal */ 154 GAUDI_QUEUE_ID_NIC_2_2 = 83, /* internal */ 155 GAUDI_QUEUE_ID_NIC_2_3 = 84, /* internal */ 156 GAUDI_QUEUE_ID_NIC_3_0 = 85, /* internal */ 157 GAUDI_QUEUE_ID_NIC_3_1 = 86, /* internal */ 158 GAUDI_QUEUE_ID_NIC_3_2 = 87, /* internal */ 159 GAUDI_QUEUE_ID_NIC_3_3 = 88, /* internal */ 160 GAUDI_QUEUE_ID_NIC_4_0 = 89, /* internal */ 161 GAUDI_QUEUE_ID_NIC_4_1 = 90, /* internal */ 162 GAUDI_QUEUE_ID_NIC_4_2 = 91, /* internal */ 163 GAUDI_QUEUE_ID_NIC_4_3 = 92, /* internal */ 164 GAUDI_QUEUE_ID_NIC_5_0 = 93, /* internal */ 165 GAUDI_QUEUE_ID_NIC_5_1 = 94, /* internal */ 166 GAUDI_QUEUE_ID_NIC_5_2 = 95, /* internal */ 167 GAUDI_QUEUE_ID_NIC_5_3 = 96, /* internal */ 168 GAUDI_QUEUE_ID_NIC_6_0 = 97, /* internal */ 169 GAUDI_QUEUE_ID_NIC_6_1 = 98, /* internal */ 170 GAUDI_QUEUE_ID_NIC_6_2 = 99, /* internal */ 171 GAUDI_QUEUE_ID_NIC_6_3 = 100, /* internal */ 172 GAUDI_QUEUE_ID_NIC_7_0 = 101, /* internal */ 173 GAUDI_QUEUE_ID_NIC_7_1 = 102, /* internal */ 174 GAUDI_QUEUE_ID_NIC_7_2 = 103, /* internal */ 175 GAUDI_QUEUE_ID_NIC_7_3 = 104, /* internal */ 176 GAUDI_QUEUE_ID_NIC_8_0 = 105, /* internal */ 177 GAUDI_QUEUE_ID_NIC_8_1 = 106, /* internal */ 178 GAUDI_QUEUE_ID_NIC_8_2 = 107, /* internal */ 179 GAUDI_QUEUE_ID_NIC_8_3 = 108, /* internal */ 180 GAUDI_QUEUE_ID_NIC_9_0 = 109, /* internal */ 181 GAUDI_QUEUE_ID_NIC_9_1 = 110, /* internal */ 182 GAUDI_QUEUE_ID_NIC_9_2 = 111, /* internal */ 183 GAUDI_QUEUE_ID_NIC_9_3 = 112, /* internal */ 184 GAUDI_QUEUE_ID_SIZE 185 }; 186 187 /* 188 * In GAUDI2 we have two modes of operation in regard to queues: 189 * 1. Legacy mode, where each QMAN exposes 4 streams to the user 190 * 2. F/W mode, where we use F/W to schedule the JOBS to the different queues. 191 * 192 * When in legacy mode, the user sends the queue id per JOB according to 193 * enum gaudi2_queue_id below. 194 * 195 * When in F/W mode, the user sends a stream id per Command Submission. The 196 * stream id is a running number from 0 up to (N-1), where N is the number 197 * of streams the F/W exposes and is passed to the user in 198 * struct hl_info_hw_ip_info 199 */ 200 201 enum gaudi2_queue_id { 202 GAUDI2_QUEUE_ID_PDMA_0_0 = 0, 203 GAUDI2_QUEUE_ID_PDMA_0_1 = 1, 204 GAUDI2_QUEUE_ID_PDMA_0_2 = 2, 205 GAUDI2_QUEUE_ID_PDMA_0_3 = 3, 206 GAUDI2_QUEUE_ID_PDMA_1_0 = 4, 207 GAUDI2_QUEUE_ID_PDMA_1_1 = 5, 208 GAUDI2_QUEUE_ID_PDMA_1_2 = 6, 209 GAUDI2_QUEUE_ID_PDMA_1_3 = 7, 210 GAUDI2_QUEUE_ID_DCORE0_EDMA_0_0 = 8, 211 GAUDI2_QUEUE_ID_DCORE0_EDMA_0_1 = 9, 212 GAUDI2_QUEUE_ID_DCORE0_EDMA_0_2 = 10, 213 GAUDI2_QUEUE_ID_DCORE0_EDMA_0_3 = 11, 214 GAUDI2_QUEUE_ID_DCORE0_EDMA_1_0 = 12, 215 GAUDI2_QUEUE_ID_DCORE0_EDMA_1_1 = 13, 216 GAUDI2_QUEUE_ID_DCORE0_EDMA_1_2 = 14, 217 GAUDI2_QUEUE_ID_DCORE0_EDMA_1_3 = 15, 218 GAUDI2_QUEUE_ID_DCORE0_MME_0_0 = 16, 219 GAUDI2_QUEUE_ID_DCORE0_MME_0_1 = 17, 220 GAUDI2_QUEUE_ID_DCORE0_MME_0_2 = 18, 221 GAUDI2_QUEUE_ID_DCORE0_MME_0_3 = 19, 222 GAUDI2_QUEUE_ID_DCORE0_TPC_0_0 = 20, 223 GAUDI2_QUEUE_ID_DCORE0_TPC_0_1 = 21, 224 GAUDI2_QUEUE_ID_DCORE0_TPC_0_2 = 22, 225 GAUDI2_QUEUE_ID_DCORE0_TPC_0_3 = 23, 226 GAUDI2_QUEUE_ID_DCORE0_TPC_1_0 = 24, 227 GAUDI2_QUEUE_ID_DCORE0_TPC_1_1 = 25, 228 GAUDI2_QUEUE_ID_DCORE0_TPC_1_2 = 26, 229 GAUDI2_QUEUE_ID_DCORE0_TPC_1_3 = 27, 230 GAUDI2_QUEUE_ID_DCORE0_TPC_2_0 = 28, 231 GAUDI2_QUEUE_ID_DCORE0_TPC_2_1 = 29, 232 GAUDI2_QUEUE_ID_DCORE0_TPC_2_2 = 30, 233 GAUDI2_QUEUE_ID_DCORE0_TPC_2_3 = 31, 234 GAUDI2_QUEUE_ID_DCORE0_TPC_3_0 = 32, 235 GAUDI2_QUEUE_ID_DCORE0_TPC_3_1 = 33, 236 GAUDI2_QUEUE_ID_DCORE0_TPC_3_2 = 34, 237 GAUDI2_QUEUE_ID_DCORE0_TPC_3_3 = 35, 238 GAUDI2_QUEUE_ID_DCORE0_TPC_4_0 = 36, 239 GAUDI2_QUEUE_ID_DCORE0_TPC_4_1 = 37, 240 GAUDI2_QUEUE_ID_DCORE0_TPC_4_2 = 38, 241 GAUDI2_QUEUE_ID_DCORE0_TPC_4_3 = 39, 242 GAUDI2_QUEUE_ID_DCORE0_TPC_5_0 = 40, 243 GAUDI2_QUEUE_ID_DCORE0_TPC_5_1 = 41, 244 GAUDI2_QUEUE_ID_DCORE0_TPC_5_2 = 42, 245 GAUDI2_QUEUE_ID_DCORE0_TPC_5_3 = 43, 246 GAUDI2_QUEUE_ID_DCORE0_TPC_6_0 = 44, 247 GAUDI2_QUEUE_ID_DCORE0_TPC_6_1 = 45, 248 GAUDI2_QUEUE_ID_DCORE0_TPC_6_2 = 46, 249 GAUDI2_QUEUE_ID_DCORE0_TPC_6_3 = 47, 250 GAUDI2_QUEUE_ID_DCORE1_EDMA_0_0 = 48, 251 GAUDI2_QUEUE_ID_DCORE1_EDMA_0_1 = 49, 252 GAUDI2_QUEUE_ID_DCORE1_EDMA_0_2 = 50, 253 GAUDI2_QUEUE_ID_DCORE1_EDMA_0_3 = 51, 254 GAUDI2_QUEUE_ID_DCORE1_EDMA_1_0 = 52, 255 GAUDI2_QUEUE_ID_DCORE1_EDMA_1_1 = 53, 256 GAUDI2_QUEUE_ID_DCORE1_EDMA_1_2 = 54, 257 GAUDI2_QUEUE_ID_DCORE1_EDMA_1_3 = 55, 258 GAUDI2_QUEUE_ID_DCORE1_MME_0_0 = 56, 259 GAUDI2_QUEUE_ID_DCORE1_MME_0_1 = 57, 260 GAUDI2_QUEUE_ID_DCORE1_MME_0_2 = 58, 261 GAUDI2_QUEUE_ID_DCORE1_MME_0_3 = 59, 262 GAUDI2_QUEUE_ID_DCORE1_TPC_0_0 = 60, 263 GAUDI2_QUEUE_ID_DCORE1_TPC_0_1 = 61, 264 GAUDI2_QUEUE_ID_DCORE1_TPC_0_2 = 62, 265 GAUDI2_QUEUE_ID_DCORE1_TPC_0_3 = 63, 266 GAUDI2_QUEUE_ID_DCORE1_TPC_1_0 = 64, 267 GAUDI2_QUEUE_ID_DCORE1_TPC_1_1 = 65, 268 GAUDI2_QUEUE_ID_DCORE1_TPC_1_2 = 66, 269 GAUDI2_QUEUE_ID_DCORE1_TPC_1_3 = 67, 270 GAUDI2_QUEUE_ID_DCORE1_TPC_2_0 = 68, 271 GAUDI2_QUEUE_ID_DCORE1_TPC_2_1 = 69, 272 GAUDI2_QUEUE_ID_DCORE1_TPC_2_2 = 70, 273 GAUDI2_QUEUE_ID_DCORE1_TPC_2_3 = 71, 274 GAUDI2_QUEUE_ID_DCORE1_TPC_3_0 = 72, 275 GAUDI2_QUEUE_ID_DCORE1_TPC_3_1 = 73, 276 GAUDI2_QUEUE_ID_DCORE1_TPC_3_2 = 74, 277 GAUDI2_QUEUE_ID_DCORE1_TPC_3_3 = 75, 278 GAUDI2_QUEUE_ID_DCORE1_TPC_4_0 = 76, 279 GAUDI2_QUEUE_ID_DCORE1_TPC_4_1 = 77, 280 GAUDI2_QUEUE_ID_DCORE1_TPC_4_2 = 78, 281 GAUDI2_QUEUE_ID_DCORE1_TPC_4_3 = 79, 282 GAUDI2_QUEUE_ID_DCORE1_TPC_5_0 = 80, 283 GAUDI2_QUEUE_ID_DCORE1_TPC_5_1 = 81, 284 GAUDI2_QUEUE_ID_DCORE1_TPC_5_2 = 82, 285 GAUDI2_QUEUE_ID_DCORE1_TPC_5_3 = 83, 286 GAUDI2_QUEUE_ID_DCORE2_EDMA_0_0 = 84, 287 GAUDI2_QUEUE_ID_DCORE2_EDMA_0_1 = 85, 288 GAUDI2_QUEUE_ID_DCORE2_EDMA_0_2 = 86, 289 GAUDI2_QUEUE_ID_DCORE2_EDMA_0_3 = 87, 290 GAUDI2_QUEUE_ID_DCORE2_EDMA_1_0 = 88, 291 GAUDI2_QUEUE_ID_DCORE2_EDMA_1_1 = 89, 292 GAUDI2_QUEUE_ID_DCORE2_EDMA_1_2 = 90, 293 GAUDI2_QUEUE_ID_DCORE2_EDMA_1_3 = 91, 294 GAUDI2_QUEUE_ID_DCORE2_MME_0_0 = 92, 295 GAUDI2_QUEUE_ID_DCORE2_MME_0_1 = 93, 296 GAUDI2_QUEUE_ID_DCORE2_MME_0_2 = 94, 297 GAUDI2_QUEUE_ID_DCORE2_MME_0_3 = 95, 298 GAUDI2_QUEUE_ID_DCORE2_TPC_0_0 = 96, 299 GAUDI2_QUEUE_ID_DCORE2_TPC_0_1 = 97, 300 GAUDI2_QUEUE_ID_DCORE2_TPC_0_2 = 98, 301 GAUDI2_QUEUE_ID_DCORE2_TPC_0_3 = 99, 302 GAUDI2_QUEUE_ID_DCORE2_TPC_1_0 = 100, 303 GAUDI2_QUEUE_ID_DCORE2_TPC_1_1 = 101, 304 GAUDI2_QUEUE_ID_DCORE2_TPC_1_2 = 102, 305 GAUDI2_QUEUE_ID_DCORE2_TPC_1_3 = 103, 306 GAUDI2_QUEUE_ID_DCORE2_TPC_2_0 = 104, 307 GAUDI2_QUEUE_ID_DCORE2_TPC_2_1 = 105, 308 GAUDI2_QUEUE_ID_DCORE2_TPC_2_2 = 106, 309 GAUDI2_QUEUE_ID_DCORE2_TPC_2_3 = 107, 310 GAUDI2_QUEUE_ID_DCORE2_TPC_3_0 = 108, 311 GAUDI2_QUEUE_ID_DCORE2_TPC_3_1 = 109, 312 GAUDI2_QUEUE_ID_DCORE2_TPC_3_2 = 110, 313 GAUDI2_QUEUE_ID_DCORE2_TPC_3_3 = 111, 314 GAUDI2_QUEUE_ID_DCORE2_TPC_4_0 = 112, 315 GAUDI2_QUEUE_ID_DCORE2_TPC_4_1 = 113, 316 GAUDI2_QUEUE_ID_DCORE2_TPC_4_2 = 114, 317 GAUDI2_QUEUE_ID_DCORE2_TPC_4_3 = 115, 318 GAUDI2_QUEUE_ID_DCORE2_TPC_5_0 = 116, 319 GAUDI2_QUEUE_ID_DCORE2_TPC_5_1 = 117, 320 GAUDI2_QUEUE_ID_DCORE2_TPC_5_2 = 118, 321 GAUDI2_QUEUE_ID_DCORE2_TPC_5_3 = 119, 322 GAUDI2_QUEUE_ID_DCORE3_EDMA_0_0 = 120, 323 GAUDI2_QUEUE_ID_DCORE3_EDMA_0_1 = 121, 324 GAUDI2_QUEUE_ID_DCORE3_EDMA_0_2 = 122, 325 GAUDI2_QUEUE_ID_DCORE3_EDMA_0_3 = 123, 326 GAUDI2_QUEUE_ID_DCORE3_EDMA_1_0 = 124, 327 GAUDI2_QUEUE_ID_DCORE3_EDMA_1_1 = 125, 328 GAUDI2_QUEUE_ID_DCORE3_EDMA_1_2 = 126, 329 GAUDI2_QUEUE_ID_DCORE3_EDMA_1_3 = 127, 330 GAUDI2_QUEUE_ID_DCORE3_MME_0_0 = 128, 331 GAUDI2_QUEUE_ID_DCORE3_MME_0_1 = 129, 332 GAUDI2_QUEUE_ID_DCORE3_MME_0_2 = 130, 333 GAUDI2_QUEUE_ID_DCORE3_MME_0_3 = 131, 334 GAUDI2_QUEUE_ID_DCORE3_TPC_0_0 = 132, 335 GAUDI2_QUEUE_ID_DCORE3_TPC_0_1 = 133, 336 GAUDI2_QUEUE_ID_DCORE3_TPC_0_2 = 134, 337 GAUDI2_QUEUE_ID_DCORE3_TPC_0_3 = 135, 338 GAUDI2_QUEUE_ID_DCORE3_TPC_1_0 = 136, 339 GAUDI2_QUEUE_ID_DCORE3_TPC_1_1 = 137, 340 GAUDI2_QUEUE_ID_DCORE3_TPC_1_2 = 138, 341 GAUDI2_QUEUE_ID_DCORE3_TPC_1_3 = 139, 342 GAUDI2_QUEUE_ID_DCORE3_TPC_2_0 = 140, 343 GAUDI2_QUEUE_ID_DCORE3_TPC_2_1 = 141, 344 GAUDI2_QUEUE_ID_DCORE3_TPC_2_2 = 142, 345 GAUDI2_QUEUE_ID_DCORE3_TPC_2_3 = 143, 346 GAUDI2_QUEUE_ID_DCORE3_TPC_3_0 = 144, 347 GAUDI2_QUEUE_ID_DCORE3_TPC_3_1 = 145, 348 GAUDI2_QUEUE_ID_DCORE3_TPC_3_2 = 146, 349 GAUDI2_QUEUE_ID_DCORE3_TPC_3_3 = 147, 350 GAUDI2_QUEUE_ID_DCORE3_TPC_4_0 = 148, 351 GAUDI2_QUEUE_ID_DCORE3_TPC_4_1 = 149, 352 GAUDI2_QUEUE_ID_DCORE3_TPC_4_2 = 150, 353 GAUDI2_QUEUE_ID_DCORE3_TPC_4_3 = 151, 354 GAUDI2_QUEUE_ID_DCORE3_TPC_5_0 = 152, 355 GAUDI2_QUEUE_ID_DCORE3_TPC_5_1 = 153, 356 GAUDI2_QUEUE_ID_DCORE3_TPC_5_2 = 154, 357 GAUDI2_QUEUE_ID_DCORE3_TPC_5_3 = 155, 358 GAUDI2_QUEUE_ID_NIC_0_0 = 156, 359 GAUDI2_QUEUE_ID_NIC_0_1 = 157, 360 GAUDI2_QUEUE_ID_NIC_0_2 = 158, 361 GAUDI2_QUEUE_ID_NIC_0_3 = 159, 362 GAUDI2_QUEUE_ID_NIC_1_0 = 160, 363 GAUDI2_QUEUE_ID_NIC_1_1 = 161, 364 GAUDI2_QUEUE_ID_NIC_1_2 = 162, 365 GAUDI2_QUEUE_ID_NIC_1_3 = 163, 366 GAUDI2_QUEUE_ID_NIC_2_0 = 164, 367 GAUDI2_QUEUE_ID_NIC_2_1 = 165, 368 GAUDI2_QUEUE_ID_NIC_2_2 = 166, 369 GAUDI2_QUEUE_ID_NIC_2_3 = 167, 370 GAUDI2_QUEUE_ID_NIC_3_0 = 168, 371 GAUDI2_QUEUE_ID_NIC_3_1 = 169, 372 GAUDI2_QUEUE_ID_NIC_3_2 = 170, 373 GAUDI2_QUEUE_ID_NIC_3_3 = 171, 374 GAUDI2_QUEUE_ID_NIC_4_0 = 172, 375 GAUDI2_QUEUE_ID_NIC_4_1 = 173, 376 GAUDI2_QUEUE_ID_NIC_4_2 = 174, 377 GAUDI2_QUEUE_ID_NIC_4_3 = 175, 378 GAUDI2_QUEUE_ID_NIC_5_0 = 176, 379 GAUDI2_QUEUE_ID_NIC_5_1 = 177, 380 GAUDI2_QUEUE_ID_NIC_5_2 = 178, 381 GAUDI2_QUEUE_ID_NIC_5_3 = 179, 382 GAUDI2_QUEUE_ID_NIC_6_0 = 180, 383 GAUDI2_QUEUE_ID_NIC_6_1 = 181, 384 GAUDI2_QUEUE_ID_NIC_6_2 = 182, 385 GAUDI2_QUEUE_ID_NIC_6_3 = 183, 386 GAUDI2_QUEUE_ID_NIC_7_0 = 184, 387 GAUDI2_QUEUE_ID_NIC_7_1 = 185, 388 GAUDI2_QUEUE_ID_NIC_7_2 = 186, 389 GAUDI2_QUEUE_ID_NIC_7_3 = 187, 390 GAUDI2_QUEUE_ID_NIC_8_0 = 188, 391 GAUDI2_QUEUE_ID_NIC_8_1 = 189, 392 GAUDI2_QUEUE_ID_NIC_8_2 = 190, 393 GAUDI2_QUEUE_ID_NIC_8_3 = 191, 394 GAUDI2_QUEUE_ID_NIC_9_0 = 192, 395 GAUDI2_QUEUE_ID_NIC_9_1 = 193, 396 GAUDI2_QUEUE_ID_NIC_9_2 = 194, 397 GAUDI2_QUEUE_ID_NIC_9_3 = 195, 398 GAUDI2_QUEUE_ID_NIC_10_0 = 196, 399 GAUDI2_QUEUE_ID_NIC_10_1 = 197, 400 GAUDI2_QUEUE_ID_NIC_10_2 = 198, 401 GAUDI2_QUEUE_ID_NIC_10_3 = 199, 402 GAUDI2_QUEUE_ID_NIC_11_0 = 200, 403 GAUDI2_QUEUE_ID_NIC_11_1 = 201, 404 GAUDI2_QUEUE_ID_NIC_11_2 = 202, 405 GAUDI2_QUEUE_ID_NIC_11_3 = 203, 406 GAUDI2_QUEUE_ID_NIC_12_0 = 204, 407 GAUDI2_QUEUE_ID_NIC_12_1 = 205, 408 GAUDI2_QUEUE_ID_NIC_12_2 = 206, 409 GAUDI2_QUEUE_ID_NIC_12_3 = 207, 410 GAUDI2_QUEUE_ID_NIC_13_0 = 208, 411 GAUDI2_QUEUE_ID_NIC_13_1 = 209, 412 GAUDI2_QUEUE_ID_NIC_13_2 = 210, 413 GAUDI2_QUEUE_ID_NIC_13_3 = 211, 414 GAUDI2_QUEUE_ID_NIC_14_0 = 212, 415 GAUDI2_QUEUE_ID_NIC_14_1 = 213, 416 GAUDI2_QUEUE_ID_NIC_14_2 = 214, 417 GAUDI2_QUEUE_ID_NIC_14_3 = 215, 418 GAUDI2_QUEUE_ID_NIC_15_0 = 216, 419 GAUDI2_QUEUE_ID_NIC_15_1 = 217, 420 GAUDI2_QUEUE_ID_NIC_15_2 = 218, 421 GAUDI2_QUEUE_ID_NIC_15_3 = 219, 422 GAUDI2_QUEUE_ID_NIC_16_0 = 220, 423 GAUDI2_QUEUE_ID_NIC_16_1 = 221, 424 GAUDI2_QUEUE_ID_NIC_16_2 = 222, 425 GAUDI2_QUEUE_ID_NIC_16_3 = 223, 426 GAUDI2_QUEUE_ID_NIC_17_0 = 224, 427 GAUDI2_QUEUE_ID_NIC_17_1 = 225, 428 GAUDI2_QUEUE_ID_NIC_17_2 = 226, 429 GAUDI2_QUEUE_ID_NIC_17_3 = 227, 430 GAUDI2_QUEUE_ID_NIC_18_0 = 228, 431 GAUDI2_QUEUE_ID_NIC_18_1 = 229, 432 GAUDI2_QUEUE_ID_NIC_18_2 = 230, 433 GAUDI2_QUEUE_ID_NIC_18_3 = 231, 434 GAUDI2_QUEUE_ID_NIC_19_0 = 232, 435 GAUDI2_QUEUE_ID_NIC_19_1 = 233, 436 GAUDI2_QUEUE_ID_NIC_19_2 = 234, 437 GAUDI2_QUEUE_ID_NIC_19_3 = 235, 438 GAUDI2_QUEUE_ID_NIC_20_0 = 236, 439 GAUDI2_QUEUE_ID_NIC_20_1 = 237, 440 GAUDI2_QUEUE_ID_NIC_20_2 = 238, 441 GAUDI2_QUEUE_ID_NIC_20_3 = 239, 442 GAUDI2_QUEUE_ID_NIC_21_0 = 240, 443 GAUDI2_QUEUE_ID_NIC_21_1 = 241, 444 GAUDI2_QUEUE_ID_NIC_21_2 = 242, 445 GAUDI2_QUEUE_ID_NIC_21_3 = 243, 446 GAUDI2_QUEUE_ID_NIC_22_0 = 244, 447 GAUDI2_QUEUE_ID_NIC_22_1 = 245, 448 GAUDI2_QUEUE_ID_NIC_22_2 = 246, 449 GAUDI2_QUEUE_ID_NIC_22_3 = 247, 450 GAUDI2_QUEUE_ID_NIC_23_0 = 248, 451 GAUDI2_QUEUE_ID_NIC_23_1 = 249, 452 GAUDI2_QUEUE_ID_NIC_23_2 = 250, 453 GAUDI2_QUEUE_ID_NIC_23_3 = 251, 454 GAUDI2_QUEUE_ID_ROT_0_0 = 252, 455 GAUDI2_QUEUE_ID_ROT_0_1 = 253, 456 GAUDI2_QUEUE_ID_ROT_0_2 = 254, 457 GAUDI2_QUEUE_ID_ROT_0_3 = 255, 458 GAUDI2_QUEUE_ID_ROT_1_0 = 256, 459 GAUDI2_QUEUE_ID_ROT_1_1 = 257, 460 GAUDI2_QUEUE_ID_ROT_1_2 = 258, 461 GAUDI2_QUEUE_ID_ROT_1_3 = 259, 462 GAUDI2_QUEUE_ID_CPU_PQ = 260, 463 GAUDI2_QUEUE_ID_SIZE 464 }; 465 466 /* 467 * Engine Numbering 468 * 469 * Used in the "busy_engines_mask" field in `struct hl_info_hw_idle' 470 */ 471 472 enum goya_engine_id { 473 GOYA_ENGINE_ID_DMA_0 = 0, 474 GOYA_ENGINE_ID_DMA_1, 475 GOYA_ENGINE_ID_DMA_2, 476 GOYA_ENGINE_ID_DMA_3, 477 GOYA_ENGINE_ID_DMA_4, 478 GOYA_ENGINE_ID_MME_0, 479 GOYA_ENGINE_ID_TPC_0, 480 GOYA_ENGINE_ID_TPC_1, 481 GOYA_ENGINE_ID_TPC_2, 482 GOYA_ENGINE_ID_TPC_3, 483 GOYA_ENGINE_ID_TPC_4, 484 GOYA_ENGINE_ID_TPC_5, 485 GOYA_ENGINE_ID_TPC_6, 486 GOYA_ENGINE_ID_TPC_7, 487 GOYA_ENGINE_ID_SIZE 488 }; 489 490 enum gaudi_engine_id { 491 GAUDI_ENGINE_ID_DMA_0 = 0, 492 GAUDI_ENGINE_ID_DMA_1, 493 GAUDI_ENGINE_ID_DMA_2, 494 GAUDI_ENGINE_ID_DMA_3, 495 GAUDI_ENGINE_ID_DMA_4, 496 GAUDI_ENGINE_ID_DMA_5, 497 GAUDI_ENGINE_ID_DMA_6, 498 GAUDI_ENGINE_ID_DMA_7, 499 GAUDI_ENGINE_ID_MME_0, 500 GAUDI_ENGINE_ID_MME_1, 501 GAUDI_ENGINE_ID_MME_2, 502 GAUDI_ENGINE_ID_MME_3, 503 GAUDI_ENGINE_ID_TPC_0, 504 GAUDI_ENGINE_ID_TPC_1, 505 GAUDI_ENGINE_ID_TPC_2, 506 GAUDI_ENGINE_ID_TPC_3, 507 GAUDI_ENGINE_ID_TPC_4, 508 GAUDI_ENGINE_ID_TPC_5, 509 GAUDI_ENGINE_ID_TPC_6, 510 GAUDI_ENGINE_ID_TPC_7, 511 GAUDI_ENGINE_ID_NIC_0, 512 GAUDI_ENGINE_ID_NIC_1, 513 GAUDI_ENGINE_ID_NIC_2, 514 GAUDI_ENGINE_ID_NIC_3, 515 GAUDI_ENGINE_ID_NIC_4, 516 GAUDI_ENGINE_ID_NIC_5, 517 GAUDI_ENGINE_ID_NIC_6, 518 GAUDI_ENGINE_ID_NIC_7, 519 GAUDI_ENGINE_ID_NIC_8, 520 GAUDI_ENGINE_ID_NIC_9, 521 GAUDI_ENGINE_ID_SIZE 522 }; 523 524 enum gaudi2_engine_id { 525 GAUDI2_DCORE0_ENGINE_ID_EDMA_0 = 0, 526 GAUDI2_DCORE0_ENGINE_ID_EDMA_1, 527 GAUDI2_DCORE0_ENGINE_ID_MME, 528 GAUDI2_DCORE0_ENGINE_ID_TPC_0, 529 GAUDI2_DCORE0_ENGINE_ID_TPC_1, 530 GAUDI2_DCORE0_ENGINE_ID_TPC_2, 531 GAUDI2_DCORE0_ENGINE_ID_TPC_3, 532 GAUDI2_DCORE0_ENGINE_ID_TPC_4, 533 GAUDI2_DCORE0_ENGINE_ID_TPC_5, 534 GAUDI2_DCORE0_ENGINE_ID_DEC_0, 535 GAUDI2_DCORE0_ENGINE_ID_DEC_1, 536 GAUDI2_DCORE1_ENGINE_ID_EDMA_0, 537 GAUDI2_DCORE1_ENGINE_ID_EDMA_1, 538 GAUDI2_DCORE1_ENGINE_ID_MME, 539 GAUDI2_DCORE1_ENGINE_ID_TPC_0, 540 GAUDI2_DCORE1_ENGINE_ID_TPC_1, 541 GAUDI2_DCORE1_ENGINE_ID_TPC_2, 542 GAUDI2_DCORE1_ENGINE_ID_TPC_3, 543 GAUDI2_DCORE1_ENGINE_ID_TPC_4, 544 GAUDI2_DCORE1_ENGINE_ID_TPC_5, 545 GAUDI2_DCORE1_ENGINE_ID_DEC_0, 546 GAUDI2_DCORE1_ENGINE_ID_DEC_1, 547 GAUDI2_DCORE2_ENGINE_ID_EDMA_0, 548 GAUDI2_DCORE2_ENGINE_ID_EDMA_1, 549 GAUDI2_DCORE2_ENGINE_ID_MME, 550 GAUDI2_DCORE2_ENGINE_ID_TPC_0, 551 GAUDI2_DCORE2_ENGINE_ID_TPC_1, 552 GAUDI2_DCORE2_ENGINE_ID_TPC_2, 553 GAUDI2_DCORE2_ENGINE_ID_TPC_3, 554 GAUDI2_DCORE2_ENGINE_ID_TPC_4, 555 GAUDI2_DCORE2_ENGINE_ID_TPC_5, 556 GAUDI2_DCORE2_ENGINE_ID_DEC_0, 557 GAUDI2_DCORE2_ENGINE_ID_DEC_1, 558 GAUDI2_DCORE3_ENGINE_ID_EDMA_0, 559 GAUDI2_DCORE3_ENGINE_ID_EDMA_1, 560 GAUDI2_DCORE3_ENGINE_ID_MME, 561 GAUDI2_DCORE3_ENGINE_ID_TPC_0, 562 GAUDI2_DCORE3_ENGINE_ID_TPC_1, 563 GAUDI2_DCORE3_ENGINE_ID_TPC_2, 564 GAUDI2_DCORE3_ENGINE_ID_TPC_3, 565 GAUDI2_DCORE3_ENGINE_ID_TPC_4, 566 GAUDI2_DCORE3_ENGINE_ID_TPC_5, 567 GAUDI2_DCORE3_ENGINE_ID_DEC_0, 568 GAUDI2_DCORE3_ENGINE_ID_DEC_1, 569 GAUDI2_DCORE0_ENGINE_ID_TPC_6, 570 GAUDI2_ENGINE_ID_PDMA_0, 571 GAUDI2_ENGINE_ID_PDMA_1, 572 GAUDI2_ENGINE_ID_ROT_0, 573 GAUDI2_ENGINE_ID_ROT_1, 574 GAUDI2_PCIE_ENGINE_ID_DEC_0, 575 GAUDI2_PCIE_ENGINE_ID_DEC_1, 576 GAUDI2_ENGINE_ID_NIC0_0, 577 GAUDI2_ENGINE_ID_NIC0_1, 578 GAUDI2_ENGINE_ID_NIC1_0, 579 GAUDI2_ENGINE_ID_NIC1_1, 580 GAUDI2_ENGINE_ID_NIC2_0, 581 GAUDI2_ENGINE_ID_NIC2_1, 582 GAUDI2_ENGINE_ID_NIC3_0, 583 GAUDI2_ENGINE_ID_NIC3_1, 584 GAUDI2_ENGINE_ID_NIC4_0, 585 GAUDI2_ENGINE_ID_NIC4_1, 586 GAUDI2_ENGINE_ID_NIC5_0, 587 GAUDI2_ENGINE_ID_NIC5_1, 588 GAUDI2_ENGINE_ID_NIC6_0, 589 GAUDI2_ENGINE_ID_NIC6_1, 590 GAUDI2_ENGINE_ID_NIC7_0, 591 GAUDI2_ENGINE_ID_NIC7_1, 592 GAUDI2_ENGINE_ID_NIC8_0, 593 GAUDI2_ENGINE_ID_NIC8_1, 594 GAUDI2_ENGINE_ID_NIC9_0, 595 GAUDI2_ENGINE_ID_NIC9_1, 596 GAUDI2_ENGINE_ID_NIC10_0, 597 GAUDI2_ENGINE_ID_NIC10_1, 598 GAUDI2_ENGINE_ID_NIC11_0, 599 GAUDI2_ENGINE_ID_NIC11_1, 600 GAUDI2_ENGINE_ID_PCIE, 601 GAUDI2_ENGINE_ID_PSOC, 602 GAUDI2_ENGINE_ID_ARC_FARM, 603 GAUDI2_ENGINE_ID_KDMA, 604 GAUDI2_ENGINE_ID_SIZE 605 }; 606 607 /* 608 * ASIC specific PLL index 609 * 610 * Used to retrieve in frequency info of different IPs via 611 * HL_INFO_PLL_FREQUENCY under HL_IOCTL_INFO IOCTL. The enums need to be 612 * used as an index in struct hl_pll_frequency_info 613 */ 614 615 enum hl_goya_pll_index { 616 HL_GOYA_CPU_PLL = 0, 617 HL_GOYA_IC_PLL, 618 HL_GOYA_MC_PLL, 619 HL_GOYA_MME_PLL, 620 HL_GOYA_PCI_PLL, 621 HL_GOYA_EMMC_PLL, 622 HL_GOYA_TPC_PLL, 623 HL_GOYA_PLL_MAX 624 }; 625 626 enum hl_gaudi_pll_index { 627 HL_GAUDI_CPU_PLL = 0, 628 HL_GAUDI_PCI_PLL, 629 HL_GAUDI_SRAM_PLL, 630 HL_GAUDI_HBM_PLL, 631 HL_GAUDI_NIC_PLL, 632 HL_GAUDI_DMA_PLL, 633 HL_GAUDI_MESH_PLL, 634 HL_GAUDI_MME_PLL, 635 HL_GAUDI_TPC_PLL, 636 HL_GAUDI_IF_PLL, 637 HL_GAUDI_PLL_MAX 638 }; 639 640 enum hl_gaudi2_pll_index { 641 HL_GAUDI2_CPU_PLL = 0, 642 HL_GAUDI2_PCI_PLL, 643 HL_GAUDI2_SRAM_PLL, 644 HL_GAUDI2_HBM_PLL, 645 HL_GAUDI2_NIC_PLL, 646 HL_GAUDI2_DMA_PLL, 647 HL_GAUDI2_MESH_PLL, 648 HL_GAUDI2_MME_PLL, 649 HL_GAUDI2_TPC_PLL, 650 HL_GAUDI2_IF_PLL, 651 HL_GAUDI2_VID_PLL, 652 HL_GAUDI2_MSS_PLL, 653 HL_GAUDI2_PLL_MAX 654 }; 655 656 /** 657 * enum hl_goya_dma_direction - Direction of DMA operation inside a LIN_DMA packet that is 658 * submitted to the GOYA's DMA QMAN. This attribute is not relevant 659 * to the H/W but the kernel driver use it to parse the packet's 660 * addresses and patch/validate them. 661 * @HL_DMA_HOST_TO_DRAM: DMA operation from Host memory to GOYA's DDR. 662 * @HL_DMA_HOST_TO_SRAM: DMA operation from Host memory to GOYA's SRAM. 663 * @HL_DMA_DRAM_TO_SRAM: DMA operation from GOYA's DDR to GOYA's SRAM. 664 * @HL_DMA_SRAM_TO_DRAM: DMA operation from GOYA's SRAM to GOYA's DDR. 665 * @HL_DMA_SRAM_TO_HOST: DMA operation from GOYA's SRAM to Host memory. 666 * @HL_DMA_DRAM_TO_HOST: DMA operation from GOYA's DDR to Host memory. 667 * @HL_DMA_DRAM_TO_DRAM: DMA operation from GOYA's DDR to GOYA's DDR. 668 * @HL_DMA_SRAM_TO_SRAM: DMA operation from GOYA's SRAM to GOYA's SRAM. 669 * @HL_DMA_ENUM_MAX: number of values in enum 670 */ 671 enum hl_goya_dma_direction { 672 HL_DMA_HOST_TO_DRAM, 673 HL_DMA_HOST_TO_SRAM, 674 HL_DMA_DRAM_TO_SRAM, 675 HL_DMA_SRAM_TO_DRAM, 676 HL_DMA_SRAM_TO_HOST, 677 HL_DMA_DRAM_TO_HOST, 678 HL_DMA_DRAM_TO_DRAM, 679 HL_DMA_SRAM_TO_SRAM, 680 HL_DMA_ENUM_MAX 681 }; 682 683 /** 684 * enum hl_device_status - Device status information. 685 * @HL_DEVICE_STATUS_OPERATIONAL: Device is operational. 686 * @HL_DEVICE_STATUS_IN_RESET: Device is currently during reset. 687 * @HL_DEVICE_STATUS_MALFUNCTION: Device is unusable. 688 * @HL_DEVICE_STATUS_NEEDS_RESET: Device needs reset because auto reset was disabled. 689 * @HL_DEVICE_STATUS_IN_DEVICE_CREATION: Device is operational but its creation is still in 690 * progress. 691 * @HL_DEVICE_STATUS_IN_RESET_AFTER_DEVICE_RELEASE: Device is currently during reset that was 692 * triggered because the user released the device 693 * @HL_DEVICE_STATUS_LAST: Last status. 694 */ 695 enum hl_device_status { 696 HL_DEVICE_STATUS_OPERATIONAL, 697 HL_DEVICE_STATUS_IN_RESET, 698 HL_DEVICE_STATUS_MALFUNCTION, 699 HL_DEVICE_STATUS_NEEDS_RESET, 700 HL_DEVICE_STATUS_IN_DEVICE_CREATION, 701 HL_DEVICE_STATUS_IN_RESET_AFTER_DEVICE_RELEASE, 702 HL_DEVICE_STATUS_LAST = HL_DEVICE_STATUS_IN_RESET_AFTER_DEVICE_RELEASE 703 }; 704 705 enum hl_server_type { 706 HL_SERVER_TYPE_UNKNOWN = 0, 707 HL_SERVER_GAUDI_HLS1 = 1, 708 HL_SERVER_GAUDI_HLS1H = 2, 709 HL_SERVER_GAUDI_TYPE1 = 3, 710 HL_SERVER_GAUDI_TYPE2 = 4, 711 HL_SERVER_GAUDI2_HLS2 = 5 712 }; 713 714 /* 715 * Notifier event values - for the notification mechanism and the HL_INFO_GET_EVENTS command 716 * 717 * HL_NOTIFIER_EVENT_TPC_ASSERT - Indicates TPC assert event 718 * HL_NOTIFIER_EVENT_UNDEFINED_OPCODE - Indicates undefined operation code 719 * HL_NOTIFIER_EVENT_DEVICE_RESET - Indicates device requires a reset 720 * HL_NOTIFIER_EVENT_CS_TIMEOUT - Indicates CS timeout error 721 * HL_NOTIFIER_EVENT_DEVICE_UNAVAILABLE - Indicates device is unavailable 722 * HL_NOTIFIER_EVENT_USER_ENGINE_ERR - Indicates device engine in error state 723 * HL_NOTIFIER_EVENT_GENERAL_HW_ERR - Indicates device HW error 724 * HL_NOTIFIER_EVENT_RAZWI - Indicates razwi happened 725 * HL_NOTIFIER_EVENT_PAGE_FAULT - Indicates page fault happened 726 */ 727 #define HL_NOTIFIER_EVENT_TPC_ASSERT (1ULL << 0) 728 #define HL_NOTIFIER_EVENT_UNDEFINED_OPCODE (1ULL << 1) 729 #define HL_NOTIFIER_EVENT_DEVICE_RESET (1ULL << 2) 730 #define HL_NOTIFIER_EVENT_CS_TIMEOUT (1ULL << 3) 731 #define HL_NOTIFIER_EVENT_DEVICE_UNAVAILABLE (1ULL << 4) 732 #define HL_NOTIFIER_EVENT_USER_ENGINE_ERR (1ULL << 5) 733 #define HL_NOTIFIER_EVENT_GENERAL_HW_ERR (1ULL << 6) 734 #define HL_NOTIFIER_EVENT_RAZWI (1ULL << 7) 735 #define HL_NOTIFIER_EVENT_PAGE_FAULT (1ULL << 8) 736 737 /* Opcode for management ioctl 738 * 739 * HW_IP_INFO - Receive information about different IP blocks in the 740 * device. 741 * HL_INFO_HW_EVENTS - Receive an array describing how many times each event 742 * occurred since the last hard reset. 743 * HL_INFO_DRAM_USAGE - Retrieve the dram usage inside the device and of the 744 * specific context. This is relevant only for devices 745 * where the dram is managed by the kernel driver 746 * HL_INFO_HW_IDLE - Retrieve information about the idle status of each 747 * internal engine. 748 * HL_INFO_DEVICE_STATUS - Retrieve the device's status. This opcode doesn't 749 * require an open context. 750 * HL_INFO_DEVICE_UTILIZATION - Retrieve the total utilization of the device 751 * over the last period specified by the user. 752 * The period can be between 100ms to 1s, in 753 * resolution of 100ms. The return value is a 754 * percentage of the utilization rate. 755 * HL_INFO_HW_EVENTS_AGGREGATE - Receive an array describing how many times each 756 * event occurred since the driver was loaded. 757 * HL_INFO_CLK_RATE - Retrieve the current and maximum clock rate 758 * of the device in MHz. The maximum clock rate is 759 * configurable via sysfs parameter 760 * HL_INFO_RESET_COUNT - Retrieve the counts of the soft and hard reset 761 * operations performed on the device since the last 762 * time the driver was loaded. 763 * HL_INFO_TIME_SYNC - Retrieve the device's time alongside the host's time 764 * for synchronization. 765 * HL_INFO_CS_COUNTERS - Retrieve command submission counters 766 * HL_INFO_PCI_COUNTERS - Retrieve PCI counters 767 * HL_INFO_CLK_THROTTLE_REASON - Retrieve clock throttling reason 768 * HL_INFO_SYNC_MANAGER - Retrieve sync manager info per dcore 769 * HL_INFO_TOTAL_ENERGY - Retrieve total energy consumption 770 * HL_INFO_PLL_FREQUENCY - Retrieve PLL frequency 771 * HL_INFO_POWER - Retrieve power information 772 * HL_INFO_OPEN_STATS - Retrieve info regarding recent device open calls 773 * HL_INFO_DRAM_REPLACED_ROWS - Retrieve DRAM replaced rows info 774 * HL_INFO_DRAM_PENDING_ROWS - Retrieve DRAM pending rows num 775 * HL_INFO_LAST_ERR_OPEN_DEV_TIME - Retrieve timestamp of the last time the device was opened 776 * and CS timeout or razwi error occurred. 777 * HL_INFO_CS_TIMEOUT_EVENT - Retrieve CS timeout timestamp and its related CS sequence number. 778 * HL_INFO_RAZWI_EVENT - Retrieve parameters of razwi: 779 * Timestamp of razwi. 780 * The address which accessing it caused the razwi. 781 * Razwi initiator. 782 * Razwi cause, was it a page fault or MMU access error. 783 * HL_INFO_DEV_MEM_ALLOC_PAGE_SIZES - Retrieve valid page sizes for device memory allocation 784 * HL_INFO_SECURED_ATTESTATION - Retrieve attestation report of the boot. 785 * HL_INFO_REGISTER_EVENTFD - Register eventfd for event notifications. 786 * HL_INFO_UNREGISTER_EVENTFD - Unregister eventfd 787 * HL_INFO_GET_EVENTS - Retrieve the last occurred events 788 * HL_INFO_UNDEFINED_OPCODE_EVENT - Retrieve last undefined opcode error information. 789 * HL_INFO_ENGINE_STATUS - Retrieve the status of all the h/w engines in the asic. 790 * HL_INFO_PAGE_FAULT_EVENT - Retrieve parameters of captured page fault. 791 * HL_INFO_USER_MAPPINGS - Retrieve user mappings, captured after page fault event. 792 * HL_INFO_FW_GENERIC_REQ - Send generic request to FW. 793 */ 794 #define HL_INFO_HW_IP_INFO 0 795 #define HL_INFO_HW_EVENTS 1 796 #define HL_INFO_DRAM_USAGE 2 797 #define HL_INFO_HW_IDLE 3 798 #define HL_INFO_DEVICE_STATUS 4 799 #define HL_INFO_DEVICE_UTILIZATION 6 800 #define HL_INFO_HW_EVENTS_AGGREGATE 7 801 #define HL_INFO_CLK_RATE 8 802 #define HL_INFO_RESET_COUNT 9 803 #define HL_INFO_TIME_SYNC 10 804 #define HL_INFO_CS_COUNTERS 11 805 #define HL_INFO_PCI_COUNTERS 12 806 #define HL_INFO_CLK_THROTTLE_REASON 13 807 #define HL_INFO_SYNC_MANAGER 14 808 #define HL_INFO_TOTAL_ENERGY 15 809 #define HL_INFO_PLL_FREQUENCY 16 810 #define HL_INFO_POWER 17 811 #define HL_INFO_OPEN_STATS 18 812 #define HL_INFO_DRAM_REPLACED_ROWS 21 813 #define HL_INFO_DRAM_PENDING_ROWS 22 814 #define HL_INFO_LAST_ERR_OPEN_DEV_TIME 23 815 #define HL_INFO_CS_TIMEOUT_EVENT 24 816 #define HL_INFO_RAZWI_EVENT 25 817 #define HL_INFO_DEV_MEM_ALLOC_PAGE_SIZES 26 818 #define HL_INFO_SECURED_ATTESTATION 27 819 #define HL_INFO_REGISTER_EVENTFD 28 820 #define HL_INFO_UNREGISTER_EVENTFD 29 821 #define HL_INFO_GET_EVENTS 30 822 #define HL_INFO_UNDEFINED_OPCODE_EVENT 31 823 #define HL_INFO_ENGINE_STATUS 32 824 #define HL_INFO_PAGE_FAULT_EVENT 33 825 #define HL_INFO_USER_MAPPINGS 34 826 #define HL_INFO_FW_GENERIC_REQ 35 827 828 #define HL_INFO_VERSION_MAX_LEN 128 829 #define HL_INFO_CARD_NAME_MAX_LEN 16 830 831 /* Maximum buffer size for retrieving engines status */ 832 #define HL_ENGINES_DATA_MAX_SIZE SZ_1M 833 834 /** 835 * struct hl_info_hw_ip_info - hardware information on various IPs in the ASIC 836 * @sram_base_address: The first SRAM physical base address that is free to be 837 * used by the user. 838 * @dram_base_address: The first DRAM virtual or physical base address that is 839 * free to be used by the user. 840 * @dram_size: The DRAM size that is available to the user. 841 * @sram_size: The SRAM size that is available to the user. 842 * @num_of_events: The number of events that can be received from the f/w. This 843 * is needed so the user can what is the size of the h/w events 844 * array he needs to pass to the kernel when he wants to fetch 845 * the event counters. 846 * @device_id: PCI device ID of the ASIC. 847 * @module_id: Module ID of the ASIC for mezzanine cards in servers 848 * (From OCP spec). 849 * @decoder_enabled_mask: Bit-mask that represents which decoders are enabled. 850 * @first_available_interrupt_id: The first available interrupt ID for the user 851 * to be used when it works with user interrupts. 852 * Relevant for Gaudi2 and later. 853 * @server_type: Server type that the Gaudi ASIC is currently installed in. 854 * The value is according to enum hl_server_type 855 * @cpld_version: CPLD version on the board. 856 * @psoc_pci_pll_nr: PCI PLL NR value. Needed by the profiler in some ASICs. 857 * @psoc_pci_pll_nf: PCI PLL NF value. Needed by the profiler in some ASICs. 858 * @psoc_pci_pll_od: PCI PLL OD value. Needed by the profiler in some ASICs. 859 * @psoc_pci_pll_div_factor: PCI PLL DIV factor value. Needed by the profiler 860 * in some ASICs. 861 * @tpc_enabled_mask: Bit-mask that represents which TPCs are enabled. Relevant 862 * for Goya/Gaudi only. 863 * @dram_enabled: Whether the DRAM is enabled. 864 * @security_enabled: Whether security is enabled on device. 865 * @mme_master_slave_mode: Indicate whether the MME is working in master/slave 866 * configuration. Relevant for Greco and later. 867 * @cpucp_version: The CPUCP f/w version. 868 * @card_name: The card name as passed by the f/w. 869 * @tpc_enabled_mask_ext: Bit-mask that represents which TPCs are enabled. 870 * Relevant for Greco and later. 871 * @dram_page_size: The DRAM physical page size. 872 * @edma_enabled_mask: Bit-mask that represents which EDMAs are enabled. 873 * Relevant for Gaudi2 and later. 874 * @number_of_user_interrupts: The number of interrupts that are available to the userspace 875 * application to use. Relevant for Gaudi2 and later. 876 * @device_mem_alloc_default_page_size: default page size used in device memory allocation. 877 * @revision_id: PCI revision ID of the ASIC. 878 */ 879 struct hl_info_hw_ip_info { 880 __u64 sram_base_address; 881 __u64 dram_base_address; 882 __u64 dram_size; 883 __u32 sram_size; 884 __u32 num_of_events; 885 __u32 device_id; 886 __u32 module_id; 887 __u32 decoder_enabled_mask; 888 __u16 first_available_interrupt_id; 889 __u16 server_type; 890 __u32 cpld_version; 891 __u32 psoc_pci_pll_nr; 892 __u32 psoc_pci_pll_nf; 893 __u32 psoc_pci_pll_od; 894 __u32 psoc_pci_pll_div_factor; 895 __u8 tpc_enabled_mask; 896 __u8 dram_enabled; 897 __u8 security_enabled; 898 __u8 mme_master_slave_mode; 899 __u8 cpucp_version[HL_INFO_VERSION_MAX_LEN]; 900 __u8 card_name[HL_INFO_CARD_NAME_MAX_LEN]; 901 __u64 tpc_enabled_mask_ext; 902 __u64 dram_page_size; 903 __u32 edma_enabled_mask; 904 __u16 number_of_user_interrupts; 905 __u16 pad2; 906 __u64 reserved4; 907 __u64 device_mem_alloc_default_page_size; 908 __u64 reserved5; 909 __u64 reserved6; 910 __u32 reserved7; 911 __u8 reserved8; 912 __u8 revision_id; 913 __u8 pad[2]; 914 }; 915 916 struct hl_info_dram_usage { 917 __u64 dram_free_mem; 918 __u64 ctx_dram_mem; 919 }; 920 921 #define HL_BUSY_ENGINES_MASK_EXT_SIZE 4 922 923 struct hl_info_hw_idle { 924 __u32 is_idle; 925 /* 926 * Bitmask of busy engines. 927 * Bits definition is according to `enum <chip>_engine_id'. 928 */ 929 __u32 busy_engines_mask; 930 931 /* 932 * Extended Bitmask of busy engines. 933 * Bits definition is according to `enum <chip>_engine_id'. 934 */ 935 __u64 busy_engines_mask_ext[HL_BUSY_ENGINES_MASK_EXT_SIZE]; 936 }; 937 938 struct hl_info_device_status { 939 __u32 status; 940 __u32 pad; 941 }; 942 943 struct hl_info_device_utilization { 944 __u32 utilization; 945 __u32 pad; 946 }; 947 948 struct hl_info_clk_rate { 949 __u32 cur_clk_rate_mhz; 950 __u32 max_clk_rate_mhz; 951 }; 952 953 struct hl_info_reset_count { 954 __u32 hard_reset_cnt; 955 __u32 soft_reset_cnt; 956 }; 957 958 struct hl_info_time_sync { 959 __u64 device_time; 960 __u64 host_time; 961 }; 962 963 /** 964 * struct hl_info_pci_counters - pci counters 965 * @rx_throughput: PCI rx throughput KBps 966 * @tx_throughput: PCI tx throughput KBps 967 * @replay_cnt: PCI replay counter 968 */ 969 struct hl_info_pci_counters { 970 __u64 rx_throughput; 971 __u64 tx_throughput; 972 __u64 replay_cnt; 973 }; 974 975 enum hl_clk_throttling_type { 976 HL_CLK_THROTTLE_TYPE_POWER, 977 HL_CLK_THROTTLE_TYPE_THERMAL, 978 HL_CLK_THROTTLE_TYPE_MAX 979 }; 980 981 /* clk_throttling_reason masks */ 982 #define HL_CLK_THROTTLE_POWER (1 << HL_CLK_THROTTLE_TYPE_POWER) 983 #define HL_CLK_THROTTLE_THERMAL (1 << HL_CLK_THROTTLE_TYPE_THERMAL) 984 985 /** 986 * struct hl_info_clk_throttle - clock throttling reason 987 * @clk_throttling_reason: each bit represents a clk throttling reason 988 * @clk_throttling_timestamp_us: represents CPU timestamp in microseconds of the start-event 989 * @clk_throttling_duration_ns: the clock throttle time in nanosec 990 */ 991 struct hl_info_clk_throttle { 992 __u32 clk_throttling_reason; 993 __u32 pad; 994 __u64 clk_throttling_timestamp_us[HL_CLK_THROTTLE_TYPE_MAX]; 995 __u64 clk_throttling_duration_ns[HL_CLK_THROTTLE_TYPE_MAX]; 996 }; 997 998 /** 999 * struct hl_info_energy - device energy information 1000 * @total_energy_consumption: total device energy consumption 1001 */ 1002 struct hl_info_energy { 1003 __u64 total_energy_consumption; 1004 }; 1005 1006 #define HL_PLL_NUM_OUTPUTS 4 1007 1008 struct hl_pll_frequency_info { 1009 __u16 output[HL_PLL_NUM_OUTPUTS]; 1010 }; 1011 1012 /** 1013 * struct hl_open_stats_info - device open statistics information 1014 * @open_counter: ever growing counter, increased on each successful dev open 1015 * @last_open_period_ms: duration (ms) device was open last time 1016 * @is_compute_ctx_active: Whether there is an active compute context executing 1017 * @compute_ctx_in_release: true if the current compute context is being released 1018 */ 1019 struct hl_open_stats_info { 1020 __u64 open_counter; 1021 __u64 last_open_period_ms; 1022 __u8 is_compute_ctx_active; 1023 __u8 compute_ctx_in_release; 1024 __u8 pad[6]; 1025 }; 1026 1027 /** 1028 * struct hl_power_info - power information 1029 * @power: power consumption 1030 */ 1031 struct hl_power_info { 1032 __u64 power; 1033 }; 1034 1035 /** 1036 * struct hl_info_sync_manager - sync manager information 1037 * @first_available_sync_object: first available sob 1038 * @first_available_monitor: first available monitor 1039 * @first_available_cq: first available cq 1040 */ 1041 struct hl_info_sync_manager { 1042 __u32 first_available_sync_object; 1043 __u32 first_available_monitor; 1044 __u32 first_available_cq; 1045 __u32 reserved; 1046 }; 1047 1048 /** 1049 * struct hl_info_cs_counters - command submission counters 1050 * @total_out_of_mem_drop_cnt: total dropped due to memory allocation issue 1051 * @ctx_out_of_mem_drop_cnt: context dropped due to memory allocation issue 1052 * @total_parsing_drop_cnt: total dropped due to error in packet parsing 1053 * @ctx_parsing_drop_cnt: context dropped due to error in packet parsing 1054 * @total_queue_full_drop_cnt: total dropped due to queue full 1055 * @ctx_queue_full_drop_cnt: context dropped due to queue full 1056 * @total_device_in_reset_drop_cnt: total dropped due to device in reset 1057 * @ctx_device_in_reset_drop_cnt: context dropped due to device in reset 1058 * @total_max_cs_in_flight_drop_cnt: total dropped due to maximum CS in-flight 1059 * @ctx_max_cs_in_flight_drop_cnt: context dropped due to maximum CS in-flight 1060 * @total_validation_drop_cnt: total dropped due to validation error 1061 * @ctx_validation_drop_cnt: context dropped due to validation error 1062 */ 1063 struct hl_info_cs_counters { 1064 __u64 total_out_of_mem_drop_cnt; 1065 __u64 ctx_out_of_mem_drop_cnt; 1066 __u64 total_parsing_drop_cnt; 1067 __u64 ctx_parsing_drop_cnt; 1068 __u64 total_queue_full_drop_cnt; 1069 __u64 ctx_queue_full_drop_cnt; 1070 __u64 total_device_in_reset_drop_cnt; 1071 __u64 ctx_device_in_reset_drop_cnt; 1072 __u64 total_max_cs_in_flight_drop_cnt; 1073 __u64 ctx_max_cs_in_flight_drop_cnt; 1074 __u64 total_validation_drop_cnt; 1075 __u64 ctx_validation_drop_cnt; 1076 }; 1077 1078 /** 1079 * struct hl_info_last_err_open_dev_time - last error boot information. 1080 * @timestamp: timestamp of last time the device was opened and error occurred. 1081 */ 1082 struct hl_info_last_err_open_dev_time { 1083 __s64 timestamp; 1084 }; 1085 1086 /** 1087 * struct hl_info_cs_timeout_event - last CS timeout information. 1088 * @timestamp: timestamp when last CS timeout event occurred. 1089 * @seq: sequence number of last CS timeout event. 1090 */ 1091 struct hl_info_cs_timeout_event { 1092 __s64 timestamp; 1093 __u64 seq; 1094 }; 1095 1096 #define HL_RAZWI_NA_ENG_ID U16_MAX 1097 #define HL_RAZWI_MAX_NUM_OF_ENGINES_PER_RTR 128 1098 #define HL_RAZWI_READ BIT(0) 1099 #define HL_RAZWI_WRITE BIT(1) 1100 #define HL_RAZWI_LBW BIT(2) 1101 #define HL_RAZWI_HBW BIT(3) 1102 #define HL_RAZWI_RR BIT(4) 1103 #define HL_RAZWI_ADDR_DEC BIT(5) 1104 1105 /** 1106 * struct hl_info_razwi_event - razwi information. 1107 * @timestamp: timestamp of razwi. 1108 * @addr: address which accessing it caused razwi. 1109 * @engine_id: engine id of the razwi initiator, if it was initiated by engine that does not 1110 * have engine id it will be set to HL_RAZWI_NA_ENG_ID. If there are several possible 1111 * engines which caused the razwi, it will hold all of them. 1112 * @num_of_possible_engines: contains number of possible engine ids. In some asics, razwi indication 1113 * might be common for several engines and there is no way to get the 1114 * exact engine. In this way, engine_id array will be filled with all 1115 * possible engines caused this razwi. Also, there might be possibility 1116 * in gaudi, where we don't indication on specific engine, in that case 1117 * the value of this parameter will be zero. 1118 * @flags: bitmask for additional data: HL_RAZWI_READ - razwi caused by read operation 1119 * HL_RAZWI_WRITE - razwi caused by write operation 1120 * HL_RAZWI_LBW - razwi caused by lbw fabric transaction 1121 * HL_RAZWI_HBW - razwi caused by hbw fabric transaction 1122 * HL_RAZWI_RR - razwi caused by range register 1123 * HL_RAZWI_ADDR_DEC - razwi caused by address decode error 1124 * Note: this data is not supported by all asics, in that case the relevant bits will not 1125 * be set. 1126 */ 1127 struct hl_info_razwi_event { 1128 __s64 timestamp; 1129 __u64 addr; 1130 __u16 engine_id[HL_RAZWI_MAX_NUM_OF_ENGINES_PER_RTR]; 1131 __u16 num_of_possible_engines; 1132 __u8 flags; 1133 __u8 pad[5]; 1134 }; 1135 1136 #define MAX_QMAN_STREAMS_INFO 4 1137 #define OPCODE_INFO_MAX_ADDR_SIZE 8 1138 /** 1139 * struct hl_info_undefined_opcode_event - info about last undefined opcode error 1140 * @timestamp: timestamp of the undefined opcode error 1141 * @cb_addr_streams: CB addresses (per stream) that are currently exists in the PQ 1142 * entries. In case all streams array entries are 1143 * filled with values, it means the execution was in Lower-CP. 1144 * @cq_addr: the address of the current handled command buffer 1145 * @cq_size: the size of the current handled command buffer 1146 * @cb_addr_streams_len: num of streams - actual len of cb_addr_streams array. 1147 * should be equal to 1 in case of undefined opcode 1148 * in Upper-CP (specific stream) and equal to 4 incase 1149 * of undefined opcode in Lower-CP. 1150 * @engine_id: engine-id that the error occurred on 1151 * @stream_id: the stream id the error occurred on. In case the stream equals to 1152 * MAX_QMAN_STREAMS_INFO it means the error occurred on a Lower-CP. 1153 */ 1154 struct hl_info_undefined_opcode_event { 1155 __s64 timestamp; 1156 __u64 cb_addr_streams[MAX_QMAN_STREAMS_INFO][OPCODE_INFO_MAX_ADDR_SIZE]; 1157 __u64 cq_addr; 1158 __u32 cq_size; 1159 __u32 cb_addr_streams_len; 1160 __u32 engine_id; 1161 __u32 stream_id; 1162 }; 1163 1164 /** 1165 * struct hl_info_dev_memalloc_page_sizes - valid page sizes in device mem alloc information. 1166 * @page_order_bitmask: bitmap in which a set bit represents the order of the supported page size 1167 * (e.g. 0x2100000 means that 1MB and 32MB pages are supported). 1168 */ 1169 struct hl_info_dev_memalloc_page_sizes { 1170 __u64 page_order_bitmask; 1171 }; 1172 1173 #define SEC_PCR_DATA_BUF_SZ 256 1174 #define SEC_PCR_QUOTE_BUF_SZ 510 /* (512 - 2) 2 bytes used for size */ 1175 #define SEC_SIGNATURE_BUF_SZ 255 /* (256 - 1) 1 byte used for size */ 1176 #define SEC_PUB_DATA_BUF_SZ 510 /* (512 - 2) 2 bytes used for size */ 1177 #define SEC_CERTIFICATE_BUF_SZ 2046 /* (2048 - 2) 2 bytes used for size */ 1178 1179 /* 1180 * struct hl_info_sec_attest - attestation report of the boot 1181 * @nonce: number only used once. random number provided by host. this also passed to the quote 1182 * command as a qualifying data. 1183 * @pcr_quote_len: length of the attestation quote data (bytes) 1184 * @pub_data_len: length of the public data (bytes) 1185 * @certificate_len: length of the certificate (bytes) 1186 * @pcr_num_reg: number of PCR registers in the pcr_data array 1187 * @pcr_reg_len: length of each PCR register in the pcr_data array (bytes) 1188 * @quote_sig_len: length of the attestation report signature (bytes) 1189 * @pcr_data: raw values of the PCR registers 1190 * @pcr_quote: attestation report data structure 1191 * @quote_sig: signature structure of the attestation report 1192 * @public_data: public key for the signed attestation 1193 * (outPublic + name + qualifiedName) 1194 * @certificate: certificate for the attestation signing key 1195 */ 1196 struct hl_info_sec_attest { 1197 __u32 nonce; 1198 __u16 pcr_quote_len; 1199 __u16 pub_data_len; 1200 __u16 certificate_len; 1201 __u8 pcr_num_reg; 1202 __u8 pcr_reg_len; 1203 __u8 quote_sig_len; 1204 __u8 pcr_data[SEC_PCR_DATA_BUF_SZ]; 1205 __u8 pcr_quote[SEC_PCR_QUOTE_BUF_SZ]; 1206 __u8 quote_sig[SEC_SIGNATURE_BUF_SZ]; 1207 __u8 public_data[SEC_PUB_DATA_BUF_SZ]; 1208 __u8 certificate[SEC_CERTIFICATE_BUF_SZ]; 1209 __u8 pad0[2]; 1210 }; 1211 1212 /** 1213 * struct hl_page_fault_info - page fault information. 1214 * @timestamp: timestamp of page fault. 1215 * @addr: address which accessing it caused page fault. 1216 * @engine_id: engine id which caused the page fault, supported only in gaudi3. 1217 */ 1218 struct hl_page_fault_info { 1219 __s64 timestamp; 1220 __u64 addr; 1221 __u16 engine_id; 1222 __u8 pad[6]; 1223 }; 1224 1225 /** 1226 * struct hl_user_mapping - user mapping information. 1227 * @dev_va: device virtual address. 1228 * @size: virtual address mapping size. 1229 */ 1230 struct hl_user_mapping { 1231 __u64 dev_va; 1232 __u64 size; 1233 }; 1234 1235 enum gaudi_dcores { 1236 HL_GAUDI_WS_DCORE, 1237 HL_GAUDI_WN_DCORE, 1238 HL_GAUDI_EN_DCORE, 1239 HL_GAUDI_ES_DCORE 1240 }; 1241 1242 /** 1243 * struct hl_info_args - Main structure to retrieve device related information. 1244 * @return_pointer: User space address of the relevant structure related to HL_INFO_* operation 1245 * mentioned in @op. 1246 * @return_size: Size of the structure used in @return_pointer, just like "size" in "snprintf", it 1247 * limits how many bytes the kernel can write. For hw_events array, the size should be 1248 * hl_info_hw_ip_info.num_of_events * sizeof(__u32). 1249 * @op: Defines which type of information to be retrieved. Refer HL_INFO_* for details. 1250 * @dcore_id: DCORE id for which the information is relevant (for Gaudi refer to enum gaudi_dcores). 1251 * @ctx_id: Context ID of the user. Currently not in use. 1252 * @period_ms: Period value, in milliseconds, for utilization rate in range 100ms - 1000ms in 100 ms 1253 * resolution. Currently not in use. 1254 * @pll_index: Index as defined in hl_<asic type>_pll_index enumeration. 1255 * @eventfd: event file descriptor for event notifications. 1256 * @user_buffer_actual_size: Actual data size which was copied to user allocated buffer by the 1257 * driver. It is possible for the user to allocate buffer larger than 1258 * needed, hence updating this variable so user will know the exact amount 1259 * of bytes copied by the kernel to the buffer. 1260 * @sec_attest_nonce: Nonce number used for attestation report. 1261 * @array_size: Number of array members copied to user buffer. 1262 * Relevant for HL_INFO_USER_MAPPINGS info ioctl. 1263 * @fw_sub_opcode: generic requests sub opcodes. 1264 * @pad: Padding to 64 bit. 1265 */ 1266 struct hl_info_args { 1267 __u64 return_pointer; 1268 __u32 return_size; 1269 __u32 op; 1270 1271 union { 1272 __u32 dcore_id; 1273 __u32 ctx_id; 1274 __u32 period_ms; 1275 __u32 pll_index; 1276 __u32 eventfd; 1277 __u32 user_buffer_actual_size; 1278 __u32 sec_attest_nonce; 1279 __u32 array_size; 1280 __u32 fw_sub_opcode; 1281 }; 1282 1283 __u32 pad; 1284 }; 1285 1286 /* Opcode to create a new command buffer */ 1287 #define HL_CB_OP_CREATE 0 1288 /* Opcode to destroy previously created command buffer */ 1289 #define HL_CB_OP_DESTROY 1 1290 /* Opcode to retrieve information about a command buffer */ 1291 #define HL_CB_OP_INFO 2 1292 1293 /* 2MB minus 32 bytes for 2xMSG_PROT */ 1294 #define HL_MAX_CB_SIZE (0x200000 - 32) 1295 1296 /* Indicates whether the command buffer should be mapped to the device's MMU */ 1297 #define HL_CB_FLAGS_MAP 0x1 1298 1299 /* Used with HL_CB_OP_INFO opcode to get the device va address for kernel mapped CB */ 1300 #define HL_CB_FLAGS_GET_DEVICE_VA 0x2 1301 1302 struct hl_cb_in { 1303 /* Handle of CB or 0 if we want to create one */ 1304 __u64 cb_handle; 1305 /* HL_CB_OP_* */ 1306 __u32 op; 1307 1308 /* Size of CB. Maximum size is HL_MAX_CB_SIZE. The minimum size that 1309 * will be allocated, regardless of this parameter's value, is PAGE_SIZE 1310 */ 1311 __u32 cb_size; 1312 1313 /* Context ID - Currently not in use */ 1314 __u32 ctx_id; 1315 /* HL_CB_FLAGS_* */ 1316 __u32 flags; 1317 }; 1318 1319 struct hl_cb_out { 1320 union { 1321 /* Handle of CB */ 1322 __u64 cb_handle; 1323 1324 union { 1325 /* Information about CB */ 1326 struct { 1327 /* Usage count of CB */ 1328 __u32 usage_cnt; 1329 __u32 pad; 1330 }; 1331 1332 /* CB mapped address to device MMU */ 1333 __u64 device_va; 1334 }; 1335 }; 1336 }; 1337 1338 union hl_cb_args { 1339 struct hl_cb_in in; 1340 struct hl_cb_out out; 1341 }; 1342 1343 /* HL_CS_CHUNK_FLAGS_ values 1344 * 1345 * HL_CS_CHUNK_FLAGS_USER_ALLOC_CB: 1346 * Indicates if the CB was allocated and mapped by userspace 1347 * (relevant to greco and above). User allocated CB is a command buffer, 1348 * allocated by the user, via malloc (or similar). After allocating the 1349 * CB, the user invokes - “memory ioctl” to map the user memory into a 1350 * device virtual address. The user provides this address via the 1351 * cb_handle field. The interface provides the ability to create a 1352 * large CBs, Which aren’t limited to “HL_MAX_CB_SIZE”. Therefore, it 1353 * increases the PCI-DMA queues throughput. This CB allocation method 1354 * also reduces the use of Linux DMA-able memory pool. Which are limited 1355 * and used by other Linux sub-systems. 1356 */ 1357 #define HL_CS_CHUNK_FLAGS_USER_ALLOC_CB 0x1 1358 1359 /* 1360 * This structure size must always be fixed to 64-bytes for backward 1361 * compatibility 1362 */ 1363 struct hl_cs_chunk { 1364 union { 1365 /* Goya/Gaudi: 1366 * For external queue, this represents a Handle of CB on the 1367 * Host. 1368 * For internal queue in Goya, this represents an SRAM or 1369 * a DRAM address of the internal CB. In Gaudi, this might also 1370 * represent a mapped host address of the CB. 1371 * 1372 * Greco onwards: 1373 * For H/W queue, this represents either a Handle of CB on the 1374 * Host, or an SRAM, a DRAM, or a mapped host address of the CB. 1375 * 1376 * A mapped host address is in the device address space, after 1377 * a host address was mapped by the device MMU. 1378 */ 1379 __u64 cb_handle; 1380 1381 /* Relevant only when HL_CS_FLAGS_WAIT or 1382 * HL_CS_FLAGS_COLLECTIVE_WAIT is set 1383 * This holds address of array of u64 values that contain 1384 * signal CS sequence numbers. The wait described by 1385 * this job will listen on all those signals 1386 * (wait event per signal) 1387 */ 1388 __u64 signal_seq_arr; 1389 1390 /* 1391 * Relevant only when HL_CS_FLAGS_WAIT or 1392 * HL_CS_FLAGS_COLLECTIVE_WAIT is set 1393 * along with HL_CS_FLAGS_ENCAP_SIGNALS. 1394 * This is the CS sequence which has the encapsulated signals. 1395 */ 1396 __u64 encaps_signal_seq; 1397 }; 1398 1399 /* Index of queue to put the CB on */ 1400 __u32 queue_index; 1401 1402 union { 1403 /* 1404 * Size of command buffer with valid packets 1405 * Can be smaller then actual CB size 1406 */ 1407 __u32 cb_size; 1408 1409 /* Relevant only when HL_CS_FLAGS_WAIT or 1410 * HL_CS_FLAGS_COLLECTIVE_WAIT is set. 1411 * Number of entries in signal_seq_arr 1412 */ 1413 __u32 num_signal_seq_arr; 1414 1415 /* Relevant only when HL_CS_FLAGS_WAIT or 1416 * HL_CS_FLAGS_COLLECTIVE_WAIT is set along 1417 * with HL_CS_FLAGS_ENCAP_SIGNALS 1418 * This set the signals range that the user want to wait for 1419 * out of the whole reserved signals range. 1420 * e.g if the signals range is 20, and user don't want 1421 * to wait for signal 8, so he set this offset to 7, then 1422 * he call the API again with 9 and so on till 20. 1423 */ 1424 __u32 encaps_signal_offset; 1425 }; 1426 1427 /* HL_CS_CHUNK_FLAGS_* */ 1428 __u32 cs_chunk_flags; 1429 1430 /* Relevant only when HL_CS_FLAGS_COLLECTIVE_WAIT is set. 1431 * This holds the collective engine ID. The wait described by this job 1432 * will sync with this engine and with all NICs before completion. 1433 */ 1434 __u32 collective_engine_id; 1435 1436 /* Align structure to 64 bytes */ 1437 __u32 pad[10]; 1438 }; 1439 1440 /* SIGNAL/WAIT/COLLECTIVE_WAIT flags are mutually exclusive */ 1441 #define HL_CS_FLAGS_FORCE_RESTORE 0x1 1442 #define HL_CS_FLAGS_SIGNAL 0x2 1443 #define HL_CS_FLAGS_WAIT 0x4 1444 #define HL_CS_FLAGS_COLLECTIVE_WAIT 0x8 1445 1446 #define HL_CS_FLAGS_TIMESTAMP 0x20 1447 #define HL_CS_FLAGS_STAGED_SUBMISSION 0x40 1448 #define HL_CS_FLAGS_STAGED_SUBMISSION_FIRST 0x80 1449 #define HL_CS_FLAGS_STAGED_SUBMISSION_LAST 0x100 1450 #define HL_CS_FLAGS_CUSTOM_TIMEOUT 0x200 1451 #define HL_CS_FLAGS_SKIP_RESET_ON_TIMEOUT 0x400 1452 1453 /* 1454 * The encapsulated signals CS is merged into the existing CS ioctls. 1455 * In order to use this feature need to follow the below procedure: 1456 * 1. Reserve signals, set the CS type to HL_CS_FLAGS_RESERVE_SIGNALS_ONLY 1457 * the output of this API will be the SOB offset from CFG_BASE. 1458 * this address will be used to patch CB cmds to do the signaling for this 1459 * SOB by incrementing it's value. 1460 * for reverting the reservation use HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY 1461 * CS type, note that this might fail if out-of-sync happened to the SOB 1462 * value, in case other signaling request to the same SOB occurred between 1463 * reserve-unreserve calls. 1464 * 2. Use the staged CS to do the encapsulated signaling jobs. 1465 * use HL_CS_FLAGS_STAGED_SUBMISSION and HL_CS_FLAGS_STAGED_SUBMISSION_FIRST 1466 * along with HL_CS_FLAGS_ENCAP_SIGNALS flag, and set encaps_signal_offset 1467 * field. This offset allows app to wait on part of the reserved signals. 1468 * 3. Use WAIT/COLLECTIVE WAIT CS along with HL_CS_FLAGS_ENCAP_SIGNALS flag 1469 * to wait for the encapsulated signals. 1470 */ 1471 #define HL_CS_FLAGS_ENCAP_SIGNALS 0x800 1472 #define HL_CS_FLAGS_RESERVE_SIGNALS_ONLY 0x1000 1473 #define HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY 0x2000 1474 1475 /* 1476 * The engine cores CS is merged into the existing CS ioctls. 1477 * Use it to control the engine cores mode. 1478 */ 1479 #define HL_CS_FLAGS_ENGINE_CORE_COMMAND 0x4000 1480 1481 /* 1482 * The flush HBW PCI writes is merged into the existing CS ioctls. 1483 * Used to flush all HBW PCI writes. 1484 * This is a blocking operation and for this reason the user shall not use 1485 * the return sequence number (which will be invalid anyway) 1486 */ 1487 #define HL_CS_FLAGS_FLUSH_PCI_HBW_WRITES 0x8000 1488 1489 #define HL_CS_STATUS_SUCCESS 0 1490 1491 #define HL_MAX_JOBS_PER_CS 512 1492 1493 /* HL_ENGINE_CORE_ values 1494 * 1495 * HL_ENGINE_CORE_HALT: engine core halt 1496 * HL_ENGINE_CORE_RUN: engine core run 1497 */ 1498 #define HL_ENGINE_CORE_HALT (1 << 0) 1499 #define HL_ENGINE_CORE_RUN (1 << 1) 1500 1501 struct hl_cs_in { 1502 1503 union { 1504 struct { 1505 /* this holds address of array of hl_cs_chunk for restore phase */ 1506 __u64 chunks_restore; 1507 1508 /* holds address of array of hl_cs_chunk for execution phase */ 1509 __u64 chunks_execute; 1510 }; 1511 1512 /* Valid only when HL_CS_FLAGS_ENGINE_CORE_COMMAND is set */ 1513 struct { 1514 /* this holds address of array of uint32 for engine_cores */ 1515 __u64 engine_cores; 1516 1517 /* number of engine cores in engine_cores array */ 1518 __u32 num_engine_cores; 1519 1520 /* the core command to be sent towards engine cores */ 1521 __u32 core_command; 1522 }; 1523 }; 1524 1525 union { 1526 /* 1527 * Sequence number of a staged submission CS 1528 * valid only if HL_CS_FLAGS_STAGED_SUBMISSION is set and 1529 * HL_CS_FLAGS_STAGED_SUBMISSION_FIRST is unset. 1530 */ 1531 __u64 seq; 1532 1533 /* 1534 * Encapsulated signals handle id 1535 * Valid for two flows: 1536 * 1. CS with encapsulated signals: 1537 * when HL_CS_FLAGS_STAGED_SUBMISSION and 1538 * HL_CS_FLAGS_STAGED_SUBMISSION_FIRST 1539 * and HL_CS_FLAGS_ENCAP_SIGNALS are set. 1540 * 2. unreserve signals: 1541 * valid when HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY is set. 1542 */ 1543 __u32 encaps_sig_handle_id; 1544 1545 /* Valid only when HL_CS_FLAGS_RESERVE_SIGNALS_ONLY is set */ 1546 struct { 1547 /* Encapsulated signals number */ 1548 __u32 encaps_signals_count; 1549 1550 /* Encapsulated signals queue index (stream) */ 1551 __u32 encaps_signals_q_idx; 1552 }; 1553 }; 1554 1555 /* Number of chunks in restore phase array. Maximum number is 1556 * HL_MAX_JOBS_PER_CS 1557 */ 1558 __u32 num_chunks_restore; 1559 1560 /* Number of chunks in execution array. Maximum number is 1561 * HL_MAX_JOBS_PER_CS 1562 */ 1563 __u32 num_chunks_execute; 1564 1565 /* timeout in seconds - valid only if HL_CS_FLAGS_CUSTOM_TIMEOUT 1566 * is set 1567 */ 1568 __u32 timeout; 1569 1570 /* HL_CS_FLAGS_* */ 1571 __u32 cs_flags; 1572 1573 /* Context ID - Currently not in use */ 1574 __u32 ctx_id; 1575 __u8 pad[4]; 1576 }; 1577 1578 struct hl_cs_out { 1579 union { 1580 /* 1581 * seq holds the sequence number of the CS to pass to wait 1582 * ioctl. All values are valid except for 0 and ULLONG_MAX 1583 */ 1584 __u64 seq; 1585 1586 /* Valid only when HL_CS_FLAGS_RESERVE_SIGNALS_ONLY is set */ 1587 struct { 1588 /* This is the reserved signal handle id */ 1589 __u32 handle_id; 1590 1591 /* This is the signals count */ 1592 __u32 count; 1593 }; 1594 }; 1595 1596 /* HL_CS_STATUS */ 1597 __u32 status; 1598 1599 /* 1600 * SOB base address offset 1601 * Valid only when HL_CS_FLAGS_RESERVE_SIGNALS_ONLY or HL_CS_FLAGS_SIGNAL is set 1602 */ 1603 __u32 sob_base_addr_offset; 1604 1605 /* 1606 * Count of completed signals in SOB before current signal submission. 1607 * Valid only when (HL_CS_FLAGS_ENCAP_SIGNALS & HL_CS_FLAGS_STAGED_SUBMISSION) 1608 * or HL_CS_FLAGS_SIGNAL is set 1609 */ 1610 __u16 sob_count_before_submission; 1611 __u16 pad[3]; 1612 }; 1613 1614 union hl_cs_args { 1615 struct hl_cs_in in; 1616 struct hl_cs_out out; 1617 }; 1618 1619 #define HL_WAIT_CS_FLAGS_INTERRUPT 0x2 1620 #define HL_WAIT_CS_FLAGS_INTERRUPT_MASK 0xFFF00000 1621 #define HL_WAIT_CS_FLAGS_ANY_CQ_INTERRUPT 0xFFF00000 1622 #define HL_WAIT_CS_FLAGS_ANY_DEC_INTERRUPT 0xFFE00000 1623 #define HL_WAIT_CS_FLAGS_MULTI_CS 0x4 1624 #define HL_WAIT_CS_FLAGS_INTERRUPT_KERNEL_CQ 0x10 1625 #define HL_WAIT_CS_FLAGS_REGISTER_INTERRUPT 0x20 1626 1627 #define HL_WAIT_MULTI_CS_LIST_MAX_LEN 32 1628 1629 struct hl_wait_cs_in { 1630 union { 1631 struct { 1632 /* 1633 * In case of wait_cs holds the CS sequence number. 1634 * In case of wait for multi CS hold a user pointer to 1635 * an array of CS sequence numbers 1636 */ 1637 __u64 seq; 1638 /* Absolute timeout to wait for command submission 1639 * in microseconds 1640 */ 1641 __u64 timeout_us; 1642 }; 1643 1644 struct { 1645 union { 1646 /* User address for completion comparison. 1647 * upon interrupt, driver will compare the value pointed 1648 * by this address with the supplied target value. 1649 * in order not to perform any comparison, set address 1650 * to all 1s. 1651 * Relevant only when HL_WAIT_CS_FLAGS_INTERRUPT is set 1652 */ 1653 __u64 addr; 1654 1655 /* cq_counters_handle to a kernel mapped cb which contains 1656 * cq counters. 1657 * Relevant only when HL_WAIT_CS_FLAGS_INTERRUPT_KERNEL_CQ is set 1658 */ 1659 __u64 cq_counters_handle; 1660 }; 1661 1662 /* Target value for completion comparison */ 1663 __u64 target; 1664 }; 1665 }; 1666 1667 /* Context ID - Currently not in use */ 1668 __u32 ctx_id; 1669 1670 /* HL_WAIT_CS_FLAGS_* 1671 * If HL_WAIT_CS_FLAGS_INTERRUPT is set, this field should include 1672 * interrupt id according to HL_WAIT_CS_FLAGS_INTERRUPT_MASK 1673 * 1674 * in order to wait for any CQ interrupt, set interrupt value to 1675 * HL_WAIT_CS_FLAGS_ANY_CQ_INTERRUPT. 1676 * 1677 * in order to wait for any decoder interrupt, set interrupt value to 1678 * HL_WAIT_CS_FLAGS_ANY_DEC_INTERRUPT. 1679 */ 1680 __u32 flags; 1681 1682 union { 1683 struct { 1684 /* Multi CS API info- valid entries in multi-CS array */ 1685 __u8 seq_arr_len; 1686 __u8 pad[7]; 1687 }; 1688 1689 /* Absolute timeout to wait for an interrupt in microseconds. 1690 * Relevant only when HL_WAIT_CS_FLAGS_INTERRUPT is set 1691 */ 1692 __u64 interrupt_timeout_us; 1693 }; 1694 1695 /* 1696 * cq counter offset inside the counters cb pointed by cq_counters_handle above. 1697 * upon interrupt, driver will compare the value pointed 1698 * by this address (cq_counters_handle + cq_counters_offset) 1699 * with the supplied target value. 1700 * relevant only when HL_WAIT_CS_FLAGS_INTERRUPT_KERNEL_CQ is set 1701 */ 1702 __u64 cq_counters_offset; 1703 1704 /* 1705 * Timestamp_handle timestamps buffer handle. 1706 * relevant only when HL_WAIT_CS_FLAGS_REGISTER_INTERRUPT is set 1707 */ 1708 __u64 timestamp_handle; 1709 1710 /* 1711 * Timestamp_offset is offset inside the timestamp buffer pointed by timestamp_handle above. 1712 * upon interrupt, if the cq reached the target value then driver will write 1713 * timestamp to this offset. 1714 * relevant only when HL_WAIT_CS_FLAGS_REGISTER_INTERRUPT is set 1715 */ 1716 __u64 timestamp_offset; 1717 }; 1718 1719 #define HL_WAIT_CS_STATUS_COMPLETED 0 1720 #define HL_WAIT_CS_STATUS_BUSY 1 1721 #define HL_WAIT_CS_STATUS_TIMEDOUT 2 1722 #define HL_WAIT_CS_STATUS_ABORTED 3 1723 1724 #define HL_WAIT_CS_STATUS_FLAG_GONE 0x1 1725 #define HL_WAIT_CS_STATUS_FLAG_TIMESTAMP_VLD 0x2 1726 1727 struct hl_wait_cs_out { 1728 /* HL_WAIT_CS_STATUS_* */ 1729 __u32 status; 1730 /* HL_WAIT_CS_STATUS_FLAG* */ 1731 __u32 flags; 1732 /* 1733 * valid only if HL_WAIT_CS_STATUS_FLAG_TIMESTAMP_VLD is set 1734 * for wait_cs: timestamp of CS completion 1735 * for wait_multi_cs: timestamp of FIRST CS completion 1736 */ 1737 __s64 timestamp_nsec; 1738 /* multi CS completion bitmap */ 1739 __u32 cs_completion_map; 1740 __u32 pad; 1741 }; 1742 1743 union hl_wait_cs_args { 1744 struct hl_wait_cs_in in; 1745 struct hl_wait_cs_out out; 1746 }; 1747 1748 /* Opcode to allocate device memory */ 1749 #define HL_MEM_OP_ALLOC 0 1750 1751 /* Opcode to free previously allocated device memory */ 1752 #define HL_MEM_OP_FREE 1 1753 1754 /* Opcode to map host and device memory */ 1755 #define HL_MEM_OP_MAP 2 1756 1757 /* Opcode to unmap previously mapped host and device memory */ 1758 #define HL_MEM_OP_UNMAP 3 1759 1760 /* Opcode to map a hw block */ 1761 #define HL_MEM_OP_MAP_BLOCK 4 1762 1763 /* Opcode to create DMA-BUF object for an existing device memory allocation 1764 * and to export an FD of that DMA-BUF back to the caller 1765 */ 1766 #define HL_MEM_OP_EXPORT_DMABUF_FD 5 1767 1768 /* Opcode to create timestamps pool for user interrupts registration support 1769 * The memory will be allocated by the kernel driver, A timestamp buffer which the user 1770 * will get handle to it for mmap, and another internal buffer used by the 1771 * driver for registration management 1772 * The memory will be freed when the user closes the file descriptor(ctx close) 1773 */ 1774 #define HL_MEM_OP_TS_ALLOC 6 1775 1776 /* Memory flags */ 1777 #define HL_MEM_CONTIGUOUS 0x1 1778 #define HL_MEM_SHARED 0x2 1779 #define HL_MEM_USERPTR 0x4 1780 #define HL_MEM_FORCE_HINT 0x8 1781 #define HL_MEM_PREFETCH 0x40 1782 1783 /** 1784 * structure hl_mem_in - structure that handle input args for memory IOCTL 1785 * @union arg: union of structures to be used based on the input operation 1786 * @op: specify the requested memory operation (one of the HL_MEM_OP_* definitions). 1787 * @flags: flags for the memory operation (one of the HL_MEM_* definitions). 1788 * For the HL_MEM_OP_EXPORT_DMABUF_FD opcode, this field holds the DMA-BUF file/FD flags. 1789 * @ctx_id: context ID - currently not in use. 1790 * @num_of_elements: number of timestamp elements used only with HL_MEM_OP_TS_ALLOC opcode. 1791 */ 1792 struct hl_mem_in { 1793 union { 1794 /** 1795 * structure for device memory allocation (used with the HL_MEM_OP_ALLOC op) 1796 * @mem_size: memory size to allocate 1797 * @page_size: page size to use on allocation. when the value is 0 the default page 1798 * size will be taken. 1799 */ 1800 struct { 1801 __u64 mem_size; 1802 __u64 page_size; 1803 } alloc; 1804 1805 /** 1806 * structure for free-ing device memory (used with the HL_MEM_OP_FREE op) 1807 * @handle: handle returned from HL_MEM_OP_ALLOC 1808 */ 1809 struct { 1810 __u64 handle; 1811 } free; 1812 1813 /** 1814 * structure for mapping device memory (used with the HL_MEM_OP_MAP op) 1815 * @hint_addr: requested virtual address of mapped memory. 1816 * the driver will try to map the requested region to this hint 1817 * address, as long as the address is valid and not already mapped. 1818 * the user should check the returned address of the IOCTL to make 1819 * sure he got the hint address. 1820 * passing 0 here means that the driver will choose the address itself. 1821 * @handle: handle returned from HL_MEM_OP_ALLOC. 1822 */ 1823 struct { 1824 __u64 hint_addr; 1825 __u64 handle; 1826 } map_device; 1827 1828 /** 1829 * structure for mapping host memory (used with the HL_MEM_OP_MAP op) 1830 * @host_virt_addr: address of allocated host memory. 1831 * @hint_addr: requested virtual address of mapped memory. 1832 * the driver will try to map the requested region to this hint 1833 * address, as long as the address is valid and not already mapped. 1834 * the user should check the returned address of the IOCTL to make 1835 * sure he got the hint address. 1836 * passing 0 here means that the driver will choose the address itself. 1837 * @size: size of allocated host memory. 1838 */ 1839 struct { 1840 __u64 host_virt_addr; 1841 __u64 hint_addr; 1842 __u64 mem_size; 1843 } map_host; 1844 1845 /** 1846 * structure for mapping hw block (used with the HL_MEM_OP_MAP_BLOCK op) 1847 * @block_addr:HW block address to map, a handle and size will be returned 1848 * to the user and will be used to mmap the relevant block. 1849 * only addresses from configuration space are allowed. 1850 */ 1851 struct { 1852 __u64 block_addr; 1853 } map_block; 1854 1855 /** 1856 * structure for unmapping host memory (used with the HL_MEM_OP_UNMAP op) 1857 * @device_virt_addr: virtual address returned from HL_MEM_OP_MAP 1858 */ 1859 struct { 1860 __u64 device_virt_addr; 1861 } unmap; 1862 1863 /** 1864 * structure for exporting DMABUF object (used with 1865 * the HL_MEM_OP_EXPORT_DMABUF_FD op) 1866 * @addr: for Gaudi1, the driver expects a physical address 1867 * inside the device's DRAM. this is because in Gaudi1 1868 * we don't have MMU that covers the device's DRAM. 1869 * for all other ASICs, the driver expects a device 1870 * virtual address that represents the start address of 1871 * a mapped DRAM memory area inside the device. 1872 * the address must be the same as was received from the 1873 * driver during a previous HL_MEM_OP_MAP operation. 1874 * @mem_size: size of memory to export. 1875 * @offset: for Gaudi1, this value must be 0. For all other ASICs, 1876 * the driver expects an offset inside of the memory area 1877 * describe by addr. the offset represents the start 1878 * address of that the exported dma-buf object describes. 1879 */ 1880 struct { 1881 __u64 addr; 1882 __u64 mem_size; 1883 __u64 offset; 1884 } export_dmabuf_fd; 1885 }; 1886 1887 __u32 op; 1888 __u32 flags; 1889 __u32 ctx_id; 1890 __u32 num_of_elements; 1891 }; 1892 1893 struct hl_mem_out { 1894 union { 1895 /* 1896 * Used for HL_MEM_OP_MAP as the virtual address that was 1897 * assigned in the device VA space. 1898 * A value of 0 means the requested operation failed. 1899 */ 1900 __u64 device_virt_addr; 1901 1902 /* 1903 * Used in HL_MEM_OP_ALLOC 1904 * This is the assigned handle for the allocated memory 1905 */ 1906 __u64 handle; 1907 1908 struct { 1909 /* 1910 * Used in HL_MEM_OP_MAP_BLOCK. 1911 * This is the assigned handle for the mapped block 1912 */ 1913 __u64 block_handle; 1914 1915 /* 1916 * Used in HL_MEM_OP_MAP_BLOCK 1917 * This is the size of the mapped block 1918 */ 1919 __u32 block_size; 1920 1921 __u32 pad; 1922 }; 1923 1924 /* Returned in HL_MEM_OP_EXPORT_DMABUF_FD. Represents the 1925 * DMA-BUF object that was created to describe a memory 1926 * allocation on the device's memory space. The FD should be 1927 * passed to the importer driver 1928 */ 1929 __s32 fd; 1930 }; 1931 }; 1932 1933 union hl_mem_args { 1934 struct hl_mem_in in; 1935 struct hl_mem_out out; 1936 }; 1937 1938 #define HL_DEBUG_MAX_AUX_VALUES 10 1939 1940 struct hl_debug_params_etr { 1941 /* Address in memory to allocate buffer */ 1942 __u64 buffer_address; 1943 1944 /* Size of buffer to allocate */ 1945 __u64 buffer_size; 1946 1947 /* Sink operation mode: SW fifo, HW fifo, Circular buffer */ 1948 __u32 sink_mode; 1949 __u32 pad; 1950 }; 1951 1952 struct hl_debug_params_etf { 1953 /* Address in memory to allocate buffer */ 1954 __u64 buffer_address; 1955 1956 /* Size of buffer to allocate */ 1957 __u64 buffer_size; 1958 1959 /* Sink operation mode: SW fifo, HW fifo, Circular buffer */ 1960 __u32 sink_mode; 1961 __u32 pad; 1962 }; 1963 1964 struct hl_debug_params_stm { 1965 /* Two bit masks for HW event and Stimulus Port */ 1966 __u64 he_mask; 1967 __u64 sp_mask; 1968 1969 /* Trace source ID */ 1970 __u32 id; 1971 1972 /* Frequency for the timestamp register */ 1973 __u32 frequency; 1974 }; 1975 1976 struct hl_debug_params_bmon { 1977 /* Two address ranges that the user can request to filter */ 1978 __u64 start_addr0; 1979 __u64 addr_mask0; 1980 1981 __u64 start_addr1; 1982 __u64 addr_mask1; 1983 1984 /* Capture window configuration */ 1985 __u32 bw_win; 1986 __u32 win_capture; 1987 1988 /* Trace source ID */ 1989 __u32 id; 1990 1991 /* Control register */ 1992 __u32 control; 1993 1994 /* Two more address ranges that the user can request to filter */ 1995 __u64 start_addr2; 1996 __u64 end_addr2; 1997 1998 __u64 start_addr3; 1999 __u64 end_addr3; 2000 }; 2001 2002 struct hl_debug_params_spmu { 2003 /* Event types selection */ 2004 __u64 event_types[HL_DEBUG_MAX_AUX_VALUES]; 2005 2006 /* Number of event types selection */ 2007 __u32 event_types_num; 2008 2009 /* TRC configuration register values */ 2010 __u32 pmtrc_val; 2011 __u32 trc_ctrl_host_val; 2012 __u32 trc_en_host_val; 2013 }; 2014 2015 /* Opcode for ETR component */ 2016 #define HL_DEBUG_OP_ETR 0 2017 /* Opcode for ETF component */ 2018 #define HL_DEBUG_OP_ETF 1 2019 /* Opcode for STM component */ 2020 #define HL_DEBUG_OP_STM 2 2021 /* Opcode for FUNNEL component */ 2022 #define HL_DEBUG_OP_FUNNEL 3 2023 /* Opcode for BMON component */ 2024 #define HL_DEBUG_OP_BMON 4 2025 /* Opcode for SPMU component */ 2026 #define HL_DEBUG_OP_SPMU 5 2027 /* Opcode for timestamp (deprecated) */ 2028 #define HL_DEBUG_OP_TIMESTAMP 6 2029 /* Opcode for setting the device into or out of debug mode. The enable 2030 * variable should be 1 for enabling debug mode and 0 for disabling it 2031 */ 2032 #define HL_DEBUG_OP_SET_MODE 7 2033 2034 struct hl_debug_args { 2035 /* 2036 * Pointer to user input structure. 2037 * This field is relevant to specific opcodes. 2038 */ 2039 __u64 input_ptr; 2040 /* Pointer to user output structure */ 2041 __u64 output_ptr; 2042 /* Size of user input structure */ 2043 __u32 input_size; 2044 /* Size of user output structure */ 2045 __u32 output_size; 2046 /* HL_DEBUG_OP_* */ 2047 __u32 op; 2048 /* 2049 * Register index in the component, taken from the debug_regs_index enum 2050 * in the various ASIC header files 2051 */ 2052 __u32 reg_idx; 2053 /* Enable/disable */ 2054 __u32 enable; 2055 /* Context ID - Currently not in use */ 2056 __u32 ctx_id; 2057 }; 2058 2059 /* 2060 * Various information operations such as: 2061 * - H/W IP information 2062 * - Current dram usage 2063 * 2064 * The user calls this IOCTL with an opcode that describes the required 2065 * information. The user should supply a pointer to a user-allocated memory 2066 * chunk, which will be filled by the driver with the requested information. 2067 * 2068 * The user supplies the maximum amount of size to copy into the user's memory, 2069 * in order to prevent data corruption in case of differences between the 2070 * definitions of structures in kernel and userspace, e.g. in case of old 2071 * userspace and new kernel driver 2072 */ 2073 #define HL_IOCTL_INFO \ 2074 _IOWR('H', 0x01, struct hl_info_args) 2075 2076 /* 2077 * Command Buffer 2078 * - Request a Command Buffer 2079 * - Destroy a Command Buffer 2080 * 2081 * The command buffers are memory blocks that reside in DMA-able address 2082 * space and are physically contiguous so they can be accessed by the device 2083 * directly. They are allocated using the coherent DMA API. 2084 * 2085 * When creating a new CB, the IOCTL returns a handle of it, and the user-space 2086 * process needs to use that handle to mmap the buffer so it can access them. 2087 * 2088 * In some instances, the device must access the command buffer through the 2089 * device's MMU, and thus its memory should be mapped. In these cases, user can 2090 * indicate the driver that such a mapping is required. 2091 * The resulting device virtual address will be used internally by the driver, 2092 * and won't be returned to user. 2093 * 2094 */ 2095 #define HL_IOCTL_CB \ 2096 _IOWR('H', 0x02, union hl_cb_args) 2097 2098 /* 2099 * Command Submission 2100 * 2101 * To submit work to the device, the user need to call this IOCTL with a set 2102 * of JOBS. That set of JOBS constitutes a CS object. 2103 * Each JOB will be enqueued on a specific queue, according to the user's input. 2104 * There can be more then one JOB per queue. 2105 * 2106 * The CS IOCTL will receive two sets of JOBS. One set is for "restore" phase 2107 * and a second set is for "execution" phase. 2108 * The JOBS on the "restore" phase are enqueued only after context-switch 2109 * (or if its the first CS for this context). The user can also order the 2110 * driver to run the "restore" phase explicitly 2111 * 2112 * Goya/Gaudi: 2113 * There are two types of queues - external and internal. External queues 2114 * are DMA queues which transfer data from/to the Host. All other queues are 2115 * internal. The driver will get completion notifications from the device only 2116 * on JOBS which are enqueued in the external queues. 2117 * 2118 * Greco onwards: 2119 * There is a single type of queue for all types of engines, either DMA engines 2120 * for transfers from/to the host or inside the device, or compute engines. 2121 * The driver will get completion notifications from the device for all queues. 2122 * 2123 * For jobs on external queues, the user needs to create command buffers 2124 * through the CB ioctl and give the CB's handle to the CS ioctl. For jobs on 2125 * internal queues, the user needs to prepare a "command buffer" with packets 2126 * on either the device SRAM/DRAM or the host, and give the device address of 2127 * that buffer to the CS ioctl. 2128 * For jobs on H/W queues both options of command buffers are valid. 2129 * 2130 * This IOCTL is asynchronous in regard to the actual execution of the CS. This 2131 * means it returns immediately after ALL the JOBS were enqueued on their 2132 * relevant queues. Therefore, the user mustn't assume the CS has been completed 2133 * or has even started to execute. 2134 * 2135 * Upon successful enqueue, the IOCTL returns a sequence number which the user 2136 * can use with the "Wait for CS" IOCTL to check whether the handle's CS 2137 * non-internal JOBS have been completed. Note that if the CS has internal JOBS 2138 * which can execute AFTER the external JOBS have finished, the driver might 2139 * report that the CS has finished executing BEFORE the internal JOBS have 2140 * actually finished executing. 2141 * 2142 * Even though the sequence number increments per CS, the user can NOT 2143 * automatically assume that if CS with sequence number N finished, then CS 2144 * with sequence number N-1 also finished. The user can make this assumption if 2145 * and only if CS N and CS N-1 are exactly the same (same CBs for the same 2146 * queues). 2147 */ 2148 #define HL_IOCTL_CS \ 2149 _IOWR('H', 0x03, union hl_cs_args) 2150 2151 /* 2152 * Wait for Command Submission 2153 * 2154 * The user can call this IOCTL with a handle it received from the CS IOCTL 2155 * to wait until the handle's CS has finished executing. The user will wait 2156 * inside the kernel until the CS has finished or until the user-requested 2157 * timeout has expired. 2158 * 2159 * If the timeout value is 0, the driver won't sleep at all. It will check 2160 * the status of the CS and return immediately 2161 * 2162 * The return value of the IOCTL is a standard Linux error code. The possible 2163 * values are: 2164 * 2165 * EINTR - Kernel waiting has been interrupted, e.g. due to OS signal 2166 * that the user process received 2167 * ETIMEDOUT - The CS has caused a timeout on the device 2168 * EIO - The CS was aborted (usually because the device was reset) 2169 * ENODEV - The device wants to do hard-reset (so user need to close FD) 2170 * 2171 * The driver also returns a custom define in case the IOCTL call returned 0. 2172 * The define can be one of the following: 2173 * 2174 * HL_WAIT_CS_STATUS_COMPLETED - The CS has been completed successfully (0) 2175 * HL_WAIT_CS_STATUS_BUSY - The CS is still executing (0) 2176 * HL_WAIT_CS_STATUS_TIMEDOUT - The CS has caused a timeout on the device 2177 * (ETIMEDOUT) 2178 * HL_WAIT_CS_STATUS_ABORTED - The CS was aborted, usually because the 2179 * device was reset (EIO) 2180 */ 2181 2182 #define HL_IOCTL_WAIT_CS \ 2183 _IOWR('H', 0x04, union hl_wait_cs_args) 2184 2185 /* 2186 * Memory 2187 * - Map host memory to device MMU 2188 * - Unmap host memory from device MMU 2189 * 2190 * This IOCTL allows the user to map host memory to the device MMU 2191 * 2192 * For host memory, the IOCTL doesn't allocate memory. The user is supposed 2193 * to allocate the memory in user-space (malloc/new). The driver pins the 2194 * physical pages (up to the allowed limit by the OS), assigns a virtual 2195 * address in the device VA space and initializes the device MMU. 2196 * 2197 * There is an option for the user to specify the requested virtual address. 2198 * 2199 */ 2200 #define HL_IOCTL_MEMORY \ 2201 _IOWR('H', 0x05, union hl_mem_args) 2202 2203 /* 2204 * Debug 2205 * - Enable/disable the ETR/ETF/FUNNEL/STM/BMON/SPMU debug traces 2206 * 2207 * This IOCTL allows the user to get debug traces from the chip. 2208 * 2209 * Before the user can send configuration requests of the various 2210 * debug/profile engines, it needs to set the device into debug mode. 2211 * This is because the debug/profile infrastructure is shared component in the 2212 * device and we can't allow multiple users to access it at the same time. 2213 * 2214 * Once a user set the device into debug mode, the driver won't allow other 2215 * users to "work" with the device, i.e. open a FD. If there are multiple users 2216 * opened on the device, the driver won't allow any user to debug the device. 2217 * 2218 * For each configuration request, the user needs to provide the register index 2219 * and essential data such as buffer address and size. 2220 * 2221 * Once the user has finished using the debug/profile engines, he should 2222 * set the device into non-debug mode, i.e. disable debug mode. 2223 * 2224 * The driver can decide to "kick out" the user if he abuses this interface. 2225 * 2226 */ 2227 #define HL_IOCTL_DEBUG \ 2228 _IOWR('H', 0x06, struct hl_debug_args) 2229 2230 #define HL_COMMAND_START 0x01 2231 #define HL_COMMAND_END 0x07 2232 2233 #endif /* HABANALABS_H_ */ 2234