1 /* exynos_drm.h 2 * 3 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 4 * Authors: 5 * Inki Dae <inki.dae@samsung.com> 6 * Joonyoung Shim <jy0922.shim@samsung.com> 7 * Seung-Woo Kim <sw0312.kim@samsung.com> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 */ 14 15 #ifndef _UAPI_EXYNOS_DRM_H_ 16 #define _UAPI_EXYNOS_DRM_H_ 17 18 #include "drm.h" 19 20 /** 21 * User-desired buffer creation information structure. 22 * 23 * @size: user-desired memory allocation size. 24 * - this size value would be page-aligned internally. 25 * @flags: user request for setting memory type or cache attributes. 26 * @handle: returned a handle to created gem object. 27 * - this handle will be set by gem module of kernel side. 28 */ 29 struct drm_exynos_gem_create { 30 __u64 size; 31 __u32 flags; 32 __u32 handle; 33 }; 34 35 /** 36 * A structure for getting a fake-offset that can be used with mmap. 37 * 38 * @handle: handle of gem object. 39 * @reserved: just padding to be 64-bit aligned. 40 * @offset: a fake-offset of gem object. 41 */ 42 struct drm_exynos_gem_map { 43 __u32 handle; 44 __u32 reserved; 45 __u64 offset; 46 }; 47 48 /** 49 * A structure to gem information. 50 * 51 * @handle: a handle to gem object created. 52 * @flags: flag value including memory type and cache attribute and 53 * this value would be set by driver. 54 * @size: size to memory region allocated by gem and this size would 55 * be set by driver. 56 */ 57 struct drm_exynos_gem_info { 58 __u32 handle; 59 __u32 flags; 60 __u64 size; 61 }; 62 63 /** 64 * A structure for user connection request of virtual display. 65 * 66 * @connection: indicate whether doing connetion or not by user. 67 * @extensions: if this value is 1 then the vidi driver would need additional 68 * 128bytes edid data. 69 * @edid: the edid data pointer from user side. 70 */ 71 struct drm_exynos_vidi_connection { 72 __u32 connection; 73 __u32 extensions; 74 __u64 edid; 75 }; 76 77 /* memory type definitions. */ 78 enum e_drm_exynos_gem_mem_type { 79 /* Physically Continuous memory and used as default. */ 80 EXYNOS_BO_CONTIG = 0 << 0, 81 /* Physically Non-Continuous memory. */ 82 EXYNOS_BO_NONCONTIG = 1 << 0, 83 /* non-cachable mapping and used as default. */ 84 EXYNOS_BO_NONCACHABLE = 0 << 1, 85 /* cachable mapping. */ 86 EXYNOS_BO_CACHABLE = 1 << 1, 87 /* write-combine mapping. */ 88 EXYNOS_BO_WC = 1 << 2, 89 EXYNOS_BO_MASK = EXYNOS_BO_NONCONTIG | EXYNOS_BO_CACHABLE | 90 EXYNOS_BO_WC 91 }; 92 93 struct drm_exynos_g2d_get_ver { 94 __u32 major; 95 __u32 minor; 96 }; 97 98 struct drm_exynos_g2d_cmd { 99 __u32 offset; 100 __u32 data; 101 }; 102 103 enum drm_exynos_g2d_buf_type { 104 G2D_BUF_USERPTR = 1 << 31, 105 }; 106 107 enum drm_exynos_g2d_event_type { 108 G2D_EVENT_NOT, 109 G2D_EVENT_NONSTOP, 110 G2D_EVENT_STOP, /* not yet */ 111 }; 112 113 struct drm_exynos_g2d_userptr { 114 unsigned long userptr; 115 unsigned long size; 116 }; 117 118 struct drm_exynos_g2d_set_cmdlist { 119 __u64 cmd; 120 __u64 cmd_buf; 121 __u32 cmd_nr; 122 __u32 cmd_buf_nr; 123 124 /* for g2d event */ 125 __u64 event_type; 126 __u64 user_data; 127 }; 128 129 struct drm_exynos_g2d_exec { 130 __u64 async; 131 }; 132 133 enum drm_exynos_ops_id { 134 EXYNOS_DRM_OPS_SRC, 135 EXYNOS_DRM_OPS_DST, 136 EXYNOS_DRM_OPS_MAX, 137 }; 138 139 struct drm_exynos_sz { 140 __u32 hsize; 141 __u32 vsize; 142 }; 143 144 struct drm_exynos_pos { 145 __u32 x; 146 __u32 y; 147 __u32 w; 148 __u32 h; 149 }; 150 151 enum drm_exynos_flip { 152 EXYNOS_DRM_FLIP_NONE = (0 << 0), 153 EXYNOS_DRM_FLIP_VERTICAL = (1 << 0), 154 EXYNOS_DRM_FLIP_HORIZONTAL = (1 << 1), 155 EXYNOS_DRM_FLIP_BOTH = EXYNOS_DRM_FLIP_VERTICAL | 156 EXYNOS_DRM_FLIP_HORIZONTAL, 157 }; 158 159 enum drm_exynos_degree { 160 EXYNOS_DRM_DEGREE_0, 161 EXYNOS_DRM_DEGREE_90, 162 EXYNOS_DRM_DEGREE_180, 163 EXYNOS_DRM_DEGREE_270, 164 }; 165 166 enum drm_exynos_planer { 167 EXYNOS_DRM_PLANAR_Y, 168 EXYNOS_DRM_PLANAR_CB, 169 EXYNOS_DRM_PLANAR_CR, 170 EXYNOS_DRM_PLANAR_MAX, 171 }; 172 173 /** 174 * A structure for ipp supported property list. 175 * 176 * @version: version of this structure. 177 * @ipp_id: id of ipp driver. 178 * @count: count of ipp driver. 179 * @writeback: flag of writeback supporting. 180 * @flip: flag of flip supporting. 181 * @degree: flag of degree information. 182 * @csc: flag of csc supporting. 183 * @crop: flag of crop supporting. 184 * @scale: flag of scale supporting. 185 * @refresh_min: min hz of refresh. 186 * @refresh_max: max hz of refresh. 187 * @crop_min: crop min resolution. 188 * @crop_max: crop max resolution. 189 * @scale_min: scale min resolution. 190 * @scale_max: scale max resolution. 191 */ 192 struct drm_exynos_ipp_prop_list { 193 __u32 version; 194 __u32 ipp_id; 195 __u32 count; 196 __u32 writeback; 197 __u32 flip; 198 __u32 degree; 199 __u32 csc; 200 __u32 crop; 201 __u32 scale; 202 __u32 refresh_min; 203 __u32 refresh_max; 204 __u32 reserved; 205 struct drm_exynos_sz crop_min; 206 struct drm_exynos_sz crop_max; 207 struct drm_exynos_sz scale_min; 208 struct drm_exynos_sz scale_max; 209 }; 210 211 /** 212 * A structure for ipp config. 213 * 214 * @ops_id: property of operation directions. 215 * @flip: property of mirror, flip. 216 * @degree: property of rotation degree. 217 * @fmt: property of image format. 218 * @sz: property of image size. 219 * @pos: property of image position(src-cropped,dst-scaler). 220 */ 221 struct drm_exynos_ipp_config { 222 __u32 ops_id; 223 __u32 flip; 224 __u32 degree; 225 __u32 fmt; 226 struct drm_exynos_sz sz; 227 struct drm_exynos_pos pos; 228 }; 229 230 enum drm_exynos_ipp_cmd { 231 IPP_CMD_NONE, 232 IPP_CMD_M2M, 233 IPP_CMD_WB, 234 IPP_CMD_OUTPUT, 235 IPP_CMD_MAX, 236 }; 237 238 /** 239 * A structure for ipp property. 240 * 241 * @config: source, destination config. 242 * @cmd: definition of command. 243 * @ipp_id: id of ipp driver. 244 * @prop_id: id of property. 245 * @refresh_rate: refresh rate. 246 */ 247 struct drm_exynos_ipp_property { 248 struct drm_exynos_ipp_config config[EXYNOS_DRM_OPS_MAX]; 249 __u32 cmd; 250 __u32 ipp_id; 251 __u32 prop_id; 252 __u32 refresh_rate; 253 }; 254 255 enum drm_exynos_ipp_buf_type { 256 IPP_BUF_ENQUEUE, 257 IPP_BUF_DEQUEUE, 258 }; 259 260 /** 261 * A structure for ipp buffer operations. 262 * 263 * @ops_id: operation directions. 264 * @buf_type: definition of buffer. 265 * @prop_id: id of property. 266 * @buf_id: id of buffer. 267 * @handle: Y, Cb, Cr each planar handle. 268 * @user_data: user data. 269 */ 270 struct drm_exynos_ipp_queue_buf { 271 __u32 ops_id; 272 __u32 buf_type; 273 __u32 prop_id; 274 __u32 buf_id; 275 __u32 handle[EXYNOS_DRM_PLANAR_MAX]; 276 __u32 reserved; 277 __u64 user_data; 278 }; 279 280 enum drm_exynos_ipp_ctrl { 281 IPP_CTRL_PLAY, 282 IPP_CTRL_STOP, 283 IPP_CTRL_PAUSE, 284 IPP_CTRL_RESUME, 285 IPP_CTRL_MAX, 286 }; 287 288 /** 289 * A structure for ipp start/stop operations. 290 * 291 * @prop_id: id of property. 292 * @ctrl: definition of control. 293 */ 294 struct drm_exynos_ipp_cmd_ctrl { 295 __u32 prop_id; 296 __u32 ctrl; 297 }; 298 299 #define DRM_EXYNOS_GEM_CREATE 0x00 300 #define DRM_EXYNOS_GEM_MAP 0x01 301 /* Reserved 0x03 ~ 0x05 for exynos specific gem ioctl */ 302 #define DRM_EXYNOS_GEM_GET 0x04 303 #define DRM_EXYNOS_VIDI_CONNECTION 0x07 304 305 /* G2D */ 306 #define DRM_EXYNOS_G2D_GET_VER 0x20 307 #define DRM_EXYNOS_G2D_SET_CMDLIST 0x21 308 #define DRM_EXYNOS_G2D_EXEC 0x22 309 310 /* IPP - Image Post Processing */ 311 #define DRM_EXYNOS_IPP_GET_PROPERTY 0x30 312 #define DRM_EXYNOS_IPP_SET_PROPERTY 0x31 313 #define DRM_EXYNOS_IPP_QUEUE_BUF 0x32 314 #define DRM_EXYNOS_IPP_CMD_CTRL 0x33 315 316 #define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \ 317 DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create) 318 #define DRM_IOCTL_EXYNOS_GEM_MAP DRM_IOWR(DRM_COMMAND_BASE + \ 319 DRM_EXYNOS_GEM_MAP, struct drm_exynos_gem_map) 320 #define DRM_IOCTL_EXYNOS_GEM_GET DRM_IOWR(DRM_COMMAND_BASE + \ 321 DRM_EXYNOS_GEM_GET, struct drm_exynos_gem_info) 322 323 #define DRM_IOCTL_EXYNOS_VIDI_CONNECTION DRM_IOWR(DRM_COMMAND_BASE + \ 324 DRM_EXYNOS_VIDI_CONNECTION, struct drm_exynos_vidi_connection) 325 326 #define DRM_IOCTL_EXYNOS_G2D_GET_VER DRM_IOWR(DRM_COMMAND_BASE + \ 327 DRM_EXYNOS_G2D_GET_VER, struct drm_exynos_g2d_get_ver) 328 #define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST DRM_IOWR(DRM_COMMAND_BASE + \ 329 DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist) 330 #define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + \ 331 DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec) 332 333 #define DRM_IOCTL_EXYNOS_IPP_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + \ 334 DRM_EXYNOS_IPP_GET_PROPERTY, struct drm_exynos_ipp_prop_list) 335 #define DRM_IOCTL_EXYNOS_IPP_SET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + \ 336 DRM_EXYNOS_IPP_SET_PROPERTY, struct drm_exynos_ipp_property) 337 #define DRM_IOCTL_EXYNOS_IPP_QUEUE_BUF DRM_IOWR(DRM_COMMAND_BASE + \ 338 DRM_EXYNOS_IPP_QUEUE_BUF, struct drm_exynos_ipp_queue_buf) 339 #define DRM_IOCTL_EXYNOS_IPP_CMD_CTRL DRM_IOWR(DRM_COMMAND_BASE + \ 340 DRM_EXYNOS_IPP_CMD_CTRL, struct drm_exynos_ipp_cmd_ctrl) 341 342 /* EXYNOS specific events */ 343 #define DRM_EXYNOS_G2D_EVENT 0x80000000 344 #define DRM_EXYNOS_IPP_EVENT 0x80000001 345 346 struct drm_exynos_g2d_event { 347 struct drm_event base; 348 __u64 user_data; 349 __u32 tv_sec; 350 __u32 tv_usec; 351 __u32 cmdlist_no; 352 __u32 reserved; 353 }; 354 355 struct drm_exynos_ipp_event { 356 struct drm_event base; 357 __u64 user_data; 358 __u32 tv_sec; 359 __u32 tv_usec; 360 __u32 prop_id; 361 __u32 reserved; 362 __u32 buf_id[EXYNOS_DRM_OPS_MAX]; 363 }; 364 365 #endif /* _UAPI_EXYNOS_DRM_H_ */ 366