1 /* exynos_drm.h 2 * 3 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 4 * Authors: 5 * Inki Dae <inki.dae@samsung.com> 6 * Joonyoung Shim <jy0922.shim@samsung.com> 7 * Seung-Woo Kim <sw0312.kim@samsung.com> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 */ 14 15 #ifndef _UAPI_EXYNOS_DRM_H_ 16 #define _UAPI_EXYNOS_DRM_H_ 17 18 #include <drm/drm.h> 19 20 /** 21 * User-desired buffer creation information structure. 22 * 23 * @size: user-desired memory allocation size. 24 * - this size value would be page-aligned internally. 25 * @flags: user request for setting memory type or cache attributes. 26 * @handle: returned a handle to created gem object. 27 * - this handle will be set by gem module of kernel side. 28 */ 29 struct drm_exynos_gem_create { 30 uint64_t size; 31 unsigned int flags; 32 unsigned int handle; 33 }; 34 35 /** 36 * A structure for getting buffer offset. 37 * 38 * @handle: a pointer to gem object created. 39 * @pad: just padding to be 64-bit aligned. 40 * @offset: relatived offset value of the memory region allocated. 41 * - this value should be set by user. 42 */ 43 struct drm_exynos_gem_map_off { 44 unsigned int handle; 45 unsigned int pad; 46 uint64_t offset; 47 }; 48 49 /** 50 * A structure for mapping buffer. 51 * 52 * @handle: a handle to gem object created. 53 * @pad: just padding to be 64-bit aligned. 54 * @size: memory size to be mapped. 55 * @mapped: having user virtual address mmaped. 56 * - this variable would be filled by exynos gem module 57 * of kernel side with user virtual address which is allocated 58 * by do_mmap(). 59 */ 60 struct drm_exynos_gem_mmap { 61 unsigned int handle; 62 unsigned int pad; 63 uint64_t size; 64 uint64_t mapped; 65 }; 66 67 /** 68 * A structure to gem information. 69 * 70 * @handle: a handle to gem object created. 71 * @flags: flag value including memory type and cache attribute and 72 * this value would be set by driver. 73 * @size: size to memory region allocated by gem and this size would 74 * be set by driver. 75 */ 76 struct drm_exynos_gem_info { 77 unsigned int handle; 78 unsigned int flags; 79 uint64_t size; 80 }; 81 82 /** 83 * A structure for user connection request of virtual display. 84 * 85 * @connection: indicate whether doing connetion or not by user. 86 * @extensions: if this value is 1 then the vidi driver would need additional 87 * 128bytes edid data. 88 * @edid: the edid data pointer from user side. 89 */ 90 struct drm_exynos_vidi_connection { 91 unsigned int connection; 92 unsigned int extensions; 93 uint64_t edid; 94 }; 95 96 /* memory type definitions. */ 97 enum e_drm_exynos_gem_mem_type { 98 /* Physically Continuous memory and used as default. */ 99 EXYNOS_BO_CONTIG = 0 << 0, 100 /* Physically Non-Continuous memory. */ 101 EXYNOS_BO_NONCONTIG = 1 << 0, 102 /* non-cachable mapping and used as default. */ 103 EXYNOS_BO_NONCACHABLE = 0 << 1, 104 /* cachable mapping. */ 105 EXYNOS_BO_CACHABLE = 1 << 1, 106 /* write-combine mapping. */ 107 EXYNOS_BO_WC = 1 << 2, 108 EXYNOS_BO_MASK = EXYNOS_BO_NONCONTIG | EXYNOS_BO_CACHABLE | 109 EXYNOS_BO_WC 110 }; 111 112 struct drm_exynos_g2d_get_ver { 113 __u32 major; 114 __u32 minor; 115 }; 116 117 struct drm_exynos_g2d_cmd { 118 __u32 offset; 119 __u32 data; 120 }; 121 122 enum drm_exynos_g2d_buf_type { 123 G2D_BUF_USERPTR = 1 << 31, 124 }; 125 126 enum drm_exynos_g2d_event_type { 127 G2D_EVENT_NOT, 128 G2D_EVENT_NONSTOP, 129 G2D_EVENT_STOP, /* not yet */ 130 }; 131 132 struct drm_exynos_g2d_userptr { 133 unsigned long userptr; 134 unsigned long size; 135 }; 136 137 struct drm_exynos_g2d_set_cmdlist { 138 __u64 cmd; 139 __u64 cmd_buf; 140 __u32 cmd_nr; 141 __u32 cmd_buf_nr; 142 143 /* for g2d event */ 144 __u64 event_type; 145 __u64 user_data; 146 }; 147 148 struct drm_exynos_g2d_exec { 149 __u64 async; 150 }; 151 152 enum drm_exynos_ops_id { 153 EXYNOS_DRM_OPS_SRC, 154 EXYNOS_DRM_OPS_DST, 155 EXYNOS_DRM_OPS_MAX, 156 }; 157 158 struct drm_exynos_sz { 159 __u32 hsize; 160 __u32 vsize; 161 }; 162 163 struct drm_exynos_pos { 164 __u32 x; 165 __u32 y; 166 __u32 w; 167 __u32 h; 168 }; 169 170 enum drm_exynos_flip { 171 EXYNOS_DRM_FLIP_NONE = (0 << 0), 172 EXYNOS_DRM_FLIP_VERTICAL = (1 << 0), 173 EXYNOS_DRM_FLIP_HORIZONTAL = (1 << 1), 174 EXYNOS_DRM_FLIP_BOTH = EXYNOS_DRM_FLIP_VERTICAL | 175 EXYNOS_DRM_FLIP_HORIZONTAL, 176 }; 177 178 enum drm_exynos_degree { 179 EXYNOS_DRM_DEGREE_0, 180 EXYNOS_DRM_DEGREE_90, 181 EXYNOS_DRM_DEGREE_180, 182 EXYNOS_DRM_DEGREE_270, 183 }; 184 185 enum drm_exynos_planer { 186 EXYNOS_DRM_PLANAR_Y, 187 EXYNOS_DRM_PLANAR_CB, 188 EXYNOS_DRM_PLANAR_CR, 189 EXYNOS_DRM_PLANAR_MAX, 190 }; 191 192 /** 193 * A structure for ipp supported property list. 194 * 195 * @version: version of this structure. 196 * @ipp_id: id of ipp driver. 197 * @count: count of ipp driver. 198 * @writeback: flag of writeback supporting. 199 * @flip: flag of flip supporting. 200 * @degree: flag of degree information. 201 * @csc: flag of csc supporting. 202 * @crop: flag of crop supporting. 203 * @scale: flag of scale supporting. 204 * @refresh_min: min hz of refresh. 205 * @refresh_max: max hz of refresh. 206 * @crop_min: crop min resolution. 207 * @crop_max: crop max resolution. 208 * @scale_min: scale min resolution. 209 * @scale_max: scale max resolution. 210 */ 211 struct drm_exynos_ipp_prop_list { 212 __u32 version; 213 __u32 ipp_id; 214 __u32 count; 215 __u32 writeback; 216 __u32 flip; 217 __u32 degree; 218 __u32 csc; 219 __u32 crop; 220 __u32 scale; 221 __u32 refresh_min; 222 __u32 refresh_max; 223 __u32 reserved; 224 struct drm_exynos_sz crop_min; 225 struct drm_exynos_sz crop_max; 226 struct drm_exynos_sz scale_min; 227 struct drm_exynos_sz scale_max; 228 }; 229 230 /** 231 * A structure for ipp config. 232 * 233 * @ops_id: property of operation directions. 234 * @flip: property of mirror, flip. 235 * @degree: property of rotation degree. 236 * @fmt: property of image format. 237 * @sz: property of image size. 238 * @pos: property of image position(src-cropped,dst-scaler). 239 */ 240 struct drm_exynos_ipp_config { 241 enum drm_exynos_ops_id ops_id; 242 enum drm_exynos_flip flip; 243 enum drm_exynos_degree degree; 244 __u32 fmt; 245 struct drm_exynos_sz sz; 246 struct drm_exynos_pos pos; 247 }; 248 249 enum drm_exynos_ipp_cmd { 250 IPP_CMD_NONE, 251 IPP_CMD_M2M, 252 IPP_CMD_WB, 253 IPP_CMD_OUTPUT, 254 IPP_CMD_MAX, 255 }; 256 257 /** 258 * A structure for ipp property. 259 * 260 * @config: source, destination config. 261 * @cmd: definition of command. 262 * @ipp_id: id of ipp driver. 263 * @prop_id: id of property. 264 * @refresh_rate: refresh rate. 265 */ 266 struct drm_exynos_ipp_property { 267 struct drm_exynos_ipp_config config[EXYNOS_DRM_OPS_MAX]; 268 enum drm_exynos_ipp_cmd cmd; 269 __u32 ipp_id; 270 __u32 prop_id; 271 __u32 refresh_rate; 272 }; 273 274 enum drm_exynos_ipp_buf_type { 275 IPP_BUF_ENQUEUE, 276 IPP_BUF_DEQUEUE, 277 }; 278 279 /** 280 * A structure for ipp buffer operations. 281 * 282 * @ops_id: operation directions. 283 * @buf_type: definition of buffer. 284 * @prop_id: id of property. 285 * @buf_id: id of buffer. 286 * @handle: Y, Cb, Cr each planar handle. 287 * @user_data: user data. 288 */ 289 struct drm_exynos_ipp_queue_buf { 290 enum drm_exynos_ops_id ops_id; 291 enum drm_exynos_ipp_buf_type buf_type; 292 __u32 prop_id; 293 __u32 buf_id; 294 __u32 handle[EXYNOS_DRM_PLANAR_MAX]; 295 __u32 reserved; 296 __u64 user_data; 297 }; 298 299 enum drm_exynos_ipp_ctrl { 300 IPP_CTRL_PLAY, 301 IPP_CTRL_STOP, 302 IPP_CTRL_PAUSE, 303 IPP_CTRL_RESUME, 304 IPP_CTRL_MAX, 305 }; 306 307 /** 308 * A structure for ipp start/stop operations. 309 * 310 * @prop_id: id of property. 311 * @ctrl: definition of control. 312 */ 313 struct drm_exynos_ipp_cmd_ctrl { 314 __u32 prop_id; 315 enum drm_exynos_ipp_ctrl ctrl; 316 }; 317 318 #define DRM_EXYNOS_GEM_CREATE 0x00 319 #define DRM_EXYNOS_GEM_MAP_OFFSET 0x01 320 #define DRM_EXYNOS_GEM_MMAP 0x02 321 /* Reserved 0x03 ~ 0x05 for exynos specific gem ioctl */ 322 #define DRM_EXYNOS_GEM_GET 0x04 323 #define DRM_EXYNOS_VIDI_CONNECTION 0x07 324 325 /* G2D */ 326 #define DRM_EXYNOS_G2D_GET_VER 0x20 327 #define DRM_EXYNOS_G2D_SET_CMDLIST 0x21 328 #define DRM_EXYNOS_G2D_EXEC 0x22 329 330 /* IPP - Image Post Processing */ 331 #define DRM_EXYNOS_IPP_GET_PROPERTY 0x30 332 #define DRM_EXYNOS_IPP_SET_PROPERTY 0x31 333 #define DRM_EXYNOS_IPP_QUEUE_BUF 0x32 334 #define DRM_EXYNOS_IPP_CMD_CTRL 0x33 335 336 #define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \ 337 DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create) 338 339 #define DRM_IOCTL_EXYNOS_GEM_MAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + \ 340 DRM_EXYNOS_GEM_MAP_OFFSET, struct drm_exynos_gem_map_off) 341 342 #define DRM_IOCTL_EXYNOS_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + \ 343 DRM_EXYNOS_GEM_MMAP, struct drm_exynos_gem_mmap) 344 345 #define DRM_IOCTL_EXYNOS_GEM_GET DRM_IOWR(DRM_COMMAND_BASE + \ 346 DRM_EXYNOS_GEM_GET, struct drm_exynos_gem_info) 347 348 #define DRM_IOCTL_EXYNOS_VIDI_CONNECTION DRM_IOWR(DRM_COMMAND_BASE + \ 349 DRM_EXYNOS_VIDI_CONNECTION, struct drm_exynos_vidi_connection) 350 351 #define DRM_IOCTL_EXYNOS_G2D_GET_VER DRM_IOWR(DRM_COMMAND_BASE + \ 352 DRM_EXYNOS_G2D_GET_VER, struct drm_exynos_g2d_get_ver) 353 #define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST DRM_IOWR(DRM_COMMAND_BASE + \ 354 DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist) 355 #define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + \ 356 DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec) 357 358 #define DRM_IOCTL_EXYNOS_IPP_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + \ 359 DRM_EXYNOS_IPP_GET_PROPERTY, struct drm_exynos_ipp_prop_list) 360 #define DRM_IOCTL_EXYNOS_IPP_SET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + \ 361 DRM_EXYNOS_IPP_SET_PROPERTY, struct drm_exynos_ipp_property) 362 #define DRM_IOCTL_EXYNOS_IPP_QUEUE_BUF DRM_IOWR(DRM_COMMAND_BASE + \ 363 DRM_EXYNOS_IPP_QUEUE_BUF, struct drm_exynos_ipp_queue_buf) 364 #define DRM_IOCTL_EXYNOS_IPP_CMD_CTRL DRM_IOWR(DRM_COMMAND_BASE + \ 365 DRM_EXYNOS_IPP_CMD_CTRL, struct drm_exynos_ipp_cmd_ctrl) 366 367 /* EXYNOS specific events */ 368 #define DRM_EXYNOS_G2D_EVENT 0x80000000 369 #define DRM_EXYNOS_IPP_EVENT 0x80000001 370 371 struct drm_exynos_g2d_event { 372 struct drm_event base; 373 __u64 user_data; 374 __u32 tv_sec; 375 __u32 tv_usec; 376 __u32 cmdlist_no; 377 __u32 reserved; 378 }; 379 380 struct drm_exynos_ipp_event { 381 struct drm_event base; 382 __u64 user_data; 383 __u32 tv_sec; 384 __u32 tv_usec; 385 __u32 prop_id; 386 __u32 reserved; 387 __u32 buf_id[EXYNOS_DRM_OPS_MAX]; 388 }; 389 390 #endif /* _UAPI_EXYNOS_DRM_H_ */ 391