1 /* 2 * Copyright (C) 2015 Etnaviv Project 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License version 2 as published by 6 * the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #ifndef __ETNAVIV_DRM_H__ 18 #define __ETNAVIV_DRM_H__ 19 20 #include "drm.h" 21 22 /* Please note that modifications to all structs defined here are 23 * subject to backwards-compatibility constraints: 24 * 1) Do not use pointers, use __u64 instead for 32 bit / 64 bit 25 * user/kernel compatibility 26 * 2) Keep fields aligned to their size 27 * 3) Because of how drm_ioctl() works, we can add new fields at 28 * the end of an ioctl if some care is taken: drm_ioctl() will 29 * zero out the new fields at the tail of the ioctl, so a zero 30 * value should have a backwards compatible meaning. And for 31 * output params, userspace won't see the newly added output 32 * fields.. so that has to be somehow ok. 33 */ 34 35 /* timeouts are specified in clock-monotonic absolute times (to simplify 36 * restarting interrupted ioctls). The following struct is logically the 37 * same as 'struct timespec' but 32/64b ABI safe. 38 */ 39 struct drm_etnaviv_timespec { 40 __s64 tv_sec; /* seconds */ 41 __s64 tv_nsec; /* nanoseconds */ 42 }; 43 44 #define ETNAVIV_PARAM_GPU_MODEL 0x01 45 #define ETNAVIV_PARAM_GPU_REVISION 0x02 46 #define ETNAVIV_PARAM_GPU_FEATURES_0 0x03 47 #define ETNAVIV_PARAM_GPU_FEATURES_1 0x04 48 #define ETNAVIV_PARAM_GPU_FEATURES_2 0x05 49 #define ETNAVIV_PARAM_GPU_FEATURES_3 0x06 50 #define ETNAVIV_PARAM_GPU_FEATURES_4 0x07 51 52 #define ETNAVIV_PARAM_GPU_STREAM_COUNT 0x10 53 #define ETNAVIV_PARAM_GPU_REGISTER_MAX 0x11 54 #define ETNAVIV_PARAM_GPU_THREAD_COUNT 0x12 55 #define ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE 0x13 56 #define ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT 0x14 57 #define ETNAVIV_PARAM_GPU_PIXEL_PIPES 0x15 58 #define ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE 0x16 59 #define ETNAVIV_PARAM_GPU_BUFFER_SIZE 0x17 60 #define ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT 0x18 61 #define ETNAVIV_PARAM_GPU_NUM_CONSTANTS 0x19 62 63 #define ETNA_MAX_PIPES 4 64 65 struct drm_etnaviv_param { 66 __u32 pipe; /* in */ 67 __u32 param; /* in, ETNAVIV_PARAM_x */ 68 __u64 value; /* out (get_param) or in (set_param) */ 69 }; 70 71 /* 72 * GEM buffers: 73 */ 74 75 #define ETNA_BO_CACHE_MASK 0x000f0000 76 /* cache modes */ 77 #define ETNA_BO_CACHED 0x00010000 78 #define ETNA_BO_WC 0x00020000 79 #define ETNA_BO_UNCACHED 0x00040000 80 /* map flags */ 81 #define ETNA_BO_FORCE_MMU 0x00100000 82 83 struct drm_etnaviv_gem_new { 84 __u64 size; /* in */ 85 __u32 flags; /* in, mask of ETNA_BO_x */ 86 __u32 handle; /* out */ 87 }; 88 89 struct drm_etnaviv_gem_info { 90 __u32 handle; /* in */ 91 __u32 pad; 92 __u64 offset; /* out, offset to pass to mmap() */ 93 }; 94 95 #define ETNA_PREP_READ 0x01 96 #define ETNA_PREP_WRITE 0x02 97 #define ETNA_PREP_NOSYNC 0x04 98 99 struct drm_etnaviv_gem_cpu_prep { 100 __u32 handle; /* in */ 101 __u32 op; /* in, mask of ETNA_PREP_x */ 102 struct drm_etnaviv_timespec timeout; /* in */ 103 }; 104 105 struct drm_etnaviv_gem_cpu_fini { 106 __u32 handle; /* in */ 107 __u32 flags; /* in, placeholder for now, no defined values */ 108 }; 109 110 /* 111 * Cmdstream Submission: 112 */ 113 114 /* The value written into the cmdstream is logically: 115 * relocbuf->gpuaddr + reloc_offset 116 * 117 * NOTE that reloc's must be sorted by order of increasing submit_offset, 118 * otherwise EINVAL. 119 */ 120 struct drm_etnaviv_gem_submit_reloc { 121 __u32 submit_offset; /* in, offset from submit_bo */ 122 __u32 reloc_idx; /* in, index of reloc_bo buffer */ 123 __u64 reloc_offset; /* in, offset from start of reloc_bo */ 124 __u32 flags; /* in, placeholder for now, no defined values */ 125 }; 126 127 /* Each buffer referenced elsewhere in the cmdstream submit (ie. the 128 * cmdstream buffer(s) themselves or reloc entries) has one (and only 129 * one) entry in the submit->bos[] table. 130 * 131 * As a optimization, the current buffer (gpu virtual address) can be 132 * passed back through the 'presumed' field. If on a subsequent reloc, 133 * userspace passes back a 'presumed' address that is still valid, 134 * then patching the cmdstream for this entry is skipped. This can 135 * avoid kernel needing to map/access the cmdstream bo in the common 136 * case. 137 */ 138 #define ETNA_SUBMIT_BO_READ 0x0001 139 #define ETNA_SUBMIT_BO_WRITE 0x0002 140 struct drm_etnaviv_gem_submit_bo { 141 __u32 flags; /* in, mask of ETNA_SUBMIT_BO_x */ 142 __u32 handle; /* in, GEM handle */ 143 __u64 presumed; /* in/out, presumed buffer address */ 144 }; 145 146 /* Each cmdstream submit consists of a table of buffers involved, and 147 * one or more cmdstream buffers. This allows for conditional execution 148 * (context-restore), and IB buffers needed for per tile/bin draw cmds. 149 */ 150 #define ETNA_PIPE_3D 0x00 151 #define ETNA_PIPE_2D 0x01 152 #define ETNA_PIPE_VG 0x02 153 struct drm_etnaviv_gem_submit { 154 __u32 fence; /* out */ 155 __u32 pipe; /* in */ 156 __u32 exec_state; /* in, initial execution state (ETNA_PIPE_x) */ 157 __u32 nr_bos; /* in, number of submit_bo's */ 158 __u32 nr_relocs; /* in, number of submit_reloc's */ 159 __u32 stream_size; /* in, cmdstream size */ 160 __u64 bos; /* in, ptr to array of submit_bo's */ 161 __u64 relocs; /* in, ptr to array of submit_reloc's */ 162 __u64 stream; /* in, ptr to cmdstream */ 163 }; 164 165 /* The normal way to synchronize with the GPU is just to CPU_PREP on 166 * a buffer if you need to access it from the CPU (other cmdstream 167 * submission from same or other contexts, PAGE_FLIP ioctl, etc, all 168 * handle the required synchronization under the hood). This ioctl 169 * mainly just exists as a way to implement the gallium pipe_fence 170 * APIs without requiring a dummy bo to synchronize on. 171 */ 172 #define ETNA_WAIT_NONBLOCK 0x01 173 struct drm_etnaviv_wait_fence { 174 __u32 pipe; /* in */ 175 __u32 fence; /* in */ 176 __u32 flags; /* in, mask of ETNA_WAIT_x */ 177 __u32 pad; 178 struct drm_etnaviv_timespec timeout; /* in */ 179 }; 180 181 #define ETNA_USERPTR_READ 0x01 182 #define ETNA_USERPTR_WRITE 0x02 183 struct drm_etnaviv_gem_userptr { 184 __u64 user_ptr; /* in, page aligned user pointer */ 185 __u64 user_size; /* in, page aligned user size */ 186 __u32 flags; /* in, flags */ 187 __u32 handle; /* out, non-zero handle */ 188 }; 189 190 struct drm_etnaviv_gem_wait { 191 __u32 pipe; /* in */ 192 __u32 handle; /* in, bo to be waited for */ 193 __u32 flags; /* in, mask of ETNA_WAIT_x */ 194 __u32 pad; 195 struct drm_etnaviv_timespec timeout; /* in */ 196 }; 197 198 #define DRM_ETNAVIV_GET_PARAM 0x00 199 /* placeholder: 200 #define DRM_ETNAVIV_SET_PARAM 0x01 201 */ 202 #define DRM_ETNAVIV_GEM_NEW 0x02 203 #define DRM_ETNAVIV_GEM_INFO 0x03 204 #define DRM_ETNAVIV_GEM_CPU_PREP 0x04 205 #define DRM_ETNAVIV_GEM_CPU_FINI 0x05 206 #define DRM_ETNAVIV_GEM_SUBMIT 0x06 207 #define DRM_ETNAVIV_WAIT_FENCE 0x07 208 #define DRM_ETNAVIV_GEM_USERPTR 0x08 209 #define DRM_ETNAVIV_GEM_WAIT 0x09 210 #define DRM_ETNAVIV_NUM_IOCTLS 0x0a 211 212 #define DRM_IOCTL_ETNAVIV_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GET_PARAM, struct drm_etnaviv_param) 213 #define DRM_IOCTL_ETNAVIV_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_NEW, struct drm_etnaviv_gem_new) 214 #define DRM_IOCTL_ETNAVIV_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_INFO, struct drm_etnaviv_gem_info) 215 #define DRM_IOCTL_ETNAVIV_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_PREP, struct drm_etnaviv_gem_cpu_prep) 216 #define DRM_IOCTL_ETNAVIV_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_FINI, struct drm_etnaviv_gem_cpu_fini) 217 #define DRM_IOCTL_ETNAVIV_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_SUBMIT, struct drm_etnaviv_gem_submit) 218 #define DRM_IOCTL_ETNAVIV_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_WAIT_FENCE, struct drm_etnaviv_wait_fence) 219 #define DRM_IOCTL_ETNAVIV_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_USERPTR, struct drm_etnaviv_gem_userptr) 220 #define DRM_IOCTL_ETNAVIV_GEM_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_WAIT, struct drm_etnaviv_gem_wait) 221 222 #endif /* __ETNAVIV_DRM_H__ */ 223