1 /* 2 * Copyright 2011 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef DRM_FOURCC_H 25 #define DRM_FOURCC_H 26 27 #include "drm.h" 28 29 #if defined(__cplusplus) 30 extern "C" { 31 #endif 32 33 /** 34 * DOC: overview 35 * 36 * In the DRM subsystem, framebuffer pixel formats are described using the 37 * fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the 38 * fourcc code, a Format Modifier may optionally be provided, in order to 39 * further describe the buffer's format - for example tiling or compression. 40 * 41 * Format Modifiers 42 * ---------------- 43 * 44 * Format modifiers are used in conjunction with a fourcc code, forming a 45 * unique fourcc:modifier pair. This format:modifier pair must fully define the 46 * format and data layout of the buffer, and should be the only way to describe 47 * that particular buffer. 48 * 49 * Having multiple fourcc:modifier pairs which describe the same layout should 50 * be avoided, as such aliases run the risk of different drivers exposing 51 * different names for the same data format, forcing userspace to understand 52 * that they are aliases. 53 * 54 * Format modifiers may change any property of the buffer, including the number 55 * of planes and/or the required allocation size. Format modifiers are 56 * vendor-namespaced, and as such the relationship between a fourcc code and a 57 * modifier is specific to the modifer being used. For example, some modifiers 58 * may preserve meaning - such as number of planes - from the fourcc code, 59 * whereas others may not. 60 * 61 * Vendors should document their modifier usage in as much detail as 62 * possible, to ensure maximum compatibility across devices, drivers and 63 * applications. 64 * 65 * The authoritative list of format modifier codes is found in 66 * `include/uapi/drm/drm_fourcc.h` 67 */ 68 69 #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \ 70 ((__u32)(c) << 16) | ((__u32)(d) << 24)) 71 72 #define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */ 73 74 /* Reserve 0 for the invalid format specifier */ 75 #define DRM_FORMAT_INVALID 0 76 77 /* color index */ 78 #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */ 79 80 /* 8 bpp Red */ 81 #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */ 82 83 /* 16 bpp Red */ 84 #define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */ 85 86 /* 16 bpp RG */ 87 #define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */ 88 #define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */ 89 90 /* 32 bpp RG */ 91 #define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */ 92 #define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */ 93 94 /* 8 bpp RGB */ 95 #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */ 96 #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */ 97 98 /* 16 bpp RGB */ 99 #define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */ 100 #define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */ 101 #define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */ 102 #define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */ 103 104 #define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */ 105 #define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */ 106 #define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */ 107 #define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */ 108 109 #define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */ 110 #define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */ 111 #define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */ 112 #define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */ 113 114 #define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */ 115 #define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */ 116 #define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */ 117 #define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */ 118 119 #define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */ 120 #define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */ 121 122 /* 24 bpp RGB */ 123 #define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */ 124 #define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */ 125 126 /* 32 bpp RGB */ 127 #define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */ 128 #define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */ 129 #define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */ 130 #define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */ 131 132 #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */ 133 #define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */ 134 #define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */ 135 #define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */ 136 137 #define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */ 138 #define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */ 139 #define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */ 140 #define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */ 141 142 #define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */ 143 #define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */ 144 #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */ 145 #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */ 146 147 /* 148 * Floating point 64bpp RGB 149 * IEEE 754-2008 binary16 half-precision float 150 * [15:0] sign:exponent:mantissa 1:5:10 151 */ 152 #define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */ 153 #define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */ 154 155 #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */ 156 #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */ 157 158 /* packed YCbCr */ 159 #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */ 160 #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */ 161 #define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */ 162 #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */ 163 164 #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */ 165 #define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */ 166 #define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */ 167 #define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */ 168 169 /* 170 * packed Y2xx indicate for each component, xx valid data occupy msb 171 * 16-xx padding occupy lsb 172 */ 173 #define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little endian per 2 Y pixels */ 174 #define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */ 175 #define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16 little endian per 2 Y pixels */ 176 177 /* 178 * packed Y4xx indicate for each component, xx valid data occupy msb 179 * 16-xx padding occupy lsb except Y410 180 */ 181 #define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 little endian */ 182 #define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */ 183 #define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 little endian */ 184 185 #define DRM_FORMAT_XVYU2101010 fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 little endian */ 186 #define DRM_FORMAT_XVYU12_16161616 fourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */ 187 #define DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 little endian */ 188 189 /* 190 * packed YCbCr420 2x2 tiled formats 191 * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile 192 */ 193 /* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */ 194 #define DRM_FORMAT_Y0L0 fourcc_code('Y', '0', 'L', '0') 195 /* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */ 196 #define DRM_FORMAT_X0L0 fourcc_code('X', '0', 'L', '0') 197 198 /* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */ 199 #define DRM_FORMAT_Y0L2 fourcc_code('Y', '0', 'L', '2') 200 /* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */ 201 #define DRM_FORMAT_X0L2 fourcc_code('X', '0', 'L', '2') 202 203 /* 204 * 1-plane YUV 4:2:0 205 * In these formats, the component ordering is specified (Y, followed by U 206 * then V), but the exact Linear layout is undefined. 207 * These formats can only be used with a non-Linear modifier. 208 */ 209 #define DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8') 210 #define DRM_FORMAT_YUV420_10BIT fourcc_code('Y', 'U', '1', '0') 211 212 /* 213 * 2 plane RGB + A 214 * index 0 = RGB plane, same format as the corresponding non _A8 format has 215 * index 1 = A plane, [7:0] A 216 */ 217 #define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8') 218 #define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8') 219 #define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8') 220 #define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8') 221 #define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8') 222 #define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8') 223 #define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8') 224 #define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8') 225 226 /* 227 * 2 plane YCbCr 228 * index 0 = Y plane, [7:0] Y 229 * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian 230 * or 231 * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian 232 */ 233 #define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */ 234 #define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */ 235 #define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */ 236 #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */ 237 #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */ 238 #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */ 239 /* 240 * 2 plane YCbCr 241 * index 0 = Y plane, [39:0] Y3:Y2:Y1:Y0 little endian 242 * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian 243 */ 244 #define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */ 245 246 /* 247 * 2 plane YCbCr MSB aligned 248 * index 0 = Y plane, [15:0] Y:x [10:6] little endian 249 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian 250 */ 251 #define DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per channel */ 252 253 /* 254 * 2 plane YCbCr MSB aligned 255 * index 0 = Y plane, [15:0] Y:x [10:6] little endian 256 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian 257 */ 258 #define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */ 259 260 /* 261 * 2 plane YCbCr MSB aligned 262 * index 0 = Y plane, [15:0] Y:x [12:4] little endian 263 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian 264 */ 265 #define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */ 266 267 /* 268 * 2 plane YCbCr MSB aligned 269 * index 0 = Y plane, [15:0] Y little endian 270 * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian 271 */ 272 #define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */ 273 274 /* 3 plane non-subsampled (444) YCbCr 275 * 16 bits per component, but only 10 bits are used and 6 bits are padded 276 * index 0: Y plane, [15:0] Y:x [10:6] little endian 277 * index 1: Cb plane, [15:0] Cb:x [10:6] little endian 278 * index 2: Cr plane, [15:0] Cr:x [10:6] little endian 279 */ 280 #define DRM_FORMAT_Q410 fourcc_code('Q', '4', '1', '0') 281 282 /* 3 plane non-subsampled (444) YCrCb 283 * 16 bits per component, but only 10 bits are used and 6 bits are padded 284 * index 0: Y plane, [15:0] Y:x [10:6] little endian 285 * index 1: Cr plane, [15:0] Cr:x [10:6] little endian 286 * index 2: Cb plane, [15:0] Cb:x [10:6] little endian 287 */ 288 #define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1') 289 290 /* 291 * 3 plane YCbCr 292 * index 0: Y plane, [7:0] Y 293 * index 1: Cb plane, [7:0] Cb 294 * index 2: Cr plane, [7:0] Cr 295 * or 296 * index 1: Cr plane, [7:0] Cr 297 * index 2: Cb plane, [7:0] Cb 298 */ 299 #define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */ 300 #define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */ 301 #define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */ 302 #define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */ 303 #define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */ 304 #define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */ 305 #define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */ 306 #define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */ 307 #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */ 308 #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */ 309 310 311 /* 312 * Format Modifiers: 313 * 314 * Format modifiers describe, typically, a re-ordering or modification 315 * of the data in a plane of an FB. This can be used to express tiled/ 316 * swizzled formats, or compression, or a combination of the two. 317 * 318 * The upper 8 bits of the format modifier are a vendor-id as assigned 319 * below. The lower 56 bits are assigned as vendor sees fit. 320 */ 321 322 /* Vendor Ids: */ 323 #define DRM_FORMAT_MOD_NONE 0 324 #define DRM_FORMAT_MOD_VENDOR_NONE 0 325 #define DRM_FORMAT_MOD_VENDOR_INTEL 0x01 326 #define DRM_FORMAT_MOD_VENDOR_AMD 0x02 327 #define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03 328 #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 329 #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 330 #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06 331 #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07 332 #define DRM_FORMAT_MOD_VENDOR_ARM 0x08 333 #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09 334 #define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a 335 336 /* add more to the end as needed */ 337 338 #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1) 339 340 #define fourcc_mod_code(vendor, val) \ 341 ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL)) 342 343 /* 344 * Format Modifier tokens: 345 * 346 * When adding a new token please document the layout with a code comment, 347 * similar to the fourcc codes above. drm_fourcc.h is considered the 348 * authoritative source for all of these. 349 * 350 * Generic modifier names: 351 * 352 * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names 353 * for layouts which are common across multiple vendors. To preserve 354 * compatibility, in cases where a vendor-specific definition already exists and 355 * a generic name for it is desired, the common name is a purely symbolic alias 356 * and must use the same numerical value as the original definition. 357 * 358 * Note that generic names should only be used for modifiers which describe 359 * generic layouts (such as pixel re-ordering), which may have 360 * independently-developed support across multiple vendors. 361 * 362 * In future cases where a generic layout is identified before merging with a 363 * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor 364 * 'NONE' could be considered. This should only be for obvious, exceptional 365 * cases to avoid polluting the 'GENERIC' namespace with modifiers which only 366 * apply to a single vendor. 367 * 368 * Generic names should not be used for cases where multiple hardware vendors 369 * have implementations of the same standardised compression scheme (such as 370 * AFBC). In those cases, all implementations should use the same format 371 * modifier(s), reflecting the vendor of the standard. 372 */ 373 374 #define DRM_FORMAT_MOD_GENERIC_16_16_TILE DRM_FORMAT_MOD_SAMSUNG_16_16_TILE 375 376 /* 377 * Invalid Modifier 378 * 379 * This modifier can be used as a sentinel to terminate the format modifiers 380 * list, or to initialize a variable with an invalid modifier. It might also be 381 * used to report an error back to userspace for certain APIs. 382 */ 383 #define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED) 384 385 /* 386 * Linear Layout 387 * 388 * Just plain linear layout. Note that this is different from no specifying any 389 * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl), 390 * which tells the driver to also take driver-internal information into account 391 * and so might actually result in a tiled framebuffer. 392 */ 393 #define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0) 394 395 /* Intel framebuffer modifiers */ 396 397 /* 398 * Intel X-tiling layout 399 * 400 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) 401 * in row-major layout. Within the tile bytes are laid out row-major, with 402 * a platform-dependent stride. On top of that the memory can apply 403 * platform-depending swizzling of some higher address bits into bit6. 404 * 405 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets. 406 * On earlier platforms the is highly platforms specific and not useful for 407 * cross-driver sharing. It exists since on a given platform it does uniquely 408 * identify the layout in a simple way for i915-specific userspace, which 409 * facilitated conversion of userspace to modifiers. Additionally the exact 410 * format on some really old platforms is not known. 411 */ 412 #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1) 413 414 /* 415 * Intel Y-tiling layout 416 * 417 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) 418 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes) 419 * chunks column-major, with a platform-dependent height. On top of that the 420 * memory can apply platform-depending swizzling of some higher address bits 421 * into bit6. 422 * 423 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets. 424 * On earlier platforms the is highly platforms specific and not useful for 425 * cross-driver sharing. It exists since on a given platform it does uniquely 426 * identify the layout in a simple way for i915-specific userspace, which 427 * facilitated conversion of userspace to modifiers. Additionally the exact 428 * format on some really old platforms is not known. 429 */ 430 #define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2) 431 432 /* 433 * Intel Yf-tiling layout 434 * 435 * This is a tiled layout using 4Kb tiles in row-major layout. 436 * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which 437 * are arranged in four groups (two wide, two high) with column-major layout. 438 * Each group therefore consits out of four 256 byte units, which are also laid 439 * out as 2x2 column-major. 440 * 256 byte units are made out of four 64 byte blocks of pixels, producing 441 * either a square block or a 2:1 unit. 442 * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width 443 * in pixel depends on the pixel depth. 444 */ 445 #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3) 446 447 /* 448 * Intel color control surface (CCS) for render compression 449 * 450 * The framebuffer format must be one of the 8:8:8:8 RGB formats. 451 * The main surface will be plane index 0 and must be Y/Yf-tiled, 452 * the CCS will be plane index 1. 453 * 454 * Each CCS tile matches a 1024x512 pixel area of the main surface. 455 * To match certain aspects of the 3D hardware the CCS is 456 * considered to be made up of normal 128Bx32 Y tiles, Thus 457 * the CCS pitch must be specified in multiples of 128 bytes. 458 * 459 * In reality the CCS tile appears to be a 64Bx64 Y tile, composed 460 * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks. 461 * But that fact is not relevant unless the memory is accessed 462 * directly. 463 */ 464 #define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4) 465 #define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5) 466 467 /* 468 * Intel color control surfaces (CCS) for Gen-12 render compression. 469 * 470 * The main surface is Y-tiled and at plane index 0, the CCS is linear and 471 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in 472 * main surface. In other words, 4 bits in CCS map to a main surface cache 473 * line pair. The main surface pitch is required to be a multiple of four 474 * Y-tile widths. 475 */ 476 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6) 477 478 /* 479 * Intel color control surfaces (CCS) for Gen-12 media compression 480 * 481 * The main surface is Y-tiled and at plane index 0, the CCS is linear and 482 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in 483 * main surface. In other words, 4 bits in CCS map to a main surface cache 484 * line pair. The main surface pitch is required to be a multiple of four 485 * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the 486 * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces, 487 * planes 2 and 3 for the respective CCS. 488 */ 489 #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7) 490 491 /* 492 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks 493 * 494 * Macroblocks are laid in a Z-shape, and each pixel data is following the 495 * standard NV12 style. 496 * As for NV12, an image is the result of two frame buffers: one for Y, 497 * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer). 498 * Alignment requirements are (for each buffer): 499 * - multiple of 128 pixels for the width 500 * - multiple of 32 pixels for the height 501 * 502 * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html 503 */ 504 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1) 505 506 /* 507 * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks 508 * 509 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major 510 * layout. For YCbCr formats Cb/Cr components are taken in such a way that 511 * they correspond to their 16x16 luma block. 512 */ 513 #define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2) 514 515 /* 516 * Qualcomm Compressed Format 517 * 518 * Refers to a compressed variant of the base format that is compressed. 519 * Implementation may be platform and base-format specific. 520 * 521 * Each macrotile consists of m x n (mostly 4 x 4) tiles. 522 * Pixel data pitch/stride is aligned with macrotile width. 523 * Pixel data height is aligned with macrotile height. 524 * Entire pixel data buffer is aligned with 4k(bytes). 525 */ 526 #define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1) 527 528 /* Vivante framebuffer modifiers */ 529 530 /* 531 * Vivante 4x4 tiling layout 532 * 533 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major 534 * layout. 535 */ 536 #define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1) 537 538 /* 539 * Vivante 64x64 super-tiling layout 540 * 541 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile 542 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row- 543 * major layout. 544 * 545 * For more information: see 546 * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling 547 */ 548 #define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2) 549 550 /* 551 * Vivante 4x4 tiling layout for dual-pipe 552 * 553 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a 554 * different base address. Offsets from the base addresses are therefore halved 555 * compared to the non-split tiled layout. 556 */ 557 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3) 558 559 /* 560 * Vivante 64x64 super-tiling layout for dual-pipe 561 * 562 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile 563 * starts at a different base address. Offsets from the base addresses are 564 * therefore halved compared to the non-split super-tiled layout. 565 */ 566 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4) 567 568 /* NVIDIA frame buffer modifiers */ 569 570 /* 571 * Tegra Tiled Layout, used by Tegra 2, 3 and 4. 572 * 573 * Pixels are arranged in simple tiles of 16 x 16 bytes. 574 */ 575 #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1) 576 577 /* 578 * Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80, 579 * and Tegra GPUs starting with Tegra K1. 580 * 581 * Pixels are arranged in Groups of Bytes (GOBs). GOB size and layout varies 582 * based on the architecture generation. GOBs themselves are then arranged in 583 * 3D blocks, with the block dimensions (in terms of GOBs) always being a power 584 * of two, and hence expressible as their log2 equivalent (E.g., "2" represents 585 * a block depth or height of "4"). 586 * 587 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format 588 * in full detail. 589 * 590 * Macro 591 * Bits Param Description 592 * ---- ----- ----------------------------------------------------------------- 593 * 594 * 3:0 h log2(height) of each block, in GOBs. Placed here for 595 * compatibility with the existing 596 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers. 597 * 598 * 4:4 - Must be 1, to indicate block-linear layout. Necessary for 599 * compatibility with the existing 600 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers. 601 * 602 * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block 603 * size). Must be zero. 604 * 605 * Note there is no log2(width) parameter. Some portions of the 606 * hardware support a block width of two gobs, but it is impractical 607 * to use due to lack of support elsewhere, and has no known 608 * benefits. 609 * 610 * 11:9 - Reserved (To support 2D-array textures with variable array stride 611 * in blocks, specified via log2(tile width in blocks)). Must be 612 * zero. 613 * 614 * 19:12 k Page Kind. This value directly maps to a field in the page 615 * tables of all GPUs >= NV50. It affects the exact layout of bits 616 * in memory and can be derived from the tuple 617 * 618 * (format, GPU model, compression type, samples per pixel) 619 * 620 * Where compression type is defined below. If GPU model were 621 * implied by the format modifier, format, or memory buffer, page 622 * kind would not need to be included in the modifier itself, but 623 * since the modifier should define the layout of the associated 624 * memory buffer independent from any device or other context, it 625 * must be included here. 626 * 627 * 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed 628 * starting with Fermi GPUs. Additionally, the mapping between page 629 * kind and bit layout has changed at various points. 630 * 631 * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping 632 * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping 633 * 2 = Gob Height 8, Turing+ Page Kind mapping 634 * 3 = Reserved for future use. 635 * 636 * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further 637 * bit remapping step that occurs at an even lower level than the 638 * page kind and block linear swizzles. This causes the layout of 639 * surfaces mapped in those SOC's GPUs to be incompatible with the 640 * equivalent mapping on other GPUs in the same system. 641 * 642 * 0 = Tegra K1 - Tegra Parker/TX2 Layout. 643 * 1 = Desktop GPU and Tegra Xavier+ Layout 644 * 645 * 25:23 c Lossless Framebuffer Compression type. 646 * 647 * 0 = none 648 * 1 = ROP/3D, layout 1, exact compression format implied by Page 649 * Kind field 650 * 2 = ROP/3D, layout 2, exact compression format implied by Page 651 * Kind field 652 * 3 = CDE horizontal 653 * 4 = CDE vertical 654 * 5 = Reserved for future use 655 * 6 = Reserved for future use 656 * 7 = Reserved for future use 657 * 658 * 55:25 - Reserved for future use. Must be zero. 659 */ 660 #define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \ 661 fourcc_mod_code(NVIDIA, (0x10 | \ 662 ((h) & 0xf) | \ 663 (((k) & 0xff) << 12) | \ 664 (((g) & 0x3) << 20) | \ 665 (((s) & 0x1) << 22) | \ 666 (((c) & 0x7) << 23))) 667 668 /* To grandfather in prior block linear format modifiers to the above layout, 669 * the page kind "0", which corresponds to "pitch/linear" and hence is unusable 670 * with block-linear layouts, is remapped within drivers to the value 0xfe, 671 * which corresponds to the "generic" kind used for simple single-sample 672 * uncompressed color formats on Fermi - Volta GPUs. 673 */ 674 static inline __u64 675 drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) 676 { 677 if (!(modifier & 0x10) || (modifier & (0xff << 12))) 678 return modifier; 679 else 680 return modifier | (0xfe << 12); 681 } 682 683 /* 684 * 16Bx2 Block Linear layout, used by Tegra K1 and later 685 * 686 * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked 687 * vertically by a power of 2 (1 to 32 GOBs) to form a block. 688 * 689 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape. 690 * 691 * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically. 692 * Valid values are: 693 * 694 * 0 == ONE_GOB 695 * 1 == TWO_GOBS 696 * 2 == FOUR_GOBS 697 * 3 == EIGHT_GOBS 698 * 4 == SIXTEEN_GOBS 699 * 5 == THIRTYTWO_GOBS 700 * 701 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format 702 * in full detail. 703 */ 704 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \ 705 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v)) 706 707 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \ 708 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0) 709 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \ 710 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1) 711 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \ 712 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2) 713 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \ 714 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3) 715 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \ 716 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4) 717 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \ 718 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5) 719 720 /* 721 * Some Broadcom modifiers take parameters, for example the number of 722 * vertical lines in the image. Reserve the lower 32 bits for modifier 723 * type, and the next 24 bits for parameters. Top 8 bits are the 724 * vendor code. 725 */ 726 #define __fourcc_mod_broadcom_param_shift 8 727 #define __fourcc_mod_broadcom_param_bits 48 728 #define fourcc_mod_broadcom_code(val, params) \ 729 fourcc_mod_code(BROADCOM, ((((__u64)params) << __fourcc_mod_broadcom_param_shift) | val)) 730 #define fourcc_mod_broadcom_param(m) \ 731 ((int)(((m) >> __fourcc_mod_broadcom_param_shift) & \ 732 ((1ULL << __fourcc_mod_broadcom_param_bits) - 1))) 733 #define fourcc_mod_broadcom_mod(m) \ 734 ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \ 735 __fourcc_mod_broadcom_param_shift)) 736 737 /* 738 * Broadcom VC4 "T" format 739 * 740 * This is the primary layout that the V3D GPU can texture from (it 741 * can't do linear). The T format has: 742 * 743 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4 744 * pixels at 32 bit depth. 745 * 746 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually 747 * 16x16 pixels). 748 * 749 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On 750 * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows 751 * they're (TR, BR, BL, TL), where bottom left is start of memory. 752 * 753 * - an image made of 4k tiles in rows either left-to-right (even rows of 4k 754 * tiles) or right-to-left (odd rows of 4k tiles). 755 */ 756 #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1) 757 758 /* 759 * Broadcom SAND format 760 * 761 * This is the native format that the H.264 codec block uses. For VC4 762 * HVS, it is only valid for H.264 (NV12/21) and RGBA modes. 763 * 764 * The image can be considered to be split into columns, and the 765 * columns are placed consecutively into memory. The width of those 766 * columns can be either 32, 64, 128, or 256 pixels, but in practice 767 * only 128 pixel columns are used. 768 * 769 * The pitch between the start of each column is set to optimally 770 * switch between SDRAM banks. This is passed as the number of lines 771 * of column width in the modifier (we can't use the stride value due 772 * to various core checks that look at it , so you should set the 773 * stride to width*cpp). 774 * 775 * Note that the column height for this format modifier is the same 776 * for all of the planes, assuming that each column contains both Y 777 * and UV. Some SAND-using hardware stores UV in a separate tiled 778 * image from Y to reduce the column height, which is not supported 779 * with these modifiers. 780 */ 781 782 #define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \ 783 fourcc_mod_broadcom_code(2, v) 784 #define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \ 785 fourcc_mod_broadcom_code(3, v) 786 #define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \ 787 fourcc_mod_broadcom_code(4, v) 788 #define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \ 789 fourcc_mod_broadcom_code(5, v) 790 791 #define DRM_FORMAT_MOD_BROADCOM_SAND32 \ 792 DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0) 793 #define DRM_FORMAT_MOD_BROADCOM_SAND64 \ 794 DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0) 795 #define DRM_FORMAT_MOD_BROADCOM_SAND128 \ 796 DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0) 797 #define DRM_FORMAT_MOD_BROADCOM_SAND256 \ 798 DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0) 799 800 /* Broadcom UIF format 801 * 802 * This is the common format for the current Broadcom multimedia 803 * blocks, including V3D 3.x and newer, newer video codecs, and 804 * displays. 805 * 806 * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles), 807 * and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are 808 * stored in columns, with padding between the columns to ensure that 809 * moving from one column to the next doesn't hit the same SDRAM page 810 * bank. 811 * 812 * To calculate the padding, it is assumed that each hardware block 813 * and the software driving it knows the platform's SDRAM page size, 814 * number of banks, and XOR address, and that it's identical between 815 * all blocks using the format. This tiling modifier will use XOR as 816 * necessary to reduce the padding. If a hardware block can't do XOR, 817 * the assumption is that a no-XOR tiling modifier will be created. 818 */ 819 #define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6) 820 821 /* 822 * Arm Framebuffer Compression (AFBC) modifiers 823 * 824 * AFBC is a proprietary lossless image compression protocol and format. 825 * It provides fine-grained random access and minimizes the amount of data 826 * transferred between IP blocks. 827 * 828 * AFBC has several features which may be supported and/or used, which are 829 * represented using bits in the modifier. Not all combinations are valid, 830 * and different devices or use-cases may support different combinations. 831 * 832 * Further information on the use of AFBC modifiers can be found in 833 * Documentation/gpu/afbc.rst 834 */ 835 836 /* 837 * The top 4 bits (out of the 56 bits alloted for specifying vendor specific 838 * modifiers) denote the category for modifiers. Currently we have only two 839 * categories of modifiers ie AFBC and MISC. We can have a maximum of sixteen 840 * different categories. 841 */ 842 #define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \ 843 fourcc_mod_code(ARM, ((__u64)(__type) << 52) | ((__val) & 0x000fffffffffffffULL)) 844 845 #define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00 846 #define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01 847 848 #define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \ 849 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode) 850 851 /* 852 * AFBC superblock size 853 * 854 * Indicates the superblock size(s) used for the AFBC buffer. The buffer 855 * size (in pixels) must be aligned to a multiple of the superblock size. 856 * Four lowest significant bits(LSBs) are reserved for block size. 857 * 858 * Where one superblock size is specified, it applies to all planes of the 859 * buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified, 860 * the first applies to the Luma plane and the second applies to the Chroma 861 * plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma). 862 * Multiple superblock sizes are only valid for multi-plane YCbCr formats. 863 */ 864 #define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf 865 #define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL) 866 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL) 867 #define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4 (3ULL) 868 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL) 869 870 /* 871 * AFBC lossless colorspace transform 872 * 873 * Indicates that the buffer makes use of the AFBC lossless colorspace 874 * transform. 875 */ 876 #define AFBC_FORMAT_MOD_YTR (1ULL << 4) 877 878 /* 879 * AFBC block-split 880 * 881 * Indicates that the payload of each superblock is split. The second 882 * half of the payload is positioned at a predefined offset from the start 883 * of the superblock payload. 884 */ 885 #define AFBC_FORMAT_MOD_SPLIT (1ULL << 5) 886 887 /* 888 * AFBC sparse layout 889 * 890 * This flag indicates that the payload of each superblock must be stored at a 891 * predefined position relative to the other superblocks in the same AFBC 892 * buffer. This order is the same order used by the header buffer. In this mode 893 * each superblock is given the same amount of space as an uncompressed 894 * superblock of the particular format would require, rounding up to the next 895 * multiple of 128 bytes in size. 896 */ 897 #define AFBC_FORMAT_MOD_SPARSE (1ULL << 6) 898 899 /* 900 * AFBC copy-block restrict 901 * 902 * Buffers with this flag must obey the copy-block restriction. The restriction 903 * is such that there are no copy-blocks referring across the border of 8x8 904 * blocks. For the subsampled data the 8x8 limitation is also subsampled. 905 */ 906 #define AFBC_FORMAT_MOD_CBR (1ULL << 7) 907 908 /* 909 * AFBC tiled layout 910 * 911 * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all 912 * superblocks inside a tile are stored together in memory. 8x8 tiles are used 913 * for pixel formats up to and including 32 bpp while 4x4 tiles are used for 914 * larger bpp formats. The order between the tiles is scan line. 915 * When the tiled layout is used, the buffer size (in pixels) must be aligned 916 * to the tile size. 917 */ 918 #define AFBC_FORMAT_MOD_TILED (1ULL << 8) 919 920 /* 921 * AFBC solid color blocks 922 * 923 * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth 924 * can be reduced if a whole superblock is a single color. 925 */ 926 #define AFBC_FORMAT_MOD_SC (1ULL << 9) 927 928 /* 929 * AFBC double-buffer 930 * 931 * Indicates that the buffer is allocated in a layout safe for front-buffer 932 * rendering. 933 */ 934 #define AFBC_FORMAT_MOD_DB (1ULL << 10) 935 936 /* 937 * AFBC buffer content hints 938 * 939 * Indicates that the buffer includes per-superblock content hints. 940 */ 941 #define AFBC_FORMAT_MOD_BCH (1ULL << 11) 942 943 /* AFBC uncompressed storage mode 944 * 945 * Indicates that the buffer is using AFBC uncompressed storage mode. 946 * In this mode all superblock payloads in the buffer use the uncompressed 947 * storage mode, which is usually only used for data which cannot be compressed. 948 * The buffer layout is the same as for AFBC buffers without USM set, this only 949 * affects the storage mode of the individual superblocks. Note that even a 950 * buffer without USM set may use uncompressed storage mode for some or all 951 * superblocks, USM just guarantees it for all. 952 */ 953 #define AFBC_FORMAT_MOD_USM (1ULL << 12) 954 955 /* 956 * Arm 16x16 Block U-Interleaved modifier 957 * 958 * This is used by Arm Mali Utgard and Midgard GPUs. It divides the image 959 * into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels 960 * in the block are reordered. 961 */ 962 #define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \ 963 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL) 964 965 /* 966 * Allwinner tiled modifier 967 * 968 * This tiling mode is implemented by the VPU found on all Allwinner platforms, 969 * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3 970 * planes. 971 * 972 * With this tiling, the luminance samples are disposed in tiles representing 973 * 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels. 974 * The pixel order in each tile is linear and the tiles are disposed linearly, 975 * both in row-major order. 976 */ 977 #define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1) 978 979 /* 980 * Amlogic Video Framebuffer Compression modifiers 981 * 982 * Amlogic uses a proprietary lossless image compression protocol and format 983 * for their hardware video codec accelerators, either video decoders or 984 * video input encoders. 985 * 986 * It considerably reduces memory bandwidth while writing and reading 987 * frames in memory. 988 * 989 * The underlying storage is considered to be 3 components, 8bit or 10-bit 990 * per component YCbCr 420, single plane : 991 * - DRM_FORMAT_YUV420_8BIT 992 * - DRM_FORMAT_YUV420_10BIT 993 * 994 * The first 8 bits of the mode defines the layout, then the following 8 bits 995 * defines the options changing the layout. 996 * 997 * Not all combinations are valid, and different SoCs may support different 998 * combinations of layout and options. 999 */ 1000 #define __fourcc_mod_amlogic_layout_mask 0xf 1001 #define __fourcc_mod_amlogic_options_shift 8 1002 #define __fourcc_mod_amlogic_options_mask 0xf 1003 1004 #define DRM_FORMAT_MOD_AMLOGIC_FBC(__layout, __options) \ 1005 fourcc_mod_code(AMLOGIC, \ 1006 ((__layout) & __fourcc_mod_amlogic_layout_mask) | \ 1007 (((__options) & __fourcc_mod_amlogic_options_mask) \ 1008 << __fourcc_mod_amlogic_options_shift)) 1009 1010 /* Amlogic FBC Layouts */ 1011 1012 /* 1013 * Amlogic FBC Basic Layout 1014 * 1015 * The basic layout is composed of: 1016 * - a body content organized in 64x32 superblocks with 4096 bytes per 1017 * superblock in default mode. 1018 * - a 32 bytes per 128x64 header block 1019 * 1020 * This layout is transferrable between Amlogic SoCs supporting this modifier. 1021 */ 1022 #define AMLOGIC_FBC_LAYOUT_BASIC (1ULL) 1023 1024 /* 1025 * Amlogic FBC Scatter Memory layout 1026 * 1027 * Indicates the header contains IOMMU references to the compressed 1028 * frames content to optimize memory access and layout. 1029 * 1030 * In this mode, only the header memory address is needed, thus the 1031 * content memory organization is tied to the current producer 1032 * execution and cannot be saved/dumped neither transferrable between 1033 * Amlogic SoCs supporting this modifier. 1034 * 1035 * Due to the nature of the layout, these buffers are not expected to 1036 * be accessible by the user-space clients, but only accessible by the 1037 * hardware producers and consumers. 1038 * 1039 * The user-space clients should expect a failure while trying to mmap 1040 * the DMA-BUF handle returned by the producer. 1041 */ 1042 #define AMLOGIC_FBC_LAYOUT_SCATTER (2ULL) 1043 1044 /* Amlogic FBC Layout Options Bit Mask */ 1045 1046 /* 1047 * Amlogic FBC Memory Saving mode 1048 * 1049 * Indicates the storage is packed when pixel size is multiple of word 1050 * boudaries, i.e. 8bit should be stored in this mode to save allocation 1051 * memory. 1052 * 1053 * This mode reduces body layout to 3072 bytes per 64x32 superblock with 1054 * the basic layout and 3200 bytes per 64x32 superblock combined with 1055 * the scatter layout. 1056 */ 1057 #define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0) 1058 1059 #if defined(__cplusplus) 1060 } 1061 #endif 1062 1063 #endif /* DRM_FOURCC_H */ 1064