1 /* 2 * Copyright 2011 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef DRM_FOURCC_H 25 #define DRM_FOURCC_H 26 27 #include "drm.h" 28 29 #if defined(__cplusplus) 30 extern "C" { 31 #endif 32 33 /** 34 * DOC: overview 35 * 36 * In the DRM subsystem, framebuffer pixel formats are described using the 37 * fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the 38 * fourcc code, a Format Modifier may optionally be provided, in order to 39 * further describe the buffer's format - for example tiling or compression. 40 * 41 * Format Modifiers 42 * ---------------- 43 * 44 * Format modifiers are used in conjunction with a fourcc code, forming a 45 * unique fourcc:modifier pair. This format:modifier pair must fully define the 46 * format and data layout of the buffer, and should be the only way to describe 47 * that particular buffer. 48 * 49 * Having multiple fourcc:modifier pairs which describe the same layout should 50 * be avoided, as such aliases run the risk of different drivers exposing 51 * different names for the same data format, forcing userspace to understand 52 * that they are aliases. 53 * 54 * Format modifiers may change any property of the buffer, including the number 55 * of planes and/or the required allocation size. Format modifiers are 56 * vendor-namespaced, and as such the relationship between a fourcc code and a 57 * modifier is specific to the modifer being used. For example, some modifiers 58 * may preserve meaning - such as number of planes - from the fourcc code, 59 * whereas others may not. 60 * 61 * Modifiers must uniquely encode buffer layout. In other words, a buffer must 62 * match only a single modifier. A modifier must not be a subset of layouts of 63 * another modifier. For instance, it's incorrect to encode pitch alignment in 64 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel 65 * aligned modifier. That said, modifiers can have implicit minimal 66 * requirements. 67 * 68 * For modifiers where the combination of fourcc code and modifier can alias, 69 * a canonical pair needs to be defined and used by all drivers. Preferred 70 * combinations are also encouraged where all combinations might lead to 71 * confusion and unnecessarily reduced interoperability. An example for the 72 * latter is AFBC, where the ABGR layouts are preferred over ARGB layouts. 73 * 74 * There are two kinds of modifier users: 75 * 76 * - Kernel and user-space drivers: for drivers it's important that modifiers 77 * don't alias, otherwise two drivers might support the same format but use 78 * different aliases, preventing them from sharing buffers in an efficient 79 * format. 80 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users 81 * see modifiers as opaque tokens they can check for equality and intersect. 82 * These users musn't need to know to reason about the modifier value 83 * (i.e. they are not expected to extract information out of the modifier). 84 * 85 * Vendors should document their modifier usage in as much detail as 86 * possible, to ensure maximum compatibility across devices, drivers and 87 * applications. 88 * 89 * The authoritative list of format modifier codes is found in 90 * `include/uapi/drm/drm_fourcc.h` 91 */ 92 93 #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \ 94 ((__u32)(c) << 16) | ((__u32)(d) << 24)) 95 96 #define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */ 97 98 /* Reserve 0 for the invalid format specifier */ 99 #define DRM_FORMAT_INVALID 0 100 101 /* color index */ 102 #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */ 103 104 /* 8 bpp Red */ 105 #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */ 106 107 /* 16 bpp Red */ 108 #define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */ 109 110 /* 16 bpp RG */ 111 #define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */ 112 #define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */ 113 114 /* 32 bpp RG */ 115 #define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */ 116 #define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */ 117 118 /* 8 bpp RGB */ 119 #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */ 120 #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */ 121 122 /* 16 bpp RGB */ 123 #define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */ 124 #define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */ 125 #define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */ 126 #define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */ 127 128 #define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */ 129 #define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */ 130 #define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */ 131 #define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */ 132 133 #define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */ 134 #define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */ 135 #define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */ 136 #define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */ 137 138 #define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */ 139 #define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */ 140 #define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */ 141 #define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */ 142 143 #define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */ 144 #define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */ 145 146 /* 24 bpp RGB */ 147 #define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */ 148 #define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */ 149 150 /* 32 bpp RGB */ 151 #define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */ 152 #define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */ 153 #define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */ 154 #define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */ 155 156 #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */ 157 #define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */ 158 #define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */ 159 #define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */ 160 161 #define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */ 162 #define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */ 163 #define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */ 164 #define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */ 165 166 #define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */ 167 #define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */ 168 #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */ 169 #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */ 170 171 /* 172 * Floating point 64bpp RGB 173 * IEEE 754-2008 binary16 half-precision float 174 * [15:0] sign:exponent:mantissa 1:5:10 175 */ 176 #define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */ 177 #define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */ 178 179 #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */ 180 #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */ 181 182 /* packed YCbCr */ 183 #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */ 184 #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */ 185 #define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */ 186 #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */ 187 188 #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */ 189 #define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */ 190 #define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */ 191 #define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */ 192 193 /* 194 * packed Y2xx indicate for each component, xx valid data occupy msb 195 * 16-xx padding occupy lsb 196 */ 197 #define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little endian per 2 Y pixels */ 198 #define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */ 199 #define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16 little endian per 2 Y pixels */ 200 201 /* 202 * packed Y4xx indicate for each component, xx valid data occupy msb 203 * 16-xx padding occupy lsb except Y410 204 */ 205 #define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 little endian */ 206 #define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */ 207 #define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 little endian */ 208 209 #define DRM_FORMAT_XVYU2101010 fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 little endian */ 210 #define DRM_FORMAT_XVYU12_16161616 fourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */ 211 #define DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 little endian */ 212 213 /* 214 * packed YCbCr420 2x2 tiled formats 215 * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile 216 */ 217 /* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */ 218 #define DRM_FORMAT_Y0L0 fourcc_code('Y', '0', 'L', '0') 219 /* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */ 220 #define DRM_FORMAT_X0L0 fourcc_code('X', '0', 'L', '0') 221 222 /* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */ 223 #define DRM_FORMAT_Y0L2 fourcc_code('Y', '0', 'L', '2') 224 /* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */ 225 #define DRM_FORMAT_X0L2 fourcc_code('X', '0', 'L', '2') 226 227 /* 228 * 1-plane YUV 4:2:0 229 * In these formats, the component ordering is specified (Y, followed by U 230 * then V), but the exact Linear layout is undefined. 231 * These formats can only be used with a non-Linear modifier. 232 */ 233 #define DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8') 234 #define DRM_FORMAT_YUV420_10BIT fourcc_code('Y', 'U', '1', '0') 235 236 /* 237 * 2 plane RGB + A 238 * index 0 = RGB plane, same format as the corresponding non _A8 format has 239 * index 1 = A plane, [7:0] A 240 */ 241 #define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8') 242 #define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8') 243 #define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8') 244 #define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8') 245 #define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8') 246 #define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8') 247 #define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8') 248 #define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8') 249 250 /* 251 * 2 plane YCbCr 252 * index 0 = Y plane, [7:0] Y 253 * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian 254 * or 255 * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian 256 */ 257 #define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */ 258 #define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */ 259 #define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */ 260 #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */ 261 #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */ 262 #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */ 263 /* 264 * 2 plane YCbCr 265 * index 0 = Y plane, [39:0] Y3:Y2:Y1:Y0 little endian 266 * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian 267 */ 268 #define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */ 269 270 /* 271 * 2 plane YCbCr MSB aligned 272 * index 0 = Y plane, [15:0] Y:x [10:6] little endian 273 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian 274 */ 275 #define DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per channel */ 276 277 /* 278 * 2 plane YCbCr MSB aligned 279 * index 0 = Y plane, [15:0] Y:x [10:6] little endian 280 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian 281 */ 282 #define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */ 283 284 /* 285 * 2 plane YCbCr MSB aligned 286 * index 0 = Y plane, [15:0] Y:x [12:4] little endian 287 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian 288 */ 289 #define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */ 290 291 /* 292 * 2 plane YCbCr MSB aligned 293 * index 0 = Y plane, [15:0] Y little endian 294 * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian 295 */ 296 #define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */ 297 298 /* 3 plane non-subsampled (444) YCbCr 299 * 16 bits per component, but only 10 bits are used and 6 bits are padded 300 * index 0: Y plane, [15:0] Y:x [10:6] little endian 301 * index 1: Cb plane, [15:0] Cb:x [10:6] little endian 302 * index 2: Cr plane, [15:0] Cr:x [10:6] little endian 303 */ 304 #define DRM_FORMAT_Q410 fourcc_code('Q', '4', '1', '0') 305 306 /* 3 plane non-subsampled (444) YCrCb 307 * 16 bits per component, but only 10 bits are used and 6 bits are padded 308 * index 0: Y plane, [15:0] Y:x [10:6] little endian 309 * index 1: Cr plane, [15:0] Cr:x [10:6] little endian 310 * index 2: Cb plane, [15:0] Cb:x [10:6] little endian 311 */ 312 #define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1') 313 314 /* 315 * 3 plane YCbCr 316 * index 0: Y plane, [7:0] Y 317 * index 1: Cb plane, [7:0] Cb 318 * index 2: Cr plane, [7:0] Cr 319 * or 320 * index 1: Cr plane, [7:0] Cr 321 * index 2: Cb plane, [7:0] Cb 322 */ 323 #define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */ 324 #define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */ 325 #define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */ 326 #define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */ 327 #define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */ 328 #define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */ 329 #define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */ 330 #define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */ 331 #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */ 332 #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */ 333 334 335 /* 336 * Format Modifiers: 337 * 338 * Format modifiers describe, typically, a re-ordering or modification 339 * of the data in a plane of an FB. This can be used to express tiled/ 340 * swizzled formats, or compression, or a combination of the two. 341 * 342 * The upper 8 bits of the format modifier are a vendor-id as assigned 343 * below. The lower 56 bits are assigned as vendor sees fit. 344 */ 345 346 /* Vendor Ids: */ 347 #define DRM_FORMAT_MOD_NONE 0 348 #define DRM_FORMAT_MOD_VENDOR_NONE 0 349 #define DRM_FORMAT_MOD_VENDOR_INTEL 0x01 350 #define DRM_FORMAT_MOD_VENDOR_AMD 0x02 351 #define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03 352 #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 353 #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 354 #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06 355 #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07 356 #define DRM_FORMAT_MOD_VENDOR_ARM 0x08 357 #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09 358 #define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a 359 360 /* add more to the end as needed */ 361 362 #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1) 363 364 #define fourcc_mod_code(vendor, val) \ 365 ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL)) 366 367 /* 368 * Format Modifier tokens: 369 * 370 * When adding a new token please document the layout with a code comment, 371 * similar to the fourcc codes above. drm_fourcc.h is considered the 372 * authoritative source for all of these. 373 * 374 * Generic modifier names: 375 * 376 * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names 377 * for layouts which are common across multiple vendors. To preserve 378 * compatibility, in cases where a vendor-specific definition already exists and 379 * a generic name for it is desired, the common name is a purely symbolic alias 380 * and must use the same numerical value as the original definition. 381 * 382 * Note that generic names should only be used for modifiers which describe 383 * generic layouts (such as pixel re-ordering), which may have 384 * independently-developed support across multiple vendors. 385 * 386 * In future cases where a generic layout is identified before merging with a 387 * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor 388 * 'NONE' could be considered. This should only be for obvious, exceptional 389 * cases to avoid polluting the 'GENERIC' namespace with modifiers which only 390 * apply to a single vendor. 391 * 392 * Generic names should not be used for cases where multiple hardware vendors 393 * have implementations of the same standardised compression scheme (such as 394 * AFBC). In those cases, all implementations should use the same format 395 * modifier(s), reflecting the vendor of the standard. 396 */ 397 398 #define DRM_FORMAT_MOD_GENERIC_16_16_TILE DRM_FORMAT_MOD_SAMSUNG_16_16_TILE 399 400 /* 401 * Invalid Modifier 402 * 403 * This modifier can be used as a sentinel to terminate the format modifiers 404 * list, or to initialize a variable with an invalid modifier. It might also be 405 * used to report an error back to userspace for certain APIs. 406 */ 407 #define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED) 408 409 /* 410 * Linear Layout 411 * 412 * Just plain linear layout. Note that this is different from no specifying any 413 * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl), 414 * which tells the driver to also take driver-internal information into account 415 * and so might actually result in a tiled framebuffer. 416 */ 417 #define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0) 418 419 /* Intel framebuffer modifiers */ 420 421 /* 422 * Intel X-tiling layout 423 * 424 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) 425 * in row-major layout. Within the tile bytes are laid out row-major, with 426 * a platform-dependent stride. On top of that the memory can apply 427 * platform-depending swizzling of some higher address bits into bit6. 428 * 429 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets. 430 * On earlier platforms the is highly platforms specific and not useful for 431 * cross-driver sharing. It exists since on a given platform it does uniquely 432 * identify the layout in a simple way for i915-specific userspace, which 433 * facilitated conversion of userspace to modifiers. Additionally the exact 434 * format on some really old platforms is not known. 435 */ 436 #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1) 437 438 /* 439 * Intel Y-tiling layout 440 * 441 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) 442 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes) 443 * chunks column-major, with a platform-dependent height. On top of that the 444 * memory can apply platform-depending swizzling of some higher address bits 445 * into bit6. 446 * 447 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets. 448 * On earlier platforms the is highly platforms specific and not useful for 449 * cross-driver sharing. It exists since on a given platform it does uniquely 450 * identify the layout in a simple way for i915-specific userspace, which 451 * facilitated conversion of userspace to modifiers. Additionally the exact 452 * format on some really old platforms is not known. 453 */ 454 #define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2) 455 456 /* 457 * Intel Yf-tiling layout 458 * 459 * This is a tiled layout using 4Kb tiles in row-major layout. 460 * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which 461 * are arranged in four groups (two wide, two high) with column-major layout. 462 * Each group therefore consits out of four 256 byte units, which are also laid 463 * out as 2x2 column-major. 464 * 256 byte units are made out of four 64 byte blocks of pixels, producing 465 * either a square block or a 2:1 unit. 466 * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width 467 * in pixel depends on the pixel depth. 468 */ 469 #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3) 470 471 /* 472 * Intel color control surface (CCS) for render compression 473 * 474 * The framebuffer format must be one of the 8:8:8:8 RGB formats. 475 * The main surface will be plane index 0 and must be Y/Yf-tiled, 476 * the CCS will be plane index 1. 477 * 478 * Each CCS tile matches a 1024x512 pixel area of the main surface. 479 * To match certain aspects of the 3D hardware the CCS is 480 * considered to be made up of normal 128Bx32 Y tiles, Thus 481 * the CCS pitch must be specified in multiples of 128 bytes. 482 * 483 * In reality the CCS tile appears to be a 64Bx64 Y tile, composed 484 * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks. 485 * But that fact is not relevant unless the memory is accessed 486 * directly. 487 */ 488 #define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4) 489 #define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5) 490 491 /* 492 * Intel color control surfaces (CCS) for Gen-12 render compression. 493 * 494 * The main surface is Y-tiled and at plane index 0, the CCS is linear and 495 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in 496 * main surface. In other words, 4 bits in CCS map to a main surface cache 497 * line pair. The main surface pitch is required to be a multiple of four 498 * Y-tile widths. 499 */ 500 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6) 501 502 /* 503 * Intel color control surfaces (CCS) for Gen-12 media compression 504 * 505 * The main surface is Y-tiled and at plane index 0, the CCS is linear and 506 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in 507 * main surface. In other words, 4 bits in CCS map to a main surface cache 508 * line pair. The main surface pitch is required to be a multiple of four 509 * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the 510 * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces, 511 * planes 2 and 3 for the respective CCS. 512 */ 513 #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7) 514 515 /* 516 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks 517 * 518 * Macroblocks are laid in a Z-shape, and each pixel data is following the 519 * standard NV12 style. 520 * As for NV12, an image is the result of two frame buffers: one for Y, 521 * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer). 522 * Alignment requirements are (for each buffer): 523 * - multiple of 128 pixels for the width 524 * - multiple of 32 pixels for the height 525 * 526 * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html 527 */ 528 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1) 529 530 /* 531 * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks 532 * 533 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major 534 * layout. For YCbCr formats Cb/Cr components are taken in such a way that 535 * they correspond to their 16x16 luma block. 536 */ 537 #define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2) 538 539 /* 540 * Qualcomm Compressed Format 541 * 542 * Refers to a compressed variant of the base format that is compressed. 543 * Implementation may be platform and base-format specific. 544 * 545 * Each macrotile consists of m x n (mostly 4 x 4) tiles. 546 * Pixel data pitch/stride is aligned with macrotile width. 547 * Pixel data height is aligned with macrotile height. 548 * Entire pixel data buffer is aligned with 4k(bytes). 549 */ 550 #define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1) 551 552 /* Vivante framebuffer modifiers */ 553 554 /* 555 * Vivante 4x4 tiling layout 556 * 557 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major 558 * layout. 559 */ 560 #define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1) 561 562 /* 563 * Vivante 64x64 super-tiling layout 564 * 565 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile 566 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row- 567 * major layout. 568 * 569 * For more information: see 570 * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling 571 */ 572 #define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2) 573 574 /* 575 * Vivante 4x4 tiling layout for dual-pipe 576 * 577 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a 578 * different base address. Offsets from the base addresses are therefore halved 579 * compared to the non-split tiled layout. 580 */ 581 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3) 582 583 /* 584 * Vivante 64x64 super-tiling layout for dual-pipe 585 * 586 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile 587 * starts at a different base address. Offsets from the base addresses are 588 * therefore halved compared to the non-split super-tiled layout. 589 */ 590 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4) 591 592 /* NVIDIA frame buffer modifiers */ 593 594 /* 595 * Tegra Tiled Layout, used by Tegra 2, 3 and 4. 596 * 597 * Pixels are arranged in simple tiles of 16 x 16 bytes. 598 */ 599 #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1) 600 601 /* 602 * Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80, 603 * and Tegra GPUs starting with Tegra K1. 604 * 605 * Pixels are arranged in Groups of Bytes (GOBs). GOB size and layout varies 606 * based on the architecture generation. GOBs themselves are then arranged in 607 * 3D blocks, with the block dimensions (in terms of GOBs) always being a power 608 * of two, and hence expressible as their log2 equivalent (E.g., "2" represents 609 * a block depth or height of "4"). 610 * 611 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format 612 * in full detail. 613 * 614 * Macro 615 * Bits Param Description 616 * ---- ----- ----------------------------------------------------------------- 617 * 618 * 3:0 h log2(height) of each block, in GOBs. Placed here for 619 * compatibility with the existing 620 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers. 621 * 622 * 4:4 - Must be 1, to indicate block-linear layout. Necessary for 623 * compatibility with the existing 624 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers. 625 * 626 * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block 627 * size). Must be zero. 628 * 629 * Note there is no log2(width) parameter. Some portions of the 630 * hardware support a block width of two gobs, but it is impractical 631 * to use due to lack of support elsewhere, and has no known 632 * benefits. 633 * 634 * 11:9 - Reserved (To support 2D-array textures with variable array stride 635 * in blocks, specified via log2(tile width in blocks)). Must be 636 * zero. 637 * 638 * 19:12 k Page Kind. This value directly maps to a field in the page 639 * tables of all GPUs >= NV50. It affects the exact layout of bits 640 * in memory and can be derived from the tuple 641 * 642 * (format, GPU model, compression type, samples per pixel) 643 * 644 * Where compression type is defined below. If GPU model were 645 * implied by the format modifier, format, or memory buffer, page 646 * kind would not need to be included in the modifier itself, but 647 * since the modifier should define the layout of the associated 648 * memory buffer independent from any device or other context, it 649 * must be included here. 650 * 651 * 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed 652 * starting with Fermi GPUs. Additionally, the mapping between page 653 * kind and bit layout has changed at various points. 654 * 655 * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping 656 * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping 657 * 2 = Gob Height 8, Turing+ Page Kind mapping 658 * 3 = Reserved for future use. 659 * 660 * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further 661 * bit remapping step that occurs at an even lower level than the 662 * page kind and block linear swizzles. This causes the layout of 663 * surfaces mapped in those SOC's GPUs to be incompatible with the 664 * equivalent mapping on other GPUs in the same system. 665 * 666 * 0 = Tegra K1 - Tegra Parker/TX2 Layout. 667 * 1 = Desktop GPU and Tegra Xavier+ Layout 668 * 669 * 25:23 c Lossless Framebuffer Compression type. 670 * 671 * 0 = none 672 * 1 = ROP/3D, layout 1, exact compression format implied by Page 673 * Kind field 674 * 2 = ROP/3D, layout 2, exact compression format implied by Page 675 * Kind field 676 * 3 = CDE horizontal 677 * 4 = CDE vertical 678 * 5 = Reserved for future use 679 * 6 = Reserved for future use 680 * 7 = Reserved for future use 681 * 682 * 55:25 - Reserved for future use. Must be zero. 683 */ 684 #define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \ 685 fourcc_mod_code(NVIDIA, (0x10 | \ 686 ((h) & 0xf) | \ 687 (((k) & 0xff) << 12) | \ 688 (((g) & 0x3) << 20) | \ 689 (((s) & 0x1) << 22) | \ 690 (((c) & 0x7) << 23))) 691 692 /* To grandfather in prior block linear format modifiers to the above layout, 693 * the page kind "0", which corresponds to "pitch/linear" and hence is unusable 694 * with block-linear layouts, is remapped within drivers to the value 0xfe, 695 * which corresponds to the "generic" kind used for simple single-sample 696 * uncompressed color formats on Fermi - Volta GPUs. 697 */ 698 static inline __u64 699 drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) 700 { 701 if (!(modifier & 0x10) || (modifier & (0xff << 12))) 702 return modifier; 703 else 704 return modifier | (0xfe << 12); 705 } 706 707 /* 708 * 16Bx2 Block Linear layout, used by Tegra K1 and later 709 * 710 * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked 711 * vertically by a power of 2 (1 to 32 GOBs) to form a block. 712 * 713 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape. 714 * 715 * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically. 716 * Valid values are: 717 * 718 * 0 == ONE_GOB 719 * 1 == TWO_GOBS 720 * 2 == FOUR_GOBS 721 * 3 == EIGHT_GOBS 722 * 4 == SIXTEEN_GOBS 723 * 5 == THIRTYTWO_GOBS 724 * 725 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format 726 * in full detail. 727 */ 728 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \ 729 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v)) 730 731 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \ 732 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0) 733 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \ 734 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1) 735 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \ 736 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2) 737 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \ 738 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3) 739 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \ 740 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4) 741 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \ 742 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5) 743 744 /* 745 * Some Broadcom modifiers take parameters, for example the number of 746 * vertical lines in the image. Reserve the lower 32 bits for modifier 747 * type, and the next 24 bits for parameters. Top 8 bits are the 748 * vendor code. 749 */ 750 #define __fourcc_mod_broadcom_param_shift 8 751 #define __fourcc_mod_broadcom_param_bits 48 752 #define fourcc_mod_broadcom_code(val, params) \ 753 fourcc_mod_code(BROADCOM, ((((__u64)params) << __fourcc_mod_broadcom_param_shift) | val)) 754 #define fourcc_mod_broadcom_param(m) \ 755 ((int)(((m) >> __fourcc_mod_broadcom_param_shift) & \ 756 ((1ULL << __fourcc_mod_broadcom_param_bits) - 1))) 757 #define fourcc_mod_broadcom_mod(m) \ 758 ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \ 759 __fourcc_mod_broadcom_param_shift)) 760 761 /* 762 * Broadcom VC4 "T" format 763 * 764 * This is the primary layout that the V3D GPU can texture from (it 765 * can't do linear). The T format has: 766 * 767 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4 768 * pixels at 32 bit depth. 769 * 770 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually 771 * 16x16 pixels). 772 * 773 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On 774 * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows 775 * they're (TR, BR, BL, TL), where bottom left is start of memory. 776 * 777 * - an image made of 4k tiles in rows either left-to-right (even rows of 4k 778 * tiles) or right-to-left (odd rows of 4k tiles). 779 */ 780 #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1) 781 782 /* 783 * Broadcom SAND format 784 * 785 * This is the native format that the H.264 codec block uses. For VC4 786 * HVS, it is only valid for H.264 (NV12/21) and RGBA modes. 787 * 788 * The image can be considered to be split into columns, and the 789 * columns are placed consecutively into memory. The width of those 790 * columns can be either 32, 64, 128, or 256 pixels, but in practice 791 * only 128 pixel columns are used. 792 * 793 * The pitch between the start of each column is set to optimally 794 * switch between SDRAM banks. This is passed as the number of lines 795 * of column width in the modifier (we can't use the stride value due 796 * to various core checks that look at it , so you should set the 797 * stride to width*cpp). 798 * 799 * Note that the column height for this format modifier is the same 800 * for all of the planes, assuming that each column contains both Y 801 * and UV. Some SAND-using hardware stores UV in a separate tiled 802 * image from Y to reduce the column height, which is not supported 803 * with these modifiers. 804 */ 805 806 #define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \ 807 fourcc_mod_broadcom_code(2, v) 808 #define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \ 809 fourcc_mod_broadcom_code(3, v) 810 #define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \ 811 fourcc_mod_broadcom_code(4, v) 812 #define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \ 813 fourcc_mod_broadcom_code(5, v) 814 815 #define DRM_FORMAT_MOD_BROADCOM_SAND32 \ 816 DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0) 817 #define DRM_FORMAT_MOD_BROADCOM_SAND64 \ 818 DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0) 819 #define DRM_FORMAT_MOD_BROADCOM_SAND128 \ 820 DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0) 821 #define DRM_FORMAT_MOD_BROADCOM_SAND256 \ 822 DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0) 823 824 /* Broadcom UIF format 825 * 826 * This is the common format for the current Broadcom multimedia 827 * blocks, including V3D 3.x and newer, newer video codecs, and 828 * displays. 829 * 830 * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles), 831 * and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are 832 * stored in columns, with padding between the columns to ensure that 833 * moving from one column to the next doesn't hit the same SDRAM page 834 * bank. 835 * 836 * To calculate the padding, it is assumed that each hardware block 837 * and the software driving it knows the platform's SDRAM page size, 838 * number of banks, and XOR address, and that it's identical between 839 * all blocks using the format. This tiling modifier will use XOR as 840 * necessary to reduce the padding. If a hardware block can't do XOR, 841 * the assumption is that a no-XOR tiling modifier will be created. 842 */ 843 #define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6) 844 845 /* 846 * Arm Framebuffer Compression (AFBC) modifiers 847 * 848 * AFBC is a proprietary lossless image compression protocol and format. 849 * It provides fine-grained random access and minimizes the amount of data 850 * transferred between IP blocks. 851 * 852 * AFBC has several features which may be supported and/or used, which are 853 * represented using bits in the modifier. Not all combinations are valid, 854 * and different devices or use-cases may support different combinations. 855 * 856 * Further information on the use of AFBC modifiers can be found in 857 * Documentation/gpu/afbc.rst 858 */ 859 860 /* 861 * The top 4 bits (out of the 56 bits alloted for specifying vendor specific 862 * modifiers) denote the category for modifiers. Currently we have only two 863 * categories of modifiers ie AFBC and MISC. We can have a maximum of sixteen 864 * different categories. 865 */ 866 #define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \ 867 fourcc_mod_code(ARM, ((__u64)(__type) << 52) | ((__val) & 0x000fffffffffffffULL)) 868 869 #define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00 870 #define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01 871 872 #define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \ 873 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode) 874 875 /* 876 * AFBC superblock size 877 * 878 * Indicates the superblock size(s) used for the AFBC buffer. The buffer 879 * size (in pixels) must be aligned to a multiple of the superblock size. 880 * Four lowest significant bits(LSBs) are reserved for block size. 881 * 882 * Where one superblock size is specified, it applies to all planes of the 883 * buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified, 884 * the first applies to the Luma plane and the second applies to the Chroma 885 * plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma). 886 * Multiple superblock sizes are only valid for multi-plane YCbCr formats. 887 */ 888 #define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf 889 #define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL) 890 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL) 891 #define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4 (3ULL) 892 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL) 893 894 /* 895 * AFBC lossless colorspace transform 896 * 897 * Indicates that the buffer makes use of the AFBC lossless colorspace 898 * transform. 899 */ 900 #define AFBC_FORMAT_MOD_YTR (1ULL << 4) 901 902 /* 903 * AFBC block-split 904 * 905 * Indicates that the payload of each superblock is split. The second 906 * half of the payload is positioned at a predefined offset from the start 907 * of the superblock payload. 908 */ 909 #define AFBC_FORMAT_MOD_SPLIT (1ULL << 5) 910 911 /* 912 * AFBC sparse layout 913 * 914 * This flag indicates that the payload of each superblock must be stored at a 915 * predefined position relative to the other superblocks in the same AFBC 916 * buffer. This order is the same order used by the header buffer. In this mode 917 * each superblock is given the same amount of space as an uncompressed 918 * superblock of the particular format would require, rounding up to the next 919 * multiple of 128 bytes in size. 920 */ 921 #define AFBC_FORMAT_MOD_SPARSE (1ULL << 6) 922 923 /* 924 * AFBC copy-block restrict 925 * 926 * Buffers with this flag must obey the copy-block restriction. The restriction 927 * is such that there are no copy-blocks referring across the border of 8x8 928 * blocks. For the subsampled data the 8x8 limitation is also subsampled. 929 */ 930 #define AFBC_FORMAT_MOD_CBR (1ULL << 7) 931 932 /* 933 * AFBC tiled layout 934 * 935 * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all 936 * superblocks inside a tile are stored together in memory. 8x8 tiles are used 937 * for pixel formats up to and including 32 bpp while 4x4 tiles are used for 938 * larger bpp formats. The order between the tiles is scan line. 939 * When the tiled layout is used, the buffer size (in pixels) must be aligned 940 * to the tile size. 941 */ 942 #define AFBC_FORMAT_MOD_TILED (1ULL << 8) 943 944 /* 945 * AFBC solid color blocks 946 * 947 * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth 948 * can be reduced if a whole superblock is a single color. 949 */ 950 #define AFBC_FORMAT_MOD_SC (1ULL << 9) 951 952 /* 953 * AFBC double-buffer 954 * 955 * Indicates that the buffer is allocated in a layout safe for front-buffer 956 * rendering. 957 */ 958 #define AFBC_FORMAT_MOD_DB (1ULL << 10) 959 960 /* 961 * AFBC buffer content hints 962 * 963 * Indicates that the buffer includes per-superblock content hints. 964 */ 965 #define AFBC_FORMAT_MOD_BCH (1ULL << 11) 966 967 /* AFBC uncompressed storage mode 968 * 969 * Indicates that the buffer is using AFBC uncompressed storage mode. 970 * In this mode all superblock payloads in the buffer use the uncompressed 971 * storage mode, which is usually only used for data which cannot be compressed. 972 * The buffer layout is the same as for AFBC buffers without USM set, this only 973 * affects the storage mode of the individual superblocks. Note that even a 974 * buffer without USM set may use uncompressed storage mode for some or all 975 * superblocks, USM just guarantees it for all. 976 */ 977 #define AFBC_FORMAT_MOD_USM (1ULL << 12) 978 979 /* 980 * Arm 16x16 Block U-Interleaved modifier 981 * 982 * This is used by Arm Mali Utgard and Midgard GPUs. It divides the image 983 * into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels 984 * in the block are reordered. 985 */ 986 #define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \ 987 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL) 988 989 /* 990 * Allwinner tiled modifier 991 * 992 * This tiling mode is implemented by the VPU found on all Allwinner platforms, 993 * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3 994 * planes. 995 * 996 * With this tiling, the luminance samples are disposed in tiles representing 997 * 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels. 998 * The pixel order in each tile is linear and the tiles are disposed linearly, 999 * both in row-major order. 1000 */ 1001 #define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1) 1002 1003 /* 1004 * Amlogic Video Framebuffer Compression modifiers 1005 * 1006 * Amlogic uses a proprietary lossless image compression protocol and format 1007 * for their hardware video codec accelerators, either video decoders or 1008 * video input encoders. 1009 * 1010 * It considerably reduces memory bandwidth while writing and reading 1011 * frames in memory. 1012 * 1013 * The underlying storage is considered to be 3 components, 8bit or 10-bit 1014 * per component YCbCr 420, single plane : 1015 * - DRM_FORMAT_YUV420_8BIT 1016 * - DRM_FORMAT_YUV420_10BIT 1017 * 1018 * The first 8 bits of the mode defines the layout, then the following 8 bits 1019 * defines the options changing the layout. 1020 * 1021 * Not all combinations are valid, and different SoCs may support different 1022 * combinations of layout and options. 1023 */ 1024 #define __fourcc_mod_amlogic_layout_mask 0xf 1025 #define __fourcc_mod_amlogic_options_shift 8 1026 #define __fourcc_mod_amlogic_options_mask 0xf 1027 1028 #define DRM_FORMAT_MOD_AMLOGIC_FBC(__layout, __options) \ 1029 fourcc_mod_code(AMLOGIC, \ 1030 ((__layout) & __fourcc_mod_amlogic_layout_mask) | \ 1031 (((__options) & __fourcc_mod_amlogic_options_mask) \ 1032 << __fourcc_mod_amlogic_options_shift)) 1033 1034 /* Amlogic FBC Layouts */ 1035 1036 /* 1037 * Amlogic FBC Basic Layout 1038 * 1039 * The basic layout is composed of: 1040 * - a body content organized in 64x32 superblocks with 4096 bytes per 1041 * superblock in default mode. 1042 * - a 32 bytes per 128x64 header block 1043 * 1044 * This layout is transferrable between Amlogic SoCs supporting this modifier. 1045 */ 1046 #define AMLOGIC_FBC_LAYOUT_BASIC (1ULL) 1047 1048 /* 1049 * Amlogic FBC Scatter Memory layout 1050 * 1051 * Indicates the header contains IOMMU references to the compressed 1052 * frames content to optimize memory access and layout. 1053 * 1054 * In this mode, only the header memory address is needed, thus the 1055 * content memory organization is tied to the current producer 1056 * execution and cannot be saved/dumped neither transferrable between 1057 * Amlogic SoCs supporting this modifier. 1058 * 1059 * Due to the nature of the layout, these buffers are not expected to 1060 * be accessible by the user-space clients, but only accessible by the 1061 * hardware producers and consumers. 1062 * 1063 * The user-space clients should expect a failure while trying to mmap 1064 * the DMA-BUF handle returned by the producer. 1065 */ 1066 #define AMLOGIC_FBC_LAYOUT_SCATTER (2ULL) 1067 1068 /* Amlogic FBC Layout Options Bit Mask */ 1069 1070 /* 1071 * Amlogic FBC Memory Saving mode 1072 * 1073 * Indicates the storage is packed when pixel size is multiple of word 1074 * boudaries, i.e. 8bit should be stored in this mode to save allocation 1075 * memory. 1076 * 1077 * This mode reduces body layout to 3072 bytes per 64x32 superblock with 1078 * the basic layout and 3200 bytes per 64x32 superblock combined with 1079 * the scatter layout. 1080 */ 1081 #define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0) 1082 1083 #if defined(__cplusplus) 1084 } 1085 #endif 1086 1087 #endif /* DRM_FOURCC_H */ 1088