xref: /openbmc/linux/include/uapi/drm/drm_fourcc.h (revision 5b628549)
1 /*
2  * Copyright 2011 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  */
23 
24 #ifndef DRM_FOURCC_H
25 #define DRM_FOURCC_H
26 
27 #include "drm.h"
28 
29 #if defined(__cplusplus)
30 extern "C" {
31 #endif
32 
33 /**
34  * DOC: overview
35  *
36  * In the DRM subsystem, framebuffer pixel formats are described using the
37  * fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the
38  * fourcc code, a Format Modifier may optionally be provided, in order to
39  * further describe the buffer's format - for example tiling or compression.
40  *
41  * Format Modifiers
42  * ----------------
43  *
44  * Format modifiers are used in conjunction with a fourcc code, forming a
45  * unique fourcc:modifier pair. This format:modifier pair must fully define the
46  * format and data layout of the buffer, and should be the only way to describe
47  * that particular buffer.
48  *
49  * Having multiple fourcc:modifier pairs which describe the same layout should
50  * be avoided, as such aliases run the risk of different drivers exposing
51  * different names for the same data format, forcing userspace to understand
52  * that they are aliases.
53  *
54  * Format modifiers may change any property of the buffer, including the number
55  * of planes and/or the required allocation size. Format modifiers are
56  * vendor-namespaced, and as such the relationship between a fourcc code and a
57  * modifier is specific to the modifer being used. For example, some modifiers
58  * may preserve meaning - such as number of planes - from the fourcc code,
59  * whereas others may not.
60  *
61  * Vendors should document their modifier usage in as much detail as
62  * possible, to ensure maximum compatibility across devices, drivers and
63  * applications.
64  *
65  * The authoritative list of format modifier codes is found in
66  * `include/uapi/drm/drm_fourcc.h`
67  */
68 
69 #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
70 				 ((__u32)(c) << 16) | ((__u32)(d) << 24))
71 
72 #define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of little endian */
73 
74 /* Reserve 0 for the invalid format specifier */
75 #define DRM_FORMAT_INVALID	0
76 
77 /* color index */
78 #define DRM_FORMAT_C8		fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
79 
80 /* 8 bpp Red */
81 #define DRM_FORMAT_R8		fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
82 
83 /* 16 bpp Red */
84 #define DRM_FORMAT_R16		fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */
85 
86 /* 16 bpp RG */
87 #define DRM_FORMAT_RG88		fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */
88 #define DRM_FORMAT_GR88		fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */
89 
90 /* 32 bpp RG */
91 #define DRM_FORMAT_RG1616	fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */
92 #define DRM_FORMAT_GR1616	fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */
93 
94 /* 8 bpp RGB */
95 #define DRM_FORMAT_RGB332	fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
96 #define DRM_FORMAT_BGR233	fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
97 
98 /* 16 bpp RGB */
99 #define DRM_FORMAT_XRGB4444	fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */
100 #define DRM_FORMAT_XBGR4444	fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */
101 #define DRM_FORMAT_RGBX4444	fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */
102 #define DRM_FORMAT_BGRX4444	fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */
103 
104 #define DRM_FORMAT_ARGB4444	fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */
105 #define DRM_FORMAT_ABGR4444	fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */
106 #define DRM_FORMAT_RGBA4444	fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */
107 #define DRM_FORMAT_BGRA4444	fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */
108 
109 #define DRM_FORMAT_XRGB1555	fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */
110 #define DRM_FORMAT_XBGR1555	fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */
111 #define DRM_FORMAT_RGBX5551	fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */
112 #define DRM_FORMAT_BGRX5551	fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */
113 
114 #define DRM_FORMAT_ARGB1555	fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */
115 #define DRM_FORMAT_ABGR1555	fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */
116 #define DRM_FORMAT_RGBA5551	fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */
117 #define DRM_FORMAT_BGRA5551	fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */
118 
119 #define DRM_FORMAT_RGB565	fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */
120 #define DRM_FORMAT_BGR565	fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */
121 
122 /* 24 bpp RGB */
123 #define DRM_FORMAT_RGB888	fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */
124 #define DRM_FORMAT_BGR888	fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */
125 
126 /* 32 bpp RGB */
127 #define DRM_FORMAT_XRGB8888	fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */
128 #define DRM_FORMAT_XBGR8888	fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */
129 #define DRM_FORMAT_RGBX8888	fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */
130 #define DRM_FORMAT_BGRX8888	fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */
131 
132 #define DRM_FORMAT_ARGB8888	fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */
133 #define DRM_FORMAT_ABGR8888	fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */
134 #define DRM_FORMAT_RGBA8888	fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */
135 #define DRM_FORMAT_BGRA8888	fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */
136 
137 #define DRM_FORMAT_XRGB2101010	fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */
138 #define DRM_FORMAT_XBGR2101010	fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */
139 #define DRM_FORMAT_RGBX1010102	fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */
140 #define DRM_FORMAT_BGRX1010102	fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */
141 
142 #define DRM_FORMAT_ARGB2101010	fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */
143 #define DRM_FORMAT_ABGR2101010	fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */
144 #define DRM_FORMAT_RGBA1010102	fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
145 #define DRM_FORMAT_BGRA1010102	fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
146 
147 /* packed YCbCr */
148 #define DRM_FORMAT_YUYV		fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
149 #define DRM_FORMAT_YVYU		fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
150 #define DRM_FORMAT_UYVY		fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */
151 #define DRM_FORMAT_VYUY		fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
152 
153 #define DRM_FORMAT_AYUV		fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
154 #define DRM_FORMAT_XYUV8888		fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
155 
156 /*
157  * packed YCbCr420 2x2 tiled formats
158  * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile
159  */
160 /* [63:0]   A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0  1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
161 #define DRM_FORMAT_Y0L0		fourcc_code('Y', '0', 'L', '0')
162 /* [63:0]   X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0  1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
163 #define DRM_FORMAT_X0L0		fourcc_code('X', '0', 'L', '0')
164 
165 /* [63:0]   A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0  1:1:10:10:10:1:1:10:10:10 little endian */
166 #define DRM_FORMAT_Y0L2		fourcc_code('Y', '0', 'L', '2')
167 /* [63:0]   X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0  1:1:10:10:10:1:1:10:10:10 little endian */
168 #define DRM_FORMAT_X0L2		fourcc_code('X', '0', 'L', '2')
169 
170 /*
171  * 2 plane RGB + A
172  * index 0 = RGB plane, same format as the corresponding non _A8 format has
173  * index 1 = A plane, [7:0] A
174  */
175 #define DRM_FORMAT_XRGB8888_A8	fourcc_code('X', 'R', 'A', '8')
176 #define DRM_FORMAT_XBGR8888_A8	fourcc_code('X', 'B', 'A', '8')
177 #define DRM_FORMAT_RGBX8888_A8	fourcc_code('R', 'X', 'A', '8')
178 #define DRM_FORMAT_BGRX8888_A8	fourcc_code('B', 'X', 'A', '8')
179 #define DRM_FORMAT_RGB888_A8	fourcc_code('R', '8', 'A', '8')
180 #define DRM_FORMAT_BGR888_A8	fourcc_code('B', '8', 'A', '8')
181 #define DRM_FORMAT_RGB565_A8	fourcc_code('R', '5', 'A', '8')
182 #define DRM_FORMAT_BGR565_A8	fourcc_code('B', '5', 'A', '8')
183 
184 /*
185  * 2 plane YCbCr
186  * index 0 = Y plane, [7:0] Y
187  * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian
188  * or
189  * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian
190  */
191 #define DRM_FORMAT_NV12		fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */
192 #define DRM_FORMAT_NV21		fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */
193 #define DRM_FORMAT_NV16		fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */
194 #define DRM_FORMAT_NV61		fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
195 #define DRM_FORMAT_NV24		fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
196 #define DRM_FORMAT_NV42		fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
197 
198 /*
199  * 2 plane YCbCr MSB aligned
200  * index 0 = Y plane, [15:0] Y:x [10:6] little endian
201  * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
202  */
203 #define DRM_FORMAT_P010		fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */
204 
205 /*
206  * 2 plane YCbCr MSB aligned
207  * index 0 = Y plane, [15:0] Y:x [12:4] little endian
208  * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
209  */
210 #define DRM_FORMAT_P012		fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */
211 
212 /*
213  * 2 plane YCbCr MSB aligned
214  * index 0 = Y plane, [15:0] Y little endian
215  * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian
216  */
217 #define DRM_FORMAT_P016		fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
218 
219 /*
220  * 3 plane YCbCr
221  * index 0: Y plane, [7:0] Y
222  * index 1: Cb plane, [7:0] Cb
223  * index 2: Cr plane, [7:0] Cr
224  * or
225  * index 1: Cr plane, [7:0] Cr
226  * index 2: Cb plane, [7:0] Cb
227  */
228 #define DRM_FORMAT_YUV410	fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */
229 #define DRM_FORMAT_YVU410	fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */
230 #define DRM_FORMAT_YUV411	fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */
231 #define DRM_FORMAT_YVU411	fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */
232 #define DRM_FORMAT_YUV420	fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */
233 #define DRM_FORMAT_YVU420	fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */
234 #define DRM_FORMAT_YUV422	fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */
235 #define DRM_FORMAT_YVU422	fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */
236 #define DRM_FORMAT_YUV444	fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */
237 #define DRM_FORMAT_YVU444	fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */
238 
239 
240 /*
241  * Format Modifiers:
242  *
243  * Format modifiers describe, typically, a re-ordering or modification
244  * of the data in a plane of an FB.  This can be used to express tiled/
245  * swizzled formats, or compression, or a combination of the two.
246  *
247  * The upper 8 bits of the format modifier are a vendor-id as assigned
248  * below.  The lower 56 bits are assigned as vendor sees fit.
249  */
250 
251 /* Vendor Ids: */
252 #define DRM_FORMAT_MOD_NONE           0
253 #define DRM_FORMAT_MOD_VENDOR_NONE    0
254 #define DRM_FORMAT_MOD_VENDOR_INTEL   0x01
255 #define DRM_FORMAT_MOD_VENDOR_AMD     0x02
256 #define DRM_FORMAT_MOD_VENDOR_NVIDIA  0x03
257 #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
258 #define DRM_FORMAT_MOD_VENDOR_QCOM    0x05
259 #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
260 #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
261 #define DRM_FORMAT_MOD_VENDOR_ARM     0x08
262 #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09
263 
264 /* add more to the end as needed */
265 
266 #define DRM_FORMAT_RESERVED	      ((1ULL << 56) - 1)
267 
268 #define fourcc_mod_code(vendor, val) \
269 	((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL))
270 
271 /*
272  * Format Modifier tokens:
273  *
274  * When adding a new token please document the layout with a code comment,
275  * similar to the fourcc codes above. drm_fourcc.h is considered the
276  * authoritative source for all of these.
277  */
278 
279 /*
280  * Invalid Modifier
281  *
282  * This modifier can be used as a sentinel to terminate the format modifiers
283  * list, or to initialize a variable with an invalid modifier. It might also be
284  * used to report an error back to userspace for certain APIs.
285  */
286 #define DRM_FORMAT_MOD_INVALID	fourcc_mod_code(NONE, DRM_FORMAT_RESERVED)
287 
288 /*
289  * Linear Layout
290  *
291  * Just plain linear layout. Note that this is different from no specifying any
292  * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl),
293  * which tells the driver to also take driver-internal information into account
294  * and so might actually result in a tiled framebuffer.
295  */
296 #define DRM_FORMAT_MOD_LINEAR	fourcc_mod_code(NONE, 0)
297 
298 /* Intel framebuffer modifiers */
299 
300 /*
301  * Intel X-tiling layout
302  *
303  * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
304  * in row-major layout. Within the tile bytes are laid out row-major, with
305  * a platform-dependent stride. On top of that the memory can apply
306  * platform-depending swizzling of some higher address bits into bit6.
307  *
308  * This format is highly platforms specific and not useful for cross-driver
309  * sharing. It exists since on a given platform it does uniquely identify the
310  * layout in a simple way for i915-specific userspace.
311  */
312 #define I915_FORMAT_MOD_X_TILED	fourcc_mod_code(INTEL, 1)
313 
314 /*
315  * Intel Y-tiling layout
316  *
317  * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
318  * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
319  * chunks column-major, with a platform-dependent height. On top of that the
320  * memory can apply platform-depending swizzling of some higher address bits
321  * into bit6.
322  *
323  * This format is highly platforms specific and not useful for cross-driver
324  * sharing. It exists since on a given platform it does uniquely identify the
325  * layout in a simple way for i915-specific userspace.
326  */
327 #define I915_FORMAT_MOD_Y_TILED	fourcc_mod_code(INTEL, 2)
328 
329 /*
330  * Intel Yf-tiling layout
331  *
332  * This is a tiled layout using 4Kb tiles in row-major layout.
333  * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
334  * are arranged in four groups (two wide, two high) with column-major layout.
335  * Each group therefore consits out of four 256 byte units, which are also laid
336  * out as 2x2 column-major.
337  * 256 byte units are made out of four 64 byte blocks of pixels, producing
338  * either a square block or a 2:1 unit.
339  * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width
340  * in pixel depends on the pixel depth.
341  */
342 #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
343 
344 /*
345  * Intel color control surface (CCS) for render compression
346  *
347  * The framebuffer format must be one of the 8:8:8:8 RGB formats.
348  * The main surface will be plane index 0 and must be Y/Yf-tiled,
349  * the CCS will be plane index 1.
350  *
351  * Each CCS tile matches a 1024x512 pixel area of the main surface.
352  * To match certain aspects of the 3D hardware the CCS is
353  * considered to be made up of normal 128Bx32 Y tiles, Thus
354  * the CCS pitch must be specified in multiples of 128 bytes.
355  *
356  * In reality the CCS tile appears to be a 64Bx64 Y tile, composed
357  * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks.
358  * But that fact is not relevant unless the memory is accessed
359  * directly.
360  */
361 #define I915_FORMAT_MOD_Y_TILED_CCS	fourcc_mod_code(INTEL, 4)
362 #define I915_FORMAT_MOD_Yf_TILED_CCS	fourcc_mod_code(INTEL, 5)
363 
364 /*
365  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
366  *
367  * Macroblocks are laid in a Z-shape, and each pixel data is following the
368  * standard NV12 style.
369  * As for NV12, an image is the result of two frame buffers: one for Y,
370  * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer).
371  * Alignment requirements are (for each buffer):
372  * - multiple of 128 pixels for the width
373  * - multiple of  32 pixels for the height
374  *
375  * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html
376  */
377 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE	fourcc_mod_code(SAMSUNG, 1)
378 
379 /*
380  * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks
381  *
382  * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
383  * layout. For YCbCr formats Cb/Cr components are taken in such a way that
384  * they correspond to their 16x16 luma block.
385  */
386 #define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE	fourcc_mod_code(SAMSUNG, 2)
387 
388 /*
389  * Qualcomm Compressed Format
390  *
391  * Refers to a compressed variant of the base format that is compressed.
392  * Implementation may be platform and base-format specific.
393  *
394  * Each macrotile consists of m x n (mostly 4 x 4) tiles.
395  * Pixel data pitch/stride is aligned with macrotile width.
396  * Pixel data height is aligned with macrotile height.
397  * Entire pixel data buffer is aligned with 4k(bytes).
398  */
399 #define DRM_FORMAT_MOD_QCOM_COMPRESSED	fourcc_mod_code(QCOM, 1)
400 
401 /* Vivante framebuffer modifiers */
402 
403 /*
404  * Vivante 4x4 tiling layout
405  *
406  * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
407  * layout.
408  */
409 #define DRM_FORMAT_MOD_VIVANTE_TILED		fourcc_mod_code(VIVANTE, 1)
410 
411 /*
412  * Vivante 64x64 super-tiling layout
413  *
414  * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
415  * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
416  * major layout.
417  *
418  * For more information: see
419  * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
420  */
421 #define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED	fourcc_mod_code(VIVANTE, 2)
422 
423 /*
424  * Vivante 4x4 tiling layout for dual-pipe
425  *
426  * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
427  * different base address. Offsets from the base addresses are therefore halved
428  * compared to the non-split tiled layout.
429  */
430 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED	fourcc_mod_code(VIVANTE, 3)
431 
432 /*
433  * Vivante 64x64 super-tiling layout for dual-pipe
434  *
435  * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
436  * starts at a different base address. Offsets from the base addresses are
437  * therefore halved compared to the non-split super-tiled layout.
438  */
439 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
440 
441 /* NVIDIA frame buffer modifiers */
442 
443 /*
444  * Tegra Tiled Layout, used by Tegra 2, 3 and 4.
445  *
446  * Pixels are arranged in simple tiles of 16 x 16 bytes.
447  */
448 #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1)
449 
450 /*
451  * 16Bx2 Block Linear layout, used by desktop GPUs, and Tegra K1 and later
452  *
453  * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked
454  * vertically by a power of 2 (1 to 32 GOBs) to form a block.
455  *
456  * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
457  *
458  * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically.
459  * Valid values are:
460  *
461  * 0 == ONE_GOB
462  * 1 == TWO_GOBS
463  * 2 == FOUR_GOBS
464  * 3 == EIGHT_GOBS
465  * 4 == SIXTEEN_GOBS
466  * 5 == THIRTYTWO_GOBS
467  *
468  * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
469  * in full detail.
470  */
471 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \
472 	fourcc_mod_code(NVIDIA, 0x10 | ((v) & 0xf))
473 
474 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \
475 	fourcc_mod_code(NVIDIA, 0x10)
476 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \
477 	fourcc_mod_code(NVIDIA, 0x11)
478 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \
479 	fourcc_mod_code(NVIDIA, 0x12)
480 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \
481 	fourcc_mod_code(NVIDIA, 0x13)
482 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \
483 	fourcc_mod_code(NVIDIA, 0x14)
484 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \
485 	fourcc_mod_code(NVIDIA, 0x15)
486 
487 /*
488  * Some Broadcom modifiers take parameters, for example the number of
489  * vertical lines in the image. Reserve the lower 32 bits for modifier
490  * type, and the next 24 bits for parameters. Top 8 bits are the
491  * vendor code.
492  */
493 #define __fourcc_mod_broadcom_param_shift 8
494 #define __fourcc_mod_broadcom_param_bits 48
495 #define fourcc_mod_broadcom_code(val, params) \
496 	fourcc_mod_code(BROADCOM, ((((__u64)params) << __fourcc_mod_broadcom_param_shift) | val))
497 #define fourcc_mod_broadcom_param(m) \
498 	((int)(((m) >> __fourcc_mod_broadcom_param_shift) &	\
499 	       ((1ULL << __fourcc_mod_broadcom_param_bits) - 1)))
500 #define fourcc_mod_broadcom_mod(m) \
501 	((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) <<	\
502 		 __fourcc_mod_broadcom_param_shift))
503 
504 /*
505  * Broadcom VC4 "T" format
506  *
507  * This is the primary layout that the V3D GPU can texture from (it
508  * can't do linear).  The T format has:
509  *
510  * - 64b utiles of pixels in a raster-order grid according to cpp.  It's 4x4
511  *   pixels at 32 bit depth.
512  *
513  * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
514  *   16x16 pixels).
515  *
516  * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels).  On
517  *   even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows
518  *   they're (TR, BR, BL, TL), where bottom left is start of memory.
519  *
520  * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
521  *   tiles) or right-to-left (odd rows of 4k tiles).
522  */
523 #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
524 
525 /*
526  * Broadcom SAND format
527  *
528  * This is the native format that the H.264 codec block uses.  For VC4
529  * HVS, it is only valid for H.264 (NV12/21) and RGBA modes.
530  *
531  * The image can be considered to be split into columns, and the
532  * columns are placed consecutively into memory.  The width of those
533  * columns can be either 32, 64, 128, or 256 pixels, but in practice
534  * only 128 pixel columns are used.
535  *
536  * The pitch between the start of each column is set to optimally
537  * switch between SDRAM banks. This is passed as the number of lines
538  * of column width in the modifier (we can't use the stride value due
539  * to various core checks that look at it , so you should set the
540  * stride to width*cpp).
541  *
542  * Note that the column height for this format modifier is the same
543  * for all of the planes, assuming that each column contains both Y
544  * and UV.  Some SAND-using hardware stores UV in a separate tiled
545  * image from Y to reduce the column height, which is not supported
546  * with these modifiers.
547  */
548 
549 #define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \
550 	fourcc_mod_broadcom_code(2, v)
551 #define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \
552 	fourcc_mod_broadcom_code(3, v)
553 #define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \
554 	fourcc_mod_broadcom_code(4, v)
555 #define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \
556 	fourcc_mod_broadcom_code(5, v)
557 
558 #define DRM_FORMAT_MOD_BROADCOM_SAND32 \
559 	DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0)
560 #define DRM_FORMAT_MOD_BROADCOM_SAND64 \
561 	DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0)
562 #define DRM_FORMAT_MOD_BROADCOM_SAND128 \
563 	DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0)
564 #define DRM_FORMAT_MOD_BROADCOM_SAND256 \
565 	DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0)
566 
567 /* Broadcom UIF format
568  *
569  * This is the common format for the current Broadcom multimedia
570  * blocks, including V3D 3.x and newer, newer video codecs, and
571  * displays.
572  *
573  * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles),
574  * and macroblocks (4x4 UIF blocks).  Those 4x4 UIF block groups are
575  * stored in columns, with padding between the columns to ensure that
576  * moving from one column to the next doesn't hit the same SDRAM page
577  * bank.
578  *
579  * To calculate the padding, it is assumed that each hardware block
580  * and the software driving it knows the platform's SDRAM page size,
581  * number of banks, and XOR address, and that it's identical between
582  * all blocks using the format.  This tiling modifier will use XOR as
583  * necessary to reduce the padding.  If a hardware block can't do XOR,
584  * the assumption is that a no-XOR tiling modifier will be created.
585  */
586 #define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6)
587 
588 /*
589  * Arm Framebuffer Compression (AFBC) modifiers
590  *
591  * AFBC is a proprietary lossless image compression protocol and format.
592  * It provides fine-grained random access and minimizes the amount of data
593  * transferred between IP blocks.
594  *
595  * AFBC has several features which may be supported and/or used, which are
596  * represented using bits in the modifier. Not all combinations are valid,
597  * and different devices or use-cases may support different combinations.
598  *
599  * Further information on the use of AFBC modifiers can be found in
600  * Documentation/gpu/afbc.rst
601  */
602 #define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode)	fourcc_mod_code(ARM, __afbc_mode)
603 
604 /*
605  * AFBC superblock size
606  *
607  * Indicates the superblock size(s) used for the AFBC buffer. The buffer
608  * size (in pixels) must be aligned to a multiple of the superblock size.
609  * Four lowest significant bits(LSBs) are reserved for block size.
610  *
611  * Where one superblock size is specified, it applies to all planes of the
612  * buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified,
613  * the first applies to the Luma plane and the second applies to the Chroma
614  * plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma).
615  * Multiple superblock sizes are only valid for multi-plane YCbCr formats.
616  */
617 #define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK      0xf
618 #define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16     (1ULL)
619 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8      (2ULL)
620 #define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4      (3ULL)
621 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL)
622 
623 /*
624  * AFBC lossless colorspace transform
625  *
626  * Indicates that the buffer makes use of the AFBC lossless colorspace
627  * transform.
628  */
629 #define AFBC_FORMAT_MOD_YTR     (1ULL <<  4)
630 
631 /*
632  * AFBC block-split
633  *
634  * Indicates that the payload of each superblock is split. The second
635  * half of the payload is positioned at a predefined offset from the start
636  * of the superblock payload.
637  */
638 #define AFBC_FORMAT_MOD_SPLIT   (1ULL <<  5)
639 
640 /*
641  * AFBC sparse layout
642  *
643  * This flag indicates that the payload of each superblock must be stored at a
644  * predefined position relative to the other superblocks in the same AFBC
645  * buffer. This order is the same order used by the header buffer. In this mode
646  * each superblock is given the same amount of space as an uncompressed
647  * superblock of the particular format would require, rounding up to the next
648  * multiple of 128 bytes in size.
649  */
650 #define AFBC_FORMAT_MOD_SPARSE  (1ULL <<  6)
651 
652 /*
653  * AFBC copy-block restrict
654  *
655  * Buffers with this flag must obey the copy-block restriction. The restriction
656  * is such that there are no copy-blocks referring across the border of 8x8
657  * blocks. For the subsampled data the 8x8 limitation is also subsampled.
658  */
659 #define AFBC_FORMAT_MOD_CBR     (1ULL <<  7)
660 
661 /*
662  * AFBC tiled layout
663  *
664  * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all
665  * superblocks inside a tile are stored together in memory. 8x8 tiles are used
666  * for pixel formats up to and including 32 bpp while 4x4 tiles are used for
667  * larger bpp formats. The order between the tiles is scan line.
668  * When the tiled layout is used, the buffer size (in pixels) must be aligned
669  * to the tile size.
670  */
671 #define AFBC_FORMAT_MOD_TILED   (1ULL <<  8)
672 
673 /*
674  * AFBC solid color blocks
675  *
676  * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth
677  * can be reduced if a whole superblock is a single color.
678  */
679 #define AFBC_FORMAT_MOD_SC      (1ULL <<  9)
680 
681 /*
682  * AFBC double-buffer
683  *
684  * Indicates that the buffer is allocated in a layout safe for front-buffer
685  * rendering.
686  */
687 #define AFBC_FORMAT_MOD_DB      (1ULL << 10)
688 
689 /*
690  * AFBC buffer content hints
691  *
692  * Indicates that the buffer includes per-superblock content hints.
693  */
694 #define AFBC_FORMAT_MOD_BCH     (1ULL << 11)
695 
696 /*
697  * Allwinner tiled modifier
698  *
699  * This tiling mode is implemented by the VPU found on all Allwinner platforms,
700  * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3
701  * planes.
702  *
703  * With this tiling, the luminance samples are disposed in tiles representing
704  * 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels.
705  * The pixel order in each tile is linear and the tiles are disposed linearly,
706  * both in row-major order.
707  */
708 #define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1)
709 
710 #if defined(__cplusplus)
711 }
712 #endif
713 
714 #endif /* DRM_FOURCC_H */
715