1 /* 2 * Copyright 2011 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef DRM_FOURCC_H 25 #define DRM_FOURCC_H 26 27 #include "drm.h" 28 29 #if defined(__cplusplus) 30 extern "C" { 31 #endif 32 33 /** 34 * DOC: overview 35 * 36 * In the DRM subsystem, framebuffer pixel formats are described using the 37 * fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the 38 * fourcc code, a Format Modifier may optionally be provided, in order to 39 * further describe the buffer's format - for example tiling or compression. 40 * 41 * Format Modifiers 42 * ---------------- 43 * 44 * Format modifiers are used in conjunction with a fourcc code, forming a 45 * unique fourcc:modifier pair. This format:modifier pair must fully define the 46 * format and data layout of the buffer, and should be the only way to describe 47 * that particular buffer. 48 * 49 * Having multiple fourcc:modifier pairs which describe the same layout should 50 * be avoided, as such aliases run the risk of different drivers exposing 51 * different names for the same data format, forcing userspace to understand 52 * that they are aliases. 53 * 54 * Format modifiers may change any property of the buffer, including the number 55 * of planes and/or the required allocation size. Format modifiers are 56 * vendor-namespaced, and as such the relationship between a fourcc code and a 57 * modifier is specific to the modifer being used. For example, some modifiers 58 * may preserve meaning - such as number of planes - from the fourcc code, 59 * whereas others may not. 60 * 61 * Vendors should document their modifier usage in as much detail as 62 * possible, to ensure maximum compatibility across devices, drivers and 63 * applications. 64 * 65 * The authoritative list of format modifier codes is found in 66 * `include/uapi/drm/drm_fourcc.h` 67 */ 68 69 #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \ 70 ((__u32)(c) << 16) | ((__u32)(d) << 24)) 71 72 #define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of little endian */ 73 74 /* Reserve 0 for the invalid format specifier */ 75 #define DRM_FORMAT_INVALID 0 76 77 /* color index */ 78 #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */ 79 80 /* 8 bpp Red */ 81 #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */ 82 83 /* 16 bpp Red */ 84 #define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */ 85 86 /* 16 bpp RG */ 87 #define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */ 88 #define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */ 89 90 /* 32 bpp RG */ 91 #define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */ 92 #define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */ 93 94 /* 8 bpp RGB */ 95 #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */ 96 #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */ 97 98 /* 16 bpp RGB */ 99 #define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */ 100 #define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */ 101 #define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */ 102 #define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */ 103 104 #define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */ 105 #define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */ 106 #define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */ 107 #define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */ 108 109 #define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */ 110 #define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */ 111 #define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */ 112 #define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */ 113 114 #define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */ 115 #define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */ 116 #define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */ 117 #define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */ 118 119 #define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */ 120 #define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */ 121 122 /* 24 bpp RGB */ 123 #define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */ 124 #define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */ 125 126 /* 32 bpp RGB */ 127 #define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */ 128 #define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */ 129 #define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */ 130 #define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */ 131 132 #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */ 133 #define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */ 134 #define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */ 135 #define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */ 136 137 #define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */ 138 #define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */ 139 #define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */ 140 #define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */ 141 142 #define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */ 143 #define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */ 144 #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */ 145 #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */ 146 147 /* packed YCbCr */ 148 #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */ 149 #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */ 150 #define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */ 151 #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */ 152 153 #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */ 154 155 /* 156 * 2 plane RGB + A 157 * index 0 = RGB plane, same format as the corresponding non _A8 format has 158 * index 1 = A plane, [7:0] A 159 */ 160 #define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8') 161 #define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8') 162 #define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8') 163 #define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8') 164 #define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8') 165 #define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8') 166 #define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8') 167 #define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8') 168 169 /* 170 * 2 plane YCbCr 171 * index 0 = Y plane, [7:0] Y 172 * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian 173 * or 174 * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian 175 */ 176 #define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */ 177 #define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */ 178 #define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */ 179 #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */ 180 #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */ 181 #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */ 182 183 /* 184 * 3 plane YCbCr 185 * index 0: Y plane, [7:0] Y 186 * index 1: Cb plane, [7:0] Cb 187 * index 2: Cr plane, [7:0] Cr 188 * or 189 * index 1: Cr plane, [7:0] Cr 190 * index 2: Cb plane, [7:0] Cb 191 */ 192 #define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */ 193 #define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */ 194 #define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */ 195 #define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */ 196 #define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */ 197 #define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */ 198 #define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */ 199 #define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */ 200 #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */ 201 #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */ 202 203 204 /* 205 * Format Modifiers: 206 * 207 * Format modifiers describe, typically, a re-ordering or modification 208 * of the data in a plane of an FB. This can be used to express tiled/ 209 * swizzled formats, or compression, or a combination of the two. 210 * 211 * The upper 8 bits of the format modifier are a vendor-id as assigned 212 * below. The lower 56 bits are assigned as vendor sees fit. 213 */ 214 215 /* Vendor Ids: */ 216 #define DRM_FORMAT_MOD_NONE 0 217 #define DRM_FORMAT_MOD_VENDOR_NONE 0 218 #define DRM_FORMAT_MOD_VENDOR_INTEL 0x01 219 #define DRM_FORMAT_MOD_VENDOR_AMD 0x02 220 #define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03 221 #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 222 #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 223 #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06 224 #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07 225 #define DRM_FORMAT_MOD_VENDOR_ARM 0x08 226 /* add more to the end as needed */ 227 228 #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1) 229 230 #define fourcc_mod_code(vendor, val) \ 231 ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL)) 232 233 /* 234 * Format Modifier tokens: 235 * 236 * When adding a new token please document the layout with a code comment, 237 * similar to the fourcc codes above. drm_fourcc.h is considered the 238 * authoritative source for all of these. 239 */ 240 241 /* 242 * Invalid Modifier 243 * 244 * This modifier can be used as a sentinel to terminate the format modifiers 245 * list, or to initialize a variable with an invalid modifier. It might also be 246 * used to report an error back to userspace for certain APIs. 247 */ 248 #define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED) 249 250 /* 251 * Linear Layout 252 * 253 * Just plain linear layout. Note that this is different from no specifying any 254 * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl), 255 * which tells the driver to also take driver-internal information into account 256 * and so might actually result in a tiled framebuffer. 257 */ 258 #define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0) 259 260 /* Intel framebuffer modifiers */ 261 262 /* 263 * Intel X-tiling layout 264 * 265 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) 266 * in row-major layout. Within the tile bytes are laid out row-major, with 267 * a platform-dependent stride. On top of that the memory can apply 268 * platform-depending swizzling of some higher address bits into bit6. 269 * 270 * This format is highly platforms specific and not useful for cross-driver 271 * sharing. It exists since on a given platform it does uniquely identify the 272 * layout in a simple way for i915-specific userspace. 273 */ 274 #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1) 275 276 /* 277 * Intel Y-tiling layout 278 * 279 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) 280 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes) 281 * chunks column-major, with a platform-dependent height. On top of that the 282 * memory can apply platform-depending swizzling of some higher address bits 283 * into bit6. 284 * 285 * This format is highly platforms specific and not useful for cross-driver 286 * sharing. It exists since on a given platform it does uniquely identify the 287 * layout in a simple way for i915-specific userspace. 288 */ 289 #define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2) 290 291 /* 292 * Intel Yf-tiling layout 293 * 294 * This is a tiled layout using 4Kb tiles in row-major layout. 295 * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which 296 * are arranged in four groups (two wide, two high) with column-major layout. 297 * Each group therefore consits out of four 256 byte units, which are also laid 298 * out as 2x2 column-major. 299 * 256 byte units are made out of four 64 byte blocks of pixels, producing 300 * either a square block or a 2:1 unit. 301 * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width 302 * in pixel depends on the pixel depth. 303 */ 304 #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3) 305 306 /* 307 * Intel color control surface (CCS) for render compression 308 * 309 * The framebuffer format must be one of the 8:8:8:8 RGB formats. 310 * The main surface will be plane index 0 and must be Y/Yf-tiled, 311 * the CCS will be plane index 1. 312 * 313 * Each CCS tile matches a 1024x512 pixel area of the main surface. 314 * To match certain aspects of the 3D hardware the CCS is 315 * considered to be made up of normal 128Bx32 Y tiles, Thus 316 * the CCS pitch must be specified in multiples of 128 bytes. 317 * 318 * In reality the CCS tile appears to be a 64Bx64 Y tile, composed 319 * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks. 320 * But that fact is not relevant unless the memory is accessed 321 * directly. 322 */ 323 #define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4) 324 #define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5) 325 326 /* 327 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks 328 * 329 * Macroblocks are laid in a Z-shape, and each pixel data is following the 330 * standard NV12 style. 331 * As for NV12, an image is the result of two frame buffers: one for Y, 332 * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer). 333 * Alignment requirements are (for each buffer): 334 * - multiple of 128 pixels for the width 335 * - multiple of 32 pixels for the height 336 * 337 * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html 338 */ 339 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1) 340 341 /* 342 * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks 343 * 344 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major 345 * layout. For YCbCr formats Cb/Cr components are taken in such a way that 346 * they correspond to their 16x16 luma block. 347 */ 348 #define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2) 349 350 /* 351 * Qualcomm Compressed Format 352 * 353 * Refers to a compressed variant of the base format that is compressed. 354 * Implementation may be platform and base-format specific. 355 * 356 * Each macrotile consists of m x n (mostly 4 x 4) tiles. 357 * Pixel data pitch/stride is aligned with macrotile width. 358 * Pixel data height is aligned with macrotile height. 359 * Entire pixel data buffer is aligned with 4k(bytes). 360 */ 361 #define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1) 362 363 /* Vivante framebuffer modifiers */ 364 365 /* 366 * Vivante 4x4 tiling layout 367 * 368 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major 369 * layout. 370 */ 371 #define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1) 372 373 /* 374 * Vivante 64x64 super-tiling layout 375 * 376 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile 377 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row- 378 * major layout. 379 * 380 * For more information: see 381 * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling 382 */ 383 #define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2) 384 385 /* 386 * Vivante 4x4 tiling layout for dual-pipe 387 * 388 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a 389 * different base address. Offsets from the base addresses are therefore halved 390 * compared to the non-split tiled layout. 391 */ 392 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3) 393 394 /* 395 * Vivante 64x64 super-tiling layout for dual-pipe 396 * 397 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile 398 * starts at a different base address. Offsets from the base addresses are 399 * therefore halved compared to the non-split super-tiled layout. 400 */ 401 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4) 402 403 /* NVIDIA frame buffer modifiers */ 404 405 /* 406 * Tegra Tiled Layout, used by Tegra 2, 3 and 4. 407 * 408 * Pixels are arranged in simple tiles of 16 x 16 bytes. 409 */ 410 #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1) 411 412 /* 413 * 16Bx2 Block Linear layout, used by desktop GPUs, and Tegra K1 and later 414 * 415 * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked 416 * vertically by a power of 2 (1 to 32 GOBs) to form a block. 417 * 418 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape. 419 * 420 * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically. 421 * Valid values are: 422 * 423 * 0 == ONE_GOB 424 * 1 == TWO_GOBS 425 * 2 == FOUR_GOBS 426 * 3 == EIGHT_GOBS 427 * 4 == SIXTEEN_GOBS 428 * 5 == THIRTYTWO_GOBS 429 * 430 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format 431 * in full detail. 432 */ 433 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \ 434 fourcc_mod_code(NVIDIA, 0x10 | ((v) & 0xf)) 435 436 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \ 437 fourcc_mod_code(NVIDIA, 0x10) 438 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \ 439 fourcc_mod_code(NVIDIA, 0x11) 440 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \ 441 fourcc_mod_code(NVIDIA, 0x12) 442 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \ 443 fourcc_mod_code(NVIDIA, 0x13) 444 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \ 445 fourcc_mod_code(NVIDIA, 0x14) 446 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \ 447 fourcc_mod_code(NVIDIA, 0x15) 448 449 /* 450 * Some Broadcom modifiers take parameters, for example the number of 451 * vertical lines in the image. Reserve the lower 32 bits for modifier 452 * type, and the next 24 bits for parameters. Top 8 bits are the 453 * vendor code. 454 */ 455 #define __fourcc_mod_broadcom_param_shift 8 456 #define __fourcc_mod_broadcom_param_bits 48 457 #define fourcc_mod_broadcom_code(val, params) \ 458 fourcc_mod_code(BROADCOM, ((((__u64)params) << __fourcc_mod_broadcom_param_shift) | val)) 459 #define fourcc_mod_broadcom_param(m) \ 460 ((int)(((m) >> __fourcc_mod_broadcom_param_shift) & \ 461 ((1ULL << __fourcc_mod_broadcom_param_bits) - 1))) 462 #define fourcc_mod_broadcom_mod(m) \ 463 ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \ 464 __fourcc_mod_broadcom_param_shift)) 465 466 /* 467 * Broadcom VC4 "T" format 468 * 469 * This is the primary layout that the V3D GPU can texture from (it 470 * can't do linear). The T format has: 471 * 472 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4 473 * pixels at 32 bit depth. 474 * 475 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually 476 * 16x16 pixels). 477 * 478 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On 479 * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows 480 * they're (TR, BR, BL, TL), where bottom left is start of memory. 481 * 482 * - an image made of 4k tiles in rows either left-to-right (even rows of 4k 483 * tiles) or right-to-left (odd rows of 4k tiles). 484 */ 485 #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1) 486 487 /* 488 * Broadcom SAND format 489 * 490 * This is the native format that the H.264 codec block uses. For VC4 491 * HVS, it is only valid for H.264 (NV12/21) and RGBA modes. 492 * 493 * The image can be considered to be split into columns, and the 494 * columns are placed consecutively into memory. The width of those 495 * columns can be either 32, 64, 128, or 256 pixels, but in practice 496 * only 128 pixel columns are used. 497 * 498 * The pitch between the start of each column is set to optimally 499 * switch between SDRAM banks. This is passed as the number of lines 500 * of column width in the modifier (we can't use the stride value due 501 * to various core checks that look at it , so you should set the 502 * stride to width*cpp). 503 * 504 * Note that the column height for this format modifier is the same 505 * for all of the planes, assuming that each column contains both Y 506 * and UV. Some SAND-using hardware stores UV in a separate tiled 507 * image from Y to reduce the column height, which is not supported 508 * with these modifiers. 509 */ 510 511 #define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \ 512 fourcc_mod_broadcom_code(2, v) 513 #define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \ 514 fourcc_mod_broadcom_code(3, v) 515 #define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \ 516 fourcc_mod_broadcom_code(4, v) 517 #define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \ 518 fourcc_mod_broadcom_code(5, v) 519 520 #define DRM_FORMAT_MOD_BROADCOM_SAND32 \ 521 DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0) 522 #define DRM_FORMAT_MOD_BROADCOM_SAND64 \ 523 DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0) 524 #define DRM_FORMAT_MOD_BROADCOM_SAND128 \ 525 DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0) 526 #define DRM_FORMAT_MOD_BROADCOM_SAND256 \ 527 DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0) 528 529 /* Broadcom UIF format 530 * 531 * This is the common format for the current Broadcom multimedia 532 * blocks, including V3D 3.x and newer, newer video codecs, and 533 * displays. 534 * 535 * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles), 536 * and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are 537 * stored in columns, with padding between the columns to ensure that 538 * moving from one column to the next doesn't hit the same SDRAM page 539 * bank. 540 * 541 * To calculate the padding, it is assumed that each hardware block 542 * and the software driving it knows the platform's SDRAM page size, 543 * number of banks, and XOR address, and that it's identical between 544 * all blocks using the format. This tiling modifier will use XOR as 545 * necessary to reduce the padding. If a hardware block can't do XOR, 546 * the assumption is that a no-XOR tiling modifier will be created. 547 */ 548 #define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6) 549 550 /* 551 * Arm Framebuffer Compression (AFBC) modifiers 552 * 553 * AFBC is a proprietary lossless image compression protocol and format. 554 * It provides fine-grained random access and minimizes the amount of data 555 * transferred between IP blocks. 556 * 557 * AFBC has several features which may be supported and/or used, which are 558 * represented using bits in the modifier. Not all combinations are valid, 559 * and different devices or use-cases may support different combinations. 560 */ 561 #define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) fourcc_mod_code(ARM, __afbc_mode) 562 563 /* 564 * AFBC superblock size 565 * 566 * Indicates the superblock size(s) used for the AFBC buffer. The buffer 567 * size (in pixels) must be aligned to a multiple of the superblock size. 568 * Four lowest significant bits(LSBs) are reserved for block size. 569 */ 570 #define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf 571 #define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL) 572 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL) 573 574 /* 575 * AFBC lossless colorspace transform 576 * 577 * Indicates that the buffer makes use of the AFBC lossless colorspace 578 * transform. 579 */ 580 #define AFBC_FORMAT_MOD_YTR (1ULL << 4) 581 582 /* 583 * AFBC block-split 584 * 585 * Indicates that the payload of each superblock is split. The second 586 * half of the payload is positioned at a predefined offset from the start 587 * of the superblock payload. 588 */ 589 #define AFBC_FORMAT_MOD_SPLIT (1ULL << 5) 590 591 /* 592 * AFBC sparse layout 593 * 594 * This flag indicates that the payload of each superblock must be stored at a 595 * predefined position relative to the other superblocks in the same AFBC 596 * buffer. This order is the same order used by the header buffer. In this mode 597 * each superblock is given the same amount of space as an uncompressed 598 * superblock of the particular format would require, rounding up to the next 599 * multiple of 128 bytes in size. 600 */ 601 #define AFBC_FORMAT_MOD_SPARSE (1ULL << 6) 602 603 /* 604 * AFBC copy-block restrict 605 * 606 * Buffers with this flag must obey the copy-block restriction. The restriction 607 * is such that there are no copy-blocks referring across the border of 8x8 608 * blocks. For the subsampled data the 8x8 limitation is also subsampled. 609 */ 610 #define AFBC_FORMAT_MOD_CBR (1ULL << 7) 611 612 /* 613 * AFBC tiled layout 614 * 615 * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all 616 * superblocks inside a tile are stored together in memory. 8x8 tiles are used 617 * for pixel formats up to and including 32 bpp while 4x4 tiles are used for 618 * larger bpp formats. The order between the tiles is scan line. 619 * When the tiled layout is used, the buffer size (in pixels) must be aligned 620 * to the tile size. 621 */ 622 #define AFBC_FORMAT_MOD_TILED (1ULL << 8) 623 624 /* 625 * AFBC solid color blocks 626 * 627 * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth 628 * can be reduced if a whole superblock is a single color. 629 */ 630 #define AFBC_FORMAT_MOD_SC (1ULL << 9) 631 632 #if defined(__cplusplus) 633 } 634 #endif 635 636 #endif /* DRM_FOURCC_H */ 637