1 /* 2 * Copyright 2011 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef DRM_FOURCC_H 25 #define DRM_FOURCC_H 26 27 #include "drm.h" 28 29 #if defined(__cplusplus) 30 extern "C" { 31 #endif 32 33 /** 34 * DOC: overview 35 * 36 * In the DRM subsystem, framebuffer pixel formats are described using the 37 * fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the 38 * fourcc code, a Format Modifier may optionally be provided, in order to 39 * further describe the buffer's format - for example tiling or compression. 40 * 41 * Format Modifiers 42 * ---------------- 43 * 44 * Format modifiers are used in conjunction with a fourcc code, forming a 45 * unique fourcc:modifier pair. This format:modifier pair must fully define the 46 * format and data layout of the buffer, and should be the only way to describe 47 * that particular buffer. 48 * 49 * Having multiple fourcc:modifier pairs which describe the same layout should 50 * be avoided, as such aliases run the risk of different drivers exposing 51 * different names for the same data format, forcing userspace to understand 52 * that they are aliases. 53 * 54 * Format modifiers may change any property of the buffer, including the number 55 * of planes and/or the required allocation size. Format modifiers are 56 * vendor-namespaced, and as such the relationship between a fourcc code and a 57 * modifier is specific to the modifer being used. For example, some modifiers 58 * may preserve meaning - such as number of planes - from the fourcc code, 59 * whereas others may not. 60 * 61 * Modifiers must uniquely encode buffer layout. In other words, a buffer must 62 * match only a single modifier. A modifier must not be a subset of layouts of 63 * another modifier. For instance, it's incorrect to encode pitch alignment in 64 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel 65 * aligned modifier. That said, modifiers can have implicit minimal 66 * requirements. 67 * 68 * For modifiers where the combination of fourcc code and modifier can alias, 69 * a canonical pair needs to be defined and used by all drivers. Preferred 70 * combinations are also encouraged where all combinations might lead to 71 * confusion and unnecessarily reduced interoperability. An example for the 72 * latter is AFBC, where the ABGR layouts are preferred over ARGB layouts. 73 * 74 * There are two kinds of modifier users: 75 * 76 * - Kernel and user-space drivers: for drivers it's important that modifiers 77 * don't alias, otherwise two drivers might support the same format but use 78 * different aliases, preventing them from sharing buffers in an efficient 79 * format. 80 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users 81 * see modifiers as opaque tokens they can check for equality and intersect. 82 * These users musn't need to know to reason about the modifier value 83 * (i.e. they are not expected to extract information out of the modifier). 84 * 85 * Vendors should document their modifier usage in as much detail as 86 * possible, to ensure maximum compatibility across devices, drivers and 87 * applications. 88 * 89 * The authoritative list of format modifier codes is found in 90 * `include/uapi/drm/drm_fourcc.h` 91 */ 92 93 #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \ 94 ((__u32)(c) << 16) | ((__u32)(d) << 24)) 95 96 #define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */ 97 98 /* Reserve 0 for the invalid format specifier */ 99 #define DRM_FORMAT_INVALID 0 100 101 /* color index */ 102 #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */ 103 104 /* 8 bpp Red */ 105 #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */ 106 107 /* 16 bpp Red */ 108 #define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */ 109 110 /* 16 bpp RG */ 111 #define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */ 112 #define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */ 113 114 /* 32 bpp RG */ 115 #define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */ 116 #define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */ 117 118 /* 8 bpp RGB */ 119 #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */ 120 #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */ 121 122 /* 16 bpp RGB */ 123 #define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */ 124 #define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */ 125 #define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */ 126 #define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */ 127 128 #define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */ 129 #define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */ 130 #define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */ 131 #define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */ 132 133 #define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */ 134 #define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */ 135 #define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */ 136 #define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */ 137 138 #define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */ 139 #define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */ 140 #define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */ 141 #define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */ 142 143 #define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */ 144 #define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */ 145 146 /* 24 bpp RGB */ 147 #define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */ 148 #define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */ 149 150 /* 32 bpp RGB */ 151 #define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */ 152 #define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */ 153 #define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */ 154 #define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */ 155 156 #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */ 157 #define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */ 158 #define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */ 159 #define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */ 160 161 #define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */ 162 #define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */ 163 #define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */ 164 #define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */ 165 166 #define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */ 167 #define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */ 168 #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */ 169 #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */ 170 171 /* 64 bpp RGB */ 172 #define DRM_FORMAT_XRGB16161616 fourcc_code('X', 'R', '4', '8') /* [63:0] x:R:G:B 16:16:16:16 little endian */ 173 #define DRM_FORMAT_XBGR16161616 fourcc_code('X', 'B', '4', '8') /* [63:0] x:B:G:R 16:16:16:16 little endian */ 174 175 #define DRM_FORMAT_ARGB16161616 fourcc_code('A', 'R', '4', '8') /* [63:0] A:R:G:B 16:16:16:16 little endian */ 176 #define DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 little endian */ 177 178 /* 179 * Floating point 64bpp RGB 180 * IEEE 754-2008 binary16 half-precision float 181 * [15:0] sign:exponent:mantissa 1:5:10 182 */ 183 #define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */ 184 #define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */ 185 186 #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */ 187 #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */ 188 189 /* 190 * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits 191 * of unused padding per component: 192 */ 193 #define DRM_FORMAT_AXBXGXRX106106106106 fourcc_code('A', 'B', '1', '0') /* [63:0] A:x:B:x:G:x:R:x 10:6:10:6:10:6:10:6 little endian */ 194 195 /* packed YCbCr */ 196 #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */ 197 #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */ 198 #define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */ 199 #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */ 200 201 #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */ 202 #define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */ 203 #define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */ 204 #define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */ 205 206 /* 207 * packed Y2xx indicate for each component, xx valid data occupy msb 208 * 16-xx padding occupy lsb 209 */ 210 #define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little endian per 2 Y pixels */ 211 #define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */ 212 #define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16 little endian per 2 Y pixels */ 213 214 /* 215 * packed Y4xx indicate for each component, xx valid data occupy msb 216 * 16-xx padding occupy lsb except Y410 217 */ 218 #define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 little endian */ 219 #define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */ 220 #define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 little endian */ 221 222 #define DRM_FORMAT_XVYU2101010 fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 little endian */ 223 #define DRM_FORMAT_XVYU12_16161616 fourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */ 224 #define DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 little endian */ 225 226 /* 227 * packed YCbCr420 2x2 tiled formats 228 * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile 229 */ 230 /* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */ 231 #define DRM_FORMAT_Y0L0 fourcc_code('Y', '0', 'L', '0') 232 /* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */ 233 #define DRM_FORMAT_X0L0 fourcc_code('X', '0', 'L', '0') 234 235 /* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */ 236 #define DRM_FORMAT_Y0L2 fourcc_code('Y', '0', 'L', '2') 237 /* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */ 238 #define DRM_FORMAT_X0L2 fourcc_code('X', '0', 'L', '2') 239 240 /* 241 * 1-plane YUV 4:2:0 242 * In these formats, the component ordering is specified (Y, followed by U 243 * then V), but the exact Linear layout is undefined. 244 * These formats can only be used with a non-Linear modifier. 245 */ 246 #define DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8') 247 #define DRM_FORMAT_YUV420_10BIT fourcc_code('Y', 'U', '1', '0') 248 249 /* 250 * 2 plane RGB + A 251 * index 0 = RGB plane, same format as the corresponding non _A8 format has 252 * index 1 = A plane, [7:0] A 253 */ 254 #define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8') 255 #define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8') 256 #define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8') 257 #define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8') 258 #define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8') 259 #define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8') 260 #define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8') 261 #define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8') 262 263 /* 264 * 2 plane YCbCr 265 * index 0 = Y plane, [7:0] Y 266 * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian 267 * or 268 * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian 269 */ 270 #define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */ 271 #define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */ 272 #define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */ 273 #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */ 274 #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */ 275 #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */ 276 /* 277 * 2 plane YCbCr 278 * index 0 = Y plane, [39:0] Y3:Y2:Y1:Y0 little endian 279 * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian 280 */ 281 #define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */ 282 283 /* 284 * 2 plane YCbCr MSB aligned 285 * index 0 = Y plane, [15:0] Y:x [10:6] little endian 286 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian 287 */ 288 #define DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per channel */ 289 290 /* 291 * 2 plane YCbCr MSB aligned 292 * index 0 = Y plane, [15:0] Y:x [10:6] little endian 293 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian 294 */ 295 #define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */ 296 297 /* 298 * 2 plane YCbCr MSB aligned 299 * index 0 = Y plane, [15:0] Y:x [12:4] little endian 300 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian 301 */ 302 #define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */ 303 304 /* 305 * 2 plane YCbCr MSB aligned 306 * index 0 = Y plane, [15:0] Y little endian 307 * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian 308 */ 309 #define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */ 310 311 /* 3 plane non-subsampled (444) YCbCr 312 * 16 bits per component, but only 10 bits are used and 6 bits are padded 313 * index 0: Y plane, [15:0] Y:x [10:6] little endian 314 * index 1: Cb plane, [15:0] Cb:x [10:6] little endian 315 * index 2: Cr plane, [15:0] Cr:x [10:6] little endian 316 */ 317 #define DRM_FORMAT_Q410 fourcc_code('Q', '4', '1', '0') 318 319 /* 3 plane non-subsampled (444) YCrCb 320 * 16 bits per component, but only 10 bits are used and 6 bits are padded 321 * index 0: Y plane, [15:0] Y:x [10:6] little endian 322 * index 1: Cr plane, [15:0] Cr:x [10:6] little endian 323 * index 2: Cb plane, [15:0] Cb:x [10:6] little endian 324 */ 325 #define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1') 326 327 /* 328 * 3 plane YCbCr 329 * index 0: Y plane, [7:0] Y 330 * index 1: Cb plane, [7:0] Cb 331 * index 2: Cr plane, [7:0] Cr 332 * or 333 * index 1: Cr plane, [7:0] Cr 334 * index 2: Cb plane, [7:0] Cb 335 */ 336 #define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */ 337 #define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */ 338 #define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */ 339 #define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */ 340 #define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */ 341 #define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */ 342 #define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */ 343 #define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */ 344 #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */ 345 #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */ 346 347 348 /* 349 * Format Modifiers: 350 * 351 * Format modifiers describe, typically, a re-ordering or modification 352 * of the data in a plane of an FB. This can be used to express tiled/ 353 * swizzled formats, or compression, or a combination of the two. 354 * 355 * The upper 8 bits of the format modifier are a vendor-id as assigned 356 * below. The lower 56 bits are assigned as vendor sees fit. 357 */ 358 359 /* Vendor Ids: */ 360 #define DRM_FORMAT_MOD_VENDOR_NONE 0 361 #define DRM_FORMAT_MOD_VENDOR_INTEL 0x01 362 #define DRM_FORMAT_MOD_VENDOR_AMD 0x02 363 #define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03 364 #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 365 #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 366 #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06 367 #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07 368 #define DRM_FORMAT_MOD_VENDOR_ARM 0x08 369 #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09 370 #define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a 371 372 /* add more to the end as needed */ 373 374 #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1) 375 376 #define fourcc_mod_get_vendor(modifier) \ 377 (((modifier) >> 56) & 0xff) 378 379 #define fourcc_mod_is_vendor(modifier, vendor) \ 380 (fourcc_mod_get_vendor(modifier) == DRM_FORMAT_MOD_VENDOR_## vendor) 381 382 #define fourcc_mod_code(vendor, val) \ 383 ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL)) 384 385 /* 386 * Format Modifier tokens: 387 * 388 * When adding a new token please document the layout with a code comment, 389 * similar to the fourcc codes above. drm_fourcc.h is considered the 390 * authoritative source for all of these. 391 * 392 * Generic modifier names: 393 * 394 * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names 395 * for layouts which are common across multiple vendors. To preserve 396 * compatibility, in cases where a vendor-specific definition already exists and 397 * a generic name for it is desired, the common name is a purely symbolic alias 398 * and must use the same numerical value as the original definition. 399 * 400 * Note that generic names should only be used for modifiers which describe 401 * generic layouts (such as pixel re-ordering), which may have 402 * independently-developed support across multiple vendors. 403 * 404 * In future cases where a generic layout is identified before merging with a 405 * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor 406 * 'NONE' could be considered. This should only be for obvious, exceptional 407 * cases to avoid polluting the 'GENERIC' namespace with modifiers which only 408 * apply to a single vendor. 409 * 410 * Generic names should not be used for cases where multiple hardware vendors 411 * have implementations of the same standardised compression scheme (such as 412 * AFBC). In those cases, all implementations should use the same format 413 * modifier(s), reflecting the vendor of the standard. 414 */ 415 416 #define DRM_FORMAT_MOD_GENERIC_16_16_TILE DRM_FORMAT_MOD_SAMSUNG_16_16_TILE 417 418 /* 419 * Invalid Modifier 420 * 421 * This modifier can be used as a sentinel to terminate the format modifiers 422 * list, or to initialize a variable with an invalid modifier. It might also be 423 * used to report an error back to userspace for certain APIs. 424 */ 425 #define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED) 426 427 /* 428 * Linear Layout 429 * 430 * Just plain linear layout. Note that this is different from no specifying any 431 * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl), 432 * which tells the driver to also take driver-internal information into account 433 * and so might actually result in a tiled framebuffer. 434 */ 435 #define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0) 436 437 /* 438 * Deprecated: use DRM_FORMAT_MOD_LINEAR instead 439 * 440 * The "none" format modifier doesn't actually mean that the modifier is 441 * implicit, instead it means that the layout is linear. Whether modifiers are 442 * used is out-of-band information carried in an API-specific way (e.g. in a 443 * flag for drm_mode_fb_cmd2). 444 */ 445 #define DRM_FORMAT_MOD_NONE 0 446 447 /* Intel framebuffer modifiers */ 448 449 /* 450 * Intel X-tiling layout 451 * 452 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) 453 * in row-major layout. Within the tile bytes are laid out row-major, with 454 * a platform-dependent stride. On top of that the memory can apply 455 * platform-depending swizzling of some higher address bits into bit6. 456 * 457 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets. 458 * On earlier platforms the is highly platforms specific and not useful for 459 * cross-driver sharing. It exists since on a given platform it does uniquely 460 * identify the layout in a simple way for i915-specific userspace, which 461 * facilitated conversion of userspace to modifiers. Additionally the exact 462 * format on some really old platforms is not known. 463 */ 464 #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1) 465 466 /* 467 * Intel Y-tiling layout 468 * 469 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) 470 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes) 471 * chunks column-major, with a platform-dependent height. On top of that the 472 * memory can apply platform-depending swizzling of some higher address bits 473 * into bit6. 474 * 475 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets. 476 * On earlier platforms the is highly platforms specific and not useful for 477 * cross-driver sharing. It exists since on a given platform it does uniquely 478 * identify the layout in a simple way for i915-specific userspace, which 479 * facilitated conversion of userspace to modifiers. Additionally the exact 480 * format on some really old platforms is not known. 481 */ 482 #define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2) 483 484 /* 485 * Intel Yf-tiling layout 486 * 487 * This is a tiled layout using 4Kb tiles in row-major layout. 488 * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which 489 * are arranged in four groups (two wide, two high) with column-major layout. 490 * Each group therefore consits out of four 256 byte units, which are also laid 491 * out as 2x2 column-major. 492 * 256 byte units are made out of four 64 byte blocks of pixels, producing 493 * either a square block or a 2:1 unit. 494 * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width 495 * in pixel depends on the pixel depth. 496 */ 497 #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3) 498 499 /* 500 * Intel color control surface (CCS) for render compression 501 * 502 * The framebuffer format must be one of the 8:8:8:8 RGB formats. 503 * The main surface will be plane index 0 and must be Y/Yf-tiled, 504 * the CCS will be plane index 1. 505 * 506 * Each CCS tile matches a 1024x512 pixel area of the main surface. 507 * To match certain aspects of the 3D hardware the CCS is 508 * considered to be made up of normal 128Bx32 Y tiles, Thus 509 * the CCS pitch must be specified in multiples of 128 bytes. 510 * 511 * In reality the CCS tile appears to be a 64Bx64 Y tile, composed 512 * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks. 513 * But that fact is not relevant unless the memory is accessed 514 * directly. 515 */ 516 #define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4) 517 #define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5) 518 519 /* 520 * Intel color control surfaces (CCS) for Gen-12 render compression. 521 * 522 * The main surface is Y-tiled and at plane index 0, the CCS is linear and 523 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in 524 * main surface. In other words, 4 bits in CCS map to a main surface cache 525 * line pair. The main surface pitch is required to be a multiple of four 526 * Y-tile widths. 527 */ 528 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6) 529 530 /* 531 * Intel color control surfaces (CCS) for Gen-12 media compression 532 * 533 * The main surface is Y-tiled and at plane index 0, the CCS is linear and 534 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in 535 * main surface. In other words, 4 bits in CCS map to a main surface cache 536 * line pair. The main surface pitch is required to be a multiple of four 537 * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the 538 * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces, 539 * planes 2 and 3 for the respective CCS. 540 */ 541 #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7) 542 543 /* 544 * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render 545 * compression. 546 * 547 * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear 548 * and at index 1. The clear color is stored at index 2, and the pitch should 549 * be ignored. The clear color structure is 256 bits. The first 128 bits 550 * represents Raw Clear Color Red, Green, Blue and Alpha color each represented 551 * by 32 bits. The raw clear color is consumed by the 3d engine and generates 552 * the converted clear color of size 64 bits. The first 32 bits store the Lower 553 * Converted Clear Color value and the next 32 bits store the Higher Converted 554 * Clear Color value when applicable. The Converted Clear Color values are 555 * consumed by the DE. The last 64 bits are used to store Color Discard Enable 556 * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line 557 * corresponds to an area of 4x1 tiles in the main surface. The main surface 558 * pitch is required to be a multiple of 4 tile widths. 559 */ 560 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8) 561 562 /* 563 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks 564 * 565 * Macroblocks are laid in a Z-shape, and each pixel data is following the 566 * standard NV12 style. 567 * As for NV12, an image is the result of two frame buffers: one for Y, 568 * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer). 569 * Alignment requirements are (for each buffer): 570 * - multiple of 128 pixels for the width 571 * - multiple of 32 pixels for the height 572 * 573 * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html 574 */ 575 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1) 576 577 /* 578 * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks 579 * 580 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major 581 * layout. For YCbCr formats Cb/Cr components are taken in such a way that 582 * they correspond to their 16x16 luma block. 583 */ 584 #define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2) 585 586 /* 587 * Qualcomm Compressed Format 588 * 589 * Refers to a compressed variant of the base format that is compressed. 590 * Implementation may be platform and base-format specific. 591 * 592 * Each macrotile consists of m x n (mostly 4 x 4) tiles. 593 * Pixel data pitch/stride is aligned with macrotile width. 594 * Pixel data height is aligned with macrotile height. 595 * Entire pixel data buffer is aligned with 4k(bytes). 596 */ 597 #define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1) 598 599 /* Vivante framebuffer modifiers */ 600 601 /* 602 * Vivante 4x4 tiling layout 603 * 604 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major 605 * layout. 606 */ 607 #define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1) 608 609 /* 610 * Vivante 64x64 super-tiling layout 611 * 612 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile 613 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row- 614 * major layout. 615 * 616 * For more information: see 617 * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling 618 */ 619 #define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2) 620 621 /* 622 * Vivante 4x4 tiling layout for dual-pipe 623 * 624 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a 625 * different base address. Offsets from the base addresses are therefore halved 626 * compared to the non-split tiled layout. 627 */ 628 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3) 629 630 /* 631 * Vivante 64x64 super-tiling layout for dual-pipe 632 * 633 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile 634 * starts at a different base address. Offsets from the base addresses are 635 * therefore halved compared to the non-split super-tiled layout. 636 */ 637 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4) 638 639 /* NVIDIA frame buffer modifiers */ 640 641 /* 642 * Tegra Tiled Layout, used by Tegra 2, 3 and 4. 643 * 644 * Pixels are arranged in simple tiles of 16 x 16 bytes. 645 */ 646 #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1) 647 648 /* 649 * Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80, 650 * and Tegra GPUs starting with Tegra K1. 651 * 652 * Pixels are arranged in Groups of Bytes (GOBs). GOB size and layout varies 653 * based on the architecture generation. GOBs themselves are then arranged in 654 * 3D blocks, with the block dimensions (in terms of GOBs) always being a power 655 * of two, and hence expressible as their log2 equivalent (E.g., "2" represents 656 * a block depth or height of "4"). 657 * 658 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format 659 * in full detail. 660 * 661 * Macro 662 * Bits Param Description 663 * ---- ----- ----------------------------------------------------------------- 664 * 665 * 3:0 h log2(height) of each block, in GOBs. Placed here for 666 * compatibility with the existing 667 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers. 668 * 669 * 4:4 - Must be 1, to indicate block-linear layout. Necessary for 670 * compatibility with the existing 671 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers. 672 * 673 * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block 674 * size). Must be zero. 675 * 676 * Note there is no log2(width) parameter. Some portions of the 677 * hardware support a block width of two gobs, but it is impractical 678 * to use due to lack of support elsewhere, and has no known 679 * benefits. 680 * 681 * 11:9 - Reserved (To support 2D-array textures with variable array stride 682 * in blocks, specified via log2(tile width in blocks)). Must be 683 * zero. 684 * 685 * 19:12 k Page Kind. This value directly maps to a field in the page 686 * tables of all GPUs >= NV50. It affects the exact layout of bits 687 * in memory and can be derived from the tuple 688 * 689 * (format, GPU model, compression type, samples per pixel) 690 * 691 * Where compression type is defined below. If GPU model were 692 * implied by the format modifier, format, or memory buffer, page 693 * kind would not need to be included in the modifier itself, but 694 * since the modifier should define the layout of the associated 695 * memory buffer independent from any device or other context, it 696 * must be included here. 697 * 698 * 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed 699 * starting with Fermi GPUs. Additionally, the mapping between page 700 * kind and bit layout has changed at various points. 701 * 702 * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping 703 * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping 704 * 2 = Gob Height 8, Turing+ Page Kind mapping 705 * 3 = Reserved for future use. 706 * 707 * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further 708 * bit remapping step that occurs at an even lower level than the 709 * page kind and block linear swizzles. This causes the layout of 710 * surfaces mapped in those SOC's GPUs to be incompatible with the 711 * equivalent mapping on other GPUs in the same system. 712 * 713 * 0 = Tegra K1 - Tegra Parker/TX2 Layout. 714 * 1 = Desktop GPU and Tegra Xavier+ Layout 715 * 716 * 25:23 c Lossless Framebuffer Compression type. 717 * 718 * 0 = none 719 * 1 = ROP/3D, layout 1, exact compression format implied by Page 720 * Kind field 721 * 2 = ROP/3D, layout 2, exact compression format implied by Page 722 * Kind field 723 * 3 = CDE horizontal 724 * 4 = CDE vertical 725 * 5 = Reserved for future use 726 * 6 = Reserved for future use 727 * 7 = Reserved for future use 728 * 729 * 55:25 - Reserved for future use. Must be zero. 730 */ 731 #define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \ 732 fourcc_mod_code(NVIDIA, (0x10 | \ 733 ((h) & 0xf) | \ 734 (((k) & 0xff) << 12) | \ 735 (((g) & 0x3) << 20) | \ 736 (((s) & 0x1) << 22) | \ 737 (((c) & 0x7) << 23))) 738 739 /* To grandfather in prior block linear format modifiers to the above layout, 740 * the page kind "0", which corresponds to "pitch/linear" and hence is unusable 741 * with block-linear layouts, is remapped within drivers to the value 0xfe, 742 * which corresponds to the "generic" kind used for simple single-sample 743 * uncompressed color formats on Fermi - Volta GPUs. 744 */ 745 static inline __u64 746 drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) 747 { 748 if (!(modifier & 0x10) || (modifier & (0xff << 12))) 749 return modifier; 750 else 751 return modifier | (0xfe << 12); 752 } 753 754 /* 755 * 16Bx2 Block Linear layout, used by Tegra K1 and later 756 * 757 * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked 758 * vertically by a power of 2 (1 to 32 GOBs) to form a block. 759 * 760 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape. 761 * 762 * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically. 763 * Valid values are: 764 * 765 * 0 == ONE_GOB 766 * 1 == TWO_GOBS 767 * 2 == FOUR_GOBS 768 * 3 == EIGHT_GOBS 769 * 4 == SIXTEEN_GOBS 770 * 5 == THIRTYTWO_GOBS 771 * 772 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format 773 * in full detail. 774 */ 775 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \ 776 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v)) 777 778 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \ 779 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0) 780 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \ 781 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1) 782 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \ 783 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2) 784 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \ 785 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3) 786 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \ 787 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4) 788 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \ 789 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5) 790 791 /* 792 * Some Broadcom modifiers take parameters, for example the number of 793 * vertical lines in the image. Reserve the lower 32 bits for modifier 794 * type, and the next 24 bits for parameters. Top 8 bits are the 795 * vendor code. 796 */ 797 #define __fourcc_mod_broadcom_param_shift 8 798 #define __fourcc_mod_broadcom_param_bits 48 799 #define fourcc_mod_broadcom_code(val, params) \ 800 fourcc_mod_code(BROADCOM, ((((__u64)params) << __fourcc_mod_broadcom_param_shift) | val)) 801 #define fourcc_mod_broadcom_param(m) \ 802 ((int)(((m) >> __fourcc_mod_broadcom_param_shift) & \ 803 ((1ULL << __fourcc_mod_broadcom_param_bits) - 1))) 804 #define fourcc_mod_broadcom_mod(m) \ 805 ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \ 806 __fourcc_mod_broadcom_param_shift)) 807 808 /* 809 * Broadcom VC4 "T" format 810 * 811 * This is the primary layout that the V3D GPU can texture from (it 812 * can't do linear). The T format has: 813 * 814 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4 815 * pixels at 32 bit depth. 816 * 817 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually 818 * 16x16 pixels). 819 * 820 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On 821 * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows 822 * they're (TR, BR, BL, TL), where bottom left is start of memory. 823 * 824 * - an image made of 4k tiles in rows either left-to-right (even rows of 4k 825 * tiles) or right-to-left (odd rows of 4k tiles). 826 */ 827 #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1) 828 829 /* 830 * Broadcom SAND format 831 * 832 * This is the native format that the H.264 codec block uses. For VC4 833 * HVS, it is only valid for H.264 (NV12/21) and RGBA modes. 834 * 835 * The image can be considered to be split into columns, and the 836 * columns are placed consecutively into memory. The width of those 837 * columns can be either 32, 64, 128, or 256 pixels, but in practice 838 * only 128 pixel columns are used. 839 * 840 * The pitch between the start of each column is set to optimally 841 * switch between SDRAM banks. This is passed as the number of lines 842 * of column width in the modifier (we can't use the stride value due 843 * to various core checks that look at it , so you should set the 844 * stride to width*cpp). 845 * 846 * Note that the column height for this format modifier is the same 847 * for all of the planes, assuming that each column contains both Y 848 * and UV. Some SAND-using hardware stores UV in a separate tiled 849 * image from Y to reduce the column height, which is not supported 850 * with these modifiers. 851 */ 852 853 #define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \ 854 fourcc_mod_broadcom_code(2, v) 855 #define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \ 856 fourcc_mod_broadcom_code(3, v) 857 #define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \ 858 fourcc_mod_broadcom_code(4, v) 859 #define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \ 860 fourcc_mod_broadcom_code(5, v) 861 862 #define DRM_FORMAT_MOD_BROADCOM_SAND32 \ 863 DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0) 864 #define DRM_FORMAT_MOD_BROADCOM_SAND64 \ 865 DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0) 866 #define DRM_FORMAT_MOD_BROADCOM_SAND128 \ 867 DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0) 868 #define DRM_FORMAT_MOD_BROADCOM_SAND256 \ 869 DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0) 870 871 /* Broadcom UIF format 872 * 873 * This is the common format for the current Broadcom multimedia 874 * blocks, including V3D 3.x and newer, newer video codecs, and 875 * displays. 876 * 877 * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles), 878 * and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are 879 * stored in columns, with padding between the columns to ensure that 880 * moving from one column to the next doesn't hit the same SDRAM page 881 * bank. 882 * 883 * To calculate the padding, it is assumed that each hardware block 884 * and the software driving it knows the platform's SDRAM page size, 885 * number of banks, and XOR address, and that it's identical between 886 * all blocks using the format. This tiling modifier will use XOR as 887 * necessary to reduce the padding. If a hardware block can't do XOR, 888 * the assumption is that a no-XOR tiling modifier will be created. 889 */ 890 #define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6) 891 892 /* 893 * Arm Framebuffer Compression (AFBC) modifiers 894 * 895 * AFBC is a proprietary lossless image compression protocol and format. 896 * It provides fine-grained random access and minimizes the amount of data 897 * transferred between IP blocks. 898 * 899 * AFBC has several features which may be supported and/or used, which are 900 * represented using bits in the modifier. Not all combinations are valid, 901 * and different devices or use-cases may support different combinations. 902 * 903 * Further information on the use of AFBC modifiers can be found in 904 * Documentation/gpu/afbc.rst 905 */ 906 907 /* 908 * The top 4 bits (out of the 56 bits alloted for specifying vendor specific 909 * modifiers) denote the category for modifiers. Currently we have three 910 * categories of modifiers ie AFBC, MISC and AFRC. We can have a maximum of 911 * sixteen different categories. 912 */ 913 #define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \ 914 fourcc_mod_code(ARM, ((__u64)(__type) << 52) | ((__val) & 0x000fffffffffffffULL)) 915 916 #define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00 917 #define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01 918 919 #define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \ 920 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode) 921 922 /* 923 * AFBC superblock size 924 * 925 * Indicates the superblock size(s) used for the AFBC buffer. The buffer 926 * size (in pixels) must be aligned to a multiple of the superblock size. 927 * Four lowest significant bits(LSBs) are reserved for block size. 928 * 929 * Where one superblock size is specified, it applies to all planes of the 930 * buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified, 931 * the first applies to the Luma plane and the second applies to the Chroma 932 * plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma). 933 * Multiple superblock sizes are only valid for multi-plane YCbCr formats. 934 */ 935 #define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf 936 #define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL) 937 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL) 938 #define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4 (3ULL) 939 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL) 940 941 /* 942 * AFBC lossless colorspace transform 943 * 944 * Indicates that the buffer makes use of the AFBC lossless colorspace 945 * transform. 946 */ 947 #define AFBC_FORMAT_MOD_YTR (1ULL << 4) 948 949 /* 950 * AFBC block-split 951 * 952 * Indicates that the payload of each superblock is split. The second 953 * half of the payload is positioned at a predefined offset from the start 954 * of the superblock payload. 955 */ 956 #define AFBC_FORMAT_MOD_SPLIT (1ULL << 5) 957 958 /* 959 * AFBC sparse layout 960 * 961 * This flag indicates that the payload of each superblock must be stored at a 962 * predefined position relative to the other superblocks in the same AFBC 963 * buffer. This order is the same order used by the header buffer. In this mode 964 * each superblock is given the same amount of space as an uncompressed 965 * superblock of the particular format would require, rounding up to the next 966 * multiple of 128 bytes in size. 967 */ 968 #define AFBC_FORMAT_MOD_SPARSE (1ULL << 6) 969 970 /* 971 * AFBC copy-block restrict 972 * 973 * Buffers with this flag must obey the copy-block restriction. The restriction 974 * is such that there are no copy-blocks referring across the border of 8x8 975 * blocks. For the subsampled data the 8x8 limitation is also subsampled. 976 */ 977 #define AFBC_FORMAT_MOD_CBR (1ULL << 7) 978 979 /* 980 * AFBC tiled layout 981 * 982 * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all 983 * superblocks inside a tile are stored together in memory. 8x8 tiles are used 984 * for pixel formats up to and including 32 bpp while 4x4 tiles are used for 985 * larger bpp formats. The order between the tiles is scan line. 986 * When the tiled layout is used, the buffer size (in pixels) must be aligned 987 * to the tile size. 988 */ 989 #define AFBC_FORMAT_MOD_TILED (1ULL << 8) 990 991 /* 992 * AFBC solid color blocks 993 * 994 * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth 995 * can be reduced if a whole superblock is a single color. 996 */ 997 #define AFBC_FORMAT_MOD_SC (1ULL << 9) 998 999 /* 1000 * AFBC double-buffer 1001 * 1002 * Indicates that the buffer is allocated in a layout safe for front-buffer 1003 * rendering. 1004 */ 1005 #define AFBC_FORMAT_MOD_DB (1ULL << 10) 1006 1007 /* 1008 * AFBC buffer content hints 1009 * 1010 * Indicates that the buffer includes per-superblock content hints. 1011 */ 1012 #define AFBC_FORMAT_MOD_BCH (1ULL << 11) 1013 1014 /* AFBC uncompressed storage mode 1015 * 1016 * Indicates that the buffer is using AFBC uncompressed storage mode. 1017 * In this mode all superblock payloads in the buffer use the uncompressed 1018 * storage mode, which is usually only used for data which cannot be compressed. 1019 * The buffer layout is the same as for AFBC buffers without USM set, this only 1020 * affects the storage mode of the individual superblocks. Note that even a 1021 * buffer without USM set may use uncompressed storage mode for some or all 1022 * superblocks, USM just guarantees it for all. 1023 */ 1024 #define AFBC_FORMAT_MOD_USM (1ULL << 12) 1025 1026 /* 1027 * Arm Fixed-Rate Compression (AFRC) modifiers 1028 * 1029 * AFRC is a proprietary fixed rate image compression protocol and format, 1030 * designed to provide guaranteed bandwidth and memory footprint 1031 * reductions in graphics and media use-cases. 1032 * 1033 * AFRC buffers consist of one or more planes, with the same components 1034 * and meaning as an uncompressed buffer using the same pixel format. 1035 * 1036 * Within each plane, the pixel/luma/chroma values are grouped into 1037 * "coding unit" blocks which are individually compressed to a 1038 * fixed size (in bytes). All coding units within a given plane of a buffer 1039 * store the same number of values, and have the same compressed size. 1040 * 1041 * The coding unit size is configurable, allowing different rates of compression. 1042 * 1043 * The start of each AFRC buffer plane must be aligned to an alignment granule which 1044 * depends on the coding unit size. 1045 * 1046 * Coding Unit Size Plane Alignment 1047 * ---------------- --------------- 1048 * 16 bytes 1024 bytes 1049 * 24 bytes 512 bytes 1050 * 32 bytes 2048 bytes 1051 * 1052 * Coding units are grouped into paging tiles. AFRC buffer dimensions must be aligned 1053 * to a multiple of the paging tile dimensions. 1054 * The dimensions of each paging tile depend on whether the buffer is optimised for 1055 * scanline (SCAN layout) or rotated (ROT layout) access. 1056 * 1057 * Layout Paging Tile Width Paging Tile Height 1058 * ------ ----------------- ------------------ 1059 * SCAN 16 coding units 4 coding units 1060 * ROT 8 coding units 8 coding units 1061 * 1062 * The dimensions of each coding unit depend on the number of components 1063 * in the compressed plane and whether the buffer is optimised for 1064 * scanline (SCAN layout) or rotated (ROT layout) access. 1065 * 1066 * Number of Components in Plane Layout Coding Unit Width Coding Unit Height 1067 * ----------------------------- --------- ----------------- ------------------ 1068 * 1 SCAN 16 samples 4 samples 1069 * Example: 16x4 luma samples in a 'Y' plane 1070 * 16x4 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer 1071 * ----------------------------- --------- ----------------- ------------------ 1072 * 1 ROT 8 samples 8 samples 1073 * Example: 8x8 luma samples in a 'Y' plane 1074 * 8x8 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer 1075 * ----------------------------- --------- ----------------- ------------------ 1076 * 2 DONT CARE 8 samples 4 samples 1077 * Example: 8x4 chroma pairs in the 'UV' plane of a semi-planar YUV buffer 1078 * ----------------------------- --------- ----------------- ------------------ 1079 * 3 DONT CARE 4 samples 4 samples 1080 * Example: 4x4 pixels in an RGB buffer without alpha 1081 * ----------------------------- --------- ----------------- ------------------ 1082 * 4 DONT CARE 4 samples 4 samples 1083 * Example: 4x4 pixels in an RGB buffer with alpha 1084 */ 1085 1086 #define DRM_FORMAT_MOD_ARM_TYPE_AFRC 0x02 1087 1088 #define DRM_FORMAT_MOD_ARM_AFRC(__afrc_mode) \ 1089 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFRC, __afrc_mode) 1090 1091 /* 1092 * AFRC coding unit size modifier. 1093 * 1094 * Indicates the number of bytes used to store each compressed coding unit for 1095 * one or more planes in an AFRC encoded buffer. The coding unit size for chrominance 1096 * is the same for both Cb and Cr, which may be stored in separate planes. 1097 * 1098 * AFRC_FORMAT_MOD_CU_SIZE_P0 indicates the number of bytes used to store 1099 * each compressed coding unit in the first plane of the buffer. For RGBA buffers 1100 * this is the only plane, while for semi-planar and fully-planar YUV buffers, 1101 * this corresponds to the luma plane. 1102 * 1103 * AFRC_FORMAT_MOD_CU_SIZE_P12 indicates the number of bytes used to store 1104 * each compressed coding unit in the second and third planes in the buffer. 1105 * For semi-planar and fully-planar YUV buffers, this corresponds to the chroma plane(s). 1106 * 1107 * For single-plane buffers, AFRC_FORMAT_MOD_CU_SIZE_P0 must be specified 1108 * and AFRC_FORMAT_MOD_CU_SIZE_P12 must be zero. 1109 * For semi-planar and fully-planar buffers, both AFRC_FORMAT_MOD_CU_SIZE_P0 and 1110 * AFRC_FORMAT_MOD_CU_SIZE_P12 must be specified. 1111 */ 1112 #define AFRC_FORMAT_MOD_CU_SIZE_MASK 0xf 1113 #define AFRC_FORMAT_MOD_CU_SIZE_16 (1ULL) 1114 #define AFRC_FORMAT_MOD_CU_SIZE_24 (2ULL) 1115 #define AFRC_FORMAT_MOD_CU_SIZE_32 (3ULL) 1116 1117 #define AFRC_FORMAT_MOD_CU_SIZE_P0(__afrc_cu_size) (__afrc_cu_size) 1118 #define AFRC_FORMAT_MOD_CU_SIZE_P12(__afrc_cu_size) ((__afrc_cu_size) << 4) 1119 1120 /* 1121 * AFRC scanline memory layout. 1122 * 1123 * Indicates if the buffer uses the scanline-optimised layout 1124 * for an AFRC encoded buffer, otherwise, it uses the rotation-optimised layout. 1125 * The memory layout is the same for all planes. 1126 */ 1127 #define AFRC_FORMAT_MOD_LAYOUT_SCAN (1ULL << 8) 1128 1129 /* 1130 * Arm 16x16 Block U-Interleaved modifier 1131 * 1132 * This is used by Arm Mali Utgard and Midgard GPUs. It divides the image 1133 * into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels 1134 * in the block are reordered. 1135 */ 1136 #define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \ 1137 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL) 1138 1139 /* 1140 * Allwinner tiled modifier 1141 * 1142 * This tiling mode is implemented by the VPU found on all Allwinner platforms, 1143 * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3 1144 * planes. 1145 * 1146 * With this tiling, the luminance samples are disposed in tiles representing 1147 * 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels. 1148 * The pixel order in each tile is linear and the tiles are disposed linearly, 1149 * both in row-major order. 1150 */ 1151 #define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1) 1152 1153 /* 1154 * Amlogic Video Framebuffer Compression modifiers 1155 * 1156 * Amlogic uses a proprietary lossless image compression protocol and format 1157 * for their hardware video codec accelerators, either video decoders or 1158 * video input encoders. 1159 * 1160 * It considerably reduces memory bandwidth while writing and reading 1161 * frames in memory. 1162 * 1163 * The underlying storage is considered to be 3 components, 8bit or 10-bit 1164 * per component YCbCr 420, single plane : 1165 * - DRM_FORMAT_YUV420_8BIT 1166 * - DRM_FORMAT_YUV420_10BIT 1167 * 1168 * The first 8 bits of the mode defines the layout, then the following 8 bits 1169 * defines the options changing the layout. 1170 * 1171 * Not all combinations are valid, and different SoCs may support different 1172 * combinations of layout and options. 1173 */ 1174 #define __fourcc_mod_amlogic_layout_mask 0xff 1175 #define __fourcc_mod_amlogic_options_shift 8 1176 #define __fourcc_mod_amlogic_options_mask 0xff 1177 1178 #define DRM_FORMAT_MOD_AMLOGIC_FBC(__layout, __options) \ 1179 fourcc_mod_code(AMLOGIC, \ 1180 ((__layout) & __fourcc_mod_amlogic_layout_mask) | \ 1181 (((__options) & __fourcc_mod_amlogic_options_mask) \ 1182 << __fourcc_mod_amlogic_options_shift)) 1183 1184 /* Amlogic FBC Layouts */ 1185 1186 /* 1187 * Amlogic FBC Basic Layout 1188 * 1189 * The basic layout is composed of: 1190 * - a body content organized in 64x32 superblocks with 4096 bytes per 1191 * superblock in default mode. 1192 * - a 32 bytes per 128x64 header block 1193 * 1194 * This layout is transferrable between Amlogic SoCs supporting this modifier. 1195 */ 1196 #define AMLOGIC_FBC_LAYOUT_BASIC (1ULL) 1197 1198 /* 1199 * Amlogic FBC Scatter Memory layout 1200 * 1201 * Indicates the header contains IOMMU references to the compressed 1202 * frames content to optimize memory access and layout. 1203 * 1204 * In this mode, only the header memory address is needed, thus the 1205 * content memory organization is tied to the current producer 1206 * execution and cannot be saved/dumped neither transferrable between 1207 * Amlogic SoCs supporting this modifier. 1208 * 1209 * Due to the nature of the layout, these buffers are not expected to 1210 * be accessible by the user-space clients, but only accessible by the 1211 * hardware producers and consumers. 1212 * 1213 * The user-space clients should expect a failure while trying to mmap 1214 * the DMA-BUF handle returned by the producer. 1215 */ 1216 #define AMLOGIC_FBC_LAYOUT_SCATTER (2ULL) 1217 1218 /* Amlogic FBC Layout Options Bit Mask */ 1219 1220 /* 1221 * Amlogic FBC Memory Saving mode 1222 * 1223 * Indicates the storage is packed when pixel size is multiple of word 1224 * boudaries, i.e. 8bit should be stored in this mode to save allocation 1225 * memory. 1226 * 1227 * This mode reduces body layout to 3072 bytes per 64x32 superblock with 1228 * the basic layout and 3200 bytes per 64x32 superblock combined with 1229 * the scatter layout. 1230 */ 1231 #define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0) 1232 1233 /* 1234 * AMD modifiers 1235 * 1236 * Memory layout: 1237 * 1238 * without DCC: 1239 * - main surface 1240 * 1241 * with DCC & without DCC_RETILE: 1242 * - main surface in plane 0 1243 * - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set) 1244 * 1245 * with DCC & DCC_RETILE: 1246 * - main surface in plane 0 1247 * - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned) 1248 * - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned) 1249 * 1250 * For multi-plane formats the above surfaces get merged into one plane for 1251 * each format plane, based on the required alignment only. 1252 * 1253 * Bits Parameter Notes 1254 * ----- ------------------------ --------------------------------------------- 1255 * 1256 * 7:0 TILE_VERSION Values are AMD_FMT_MOD_TILE_VER_* 1257 * 12:8 TILE Values are AMD_FMT_MOD_TILE_<version>_* 1258 * 13 DCC 1259 * 14 DCC_RETILE 1260 * 15 DCC_PIPE_ALIGN 1261 * 16 DCC_INDEPENDENT_64B 1262 * 17 DCC_INDEPENDENT_128B 1263 * 19:18 DCC_MAX_COMPRESSED_BLOCK Values are AMD_FMT_MOD_DCC_BLOCK_* 1264 * 20 DCC_CONSTANT_ENCODE 1265 * 23:21 PIPE_XOR_BITS Only for some chips 1266 * 26:24 BANK_XOR_BITS Only for some chips 1267 * 29:27 PACKERS Only for some chips 1268 * 32:30 RB Only for some chips 1269 * 35:33 PIPE Only for some chips 1270 * 55:36 - Reserved for future use, must be zero 1271 */ 1272 #define AMD_FMT_MOD fourcc_mod_code(AMD, 0) 1273 1274 #define IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD) 1275 1276 /* Reserve 0 for GFX8 and older */ 1277 #define AMD_FMT_MOD_TILE_VER_GFX9 1 1278 #define AMD_FMT_MOD_TILE_VER_GFX10 2 1279 #define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3 1280 1281 /* 1282 * 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical 1283 * version. 1284 */ 1285 #define AMD_FMT_MOD_TILE_GFX9_64K_S 9 1286 1287 /* 1288 * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has 1289 * GFX9 as canonical version. 1290 */ 1291 #define AMD_FMT_MOD_TILE_GFX9_64K_D 10 1292 #define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25 1293 #define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26 1294 #define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27 1295 1296 #define AMD_FMT_MOD_DCC_BLOCK_64B 0 1297 #define AMD_FMT_MOD_DCC_BLOCK_128B 1 1298 #define AMD_FMT_MOD_DCC_BLOCK_256B 2 1299 1300 #define AMD_FMT_MOD_TILE_VERSION_SHIFT 0 1301 #define AMD_FMT_MOD_TILE_VERSION_MASK 0xFF 1302 #define AMD_FMT_MOD_TILE_SHIFT 8 1303 #define AMD_FMT_MOD_TILE_MASK 0x1F 1304 1305 /* Whether DCC compression is enabled. */ 1306 #define AMD_FMT_MOD_DCC_SHIFT 13 1307 #define AMD_FMT_MOD_DCC_MASK 0x1 1308 1309 /* 1310 * Whether to include two DCC surfaces, one which is rb & pipe aligned, and 1311 * one which is not-aligned. 1312 */ 1313 #define AMD_FMT_MOD_DCC_RETILE_SHIFT 14 1314 #define AMD_FMT_MOD_DCC_RETILE_MASK 0x1 1315 1316 /* Only set if DCC_RETILE = false */ 1317 #define AMD_FMT_MOD_DCC_PIPE_ALIGN_SHIFT 15 1318 #define AMD_FMT_MOD_DCC_PIPE_ALIGN_MASK 0x1 1319 1320 #define AMD_FMT_MOD_DCC_INDEPENDENT_64B_SHIFT 16 1321 #define AMD_FMT_MOD_DCC_INDEPENDENT_64B_MASK 0x1 1322 #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17 1323 #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1 1324 #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18 1325 #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 1326 1327 /* 1328 * DCC supports embedding some clear colors directly in the DCC surface. 1329 * However, on older GPUs the rendering HW ignores the embedded clear color 1330 * and prefers the driver provided color. This necessitates doing a fastclear 1331 * eliminate operation before a process transfers control. 1332 * 1333 * If this bit is set that means the fastclear eliminate is not needed for these 1334 * embeddable colors. 1335 */ 1336 #define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20 1337 #define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1 1338 1339 /* 1340 * The below fields are for accounting for per GPU differences. These are only 1341 * relevant for GFX9 and later and if the tile field is *_X/_T. 1342 * 1343 * PIPE_XOR_BITS = always needed 1344 * BANK_XOR_BITS = only for TILE_VER_GFX9 1345 * PACKERS = only for TILE_VER_GFX10_RBPLUS 1346 * RB = only for TILE_VER_GFX9 & DCC 1347 * PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE | DCC_PIPE_ALIGN) 1348 */ 1349 #define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21 1350 #define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7 1351 #define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24 1352 #define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7 1353 #define AMD_FMT_MOD_PACKERS_SHIFT 27 1354 #define AMD_FMT_MOD_PACKERS_MASK 0x7 1355 #define AMD_FMT_MOD_RB_SHIFT 30 1356 #define AMD_FMT_MOD_RB_MASK 0x7 1357 #define AMD_FMT_MOD_PIPE_SHIFT 33 1358 #define AMD_FMT_MOD_PIPE_MASK 0x7 1359 1360 #define AMD_FMT_MOD_SET(field, value) \ 1361 ((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT) 1362 #define AMD_FMT_MOD_GET(field, value) \ 1363 (((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK) 1364 #define AMD_FMT_MOD_CLEAR(field) \ 1365 (~((uint64_t)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT)) 1366 1367 #if defined(__cplusplus) 1368 } 1369 #endif 1370 1371 #endif /* DRM_FOURCC_H */ 1372