1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2 /* 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * Copyright(c) 2018 Intel Corporation. All rights reserved. 7 */ 8 9 #ifndef __INCLUDE_SOUND_SOF_TOPOLOGY_H__ 10 #define __INCLUDE_SOUND_SOF_TOPOLOGY_H__ 11 12 #include <sound/sof/header.h> 13 14 /* 15 * Component 16 */ 17 18 /* types of component */ 19 enum sof_comp_type { 20 SOF_COMP_NONE = 0, 21 SOF_COMP_HOST, 22 SOF_COMP_DAI, 23 SOF_COMP_SG_HOST, /**< scatter gather variant */ 24 SOF_COMP_SG_DAI, /**< scatter gather variant */ 25 SOF_COMP_VOLUME, 26 SOF_COMP_MIXER, 27 SOF_COMP_MUX, 28 SOF_COMP_SRC, 29 SOF_COMP_SPLITTER, 30 SOF_COMP_TONE, 31 SOF_COMP_SWITCH, 32 SOF_COMP_BUFFER, 33 SOF_COMP_EQ_IIR, 34 SOF_COMP_EQ_FIR, 35 SOF_COMP_KEYWORD_DETECT, 36 SOF_COMP_KPB, /* A key phrase buffer component */ 37 SOF_COMP_SELECTOR, /**< channel selector component */ 38 SOF_COMP_DEMUX, 39 SOF_COMP_ASRC, /**< Asynchronous sample rate converter */ 40 SOF_COMP_DCBLOCK, 41 /* keep FILEREAD/FILEWRITE as the last ones */ 42 SOF_COMP_FILEREAD = 10000, /**< host test based file IO */ 43 SOF_COMP_FILEWRITE = 10001, /**< host test based file IO */ 44 }; 45 46 /* XRUN action for component */ 47 #define SOF_XRUN_STOP 1 /**< stop stream */ 48 #define SOF_XRUN_UNDER_ZERO 2 /**< send 0s to sink */ 49 #define SOF_XRUN_OVER_NULL 4 /**< send data to NULL */ 50 51 /* create new generic component - SOF_IPC_TPLG_COMP_NEW */ 52 struct sof_ipc_comp { 53 struct sof_ipc_cmd_hdr hdr; 54 uint32_t id; 55 enum sof_comp_type type; 56 uint32_t pipeline_id; 57 uint32_t core; 58 59 /* reserved for future use */ 60 uint32_t reserved[1]; 61 } __packed; 62 63 /* 64 * Component Buffers 65 */ 66 67 /* 68 * SOF memory capabilities, add new ones at the end 69 */ 70 #define SOF_MEM_CAPS_RAM (1 << 0) 71 #define SOF_MEM_CAPS_ROM (1 << 1) 72 #define SOF_MEM_CAPS_EXT (1 << 2) /**< external */ 73 #define SOF_MEM_CAPS_LP (1 << 3) /**< low power */ 74 #define SOF_MEM_CAPS_HP (1 << 4) /**< high performance */ 75 #define SOF_MEM_CAPS_DMA (1 << 5) /**< DMA'able */ 76 #define SOF_MEM_CAPS_CACHE (1 << 6) /**< cacheable */ 77 #define SOF_MEM_CAPS_EXEC (1 << 7) /**< executable */ 78 79 /* 80 * overrun will cause ring buffer overwrite, instead of XRUN. 81 */ 82 #define SOF_BUF_OVERRUN_PERMITTED BIT(0) 83 84 /* 85 * underrun will cause readback of 0s, instead of XRUN. 86 */ 87 #define SOF_BUF_UNDERRUN_PERMITTED BIT(1) 88 89 /* create new component buffer - SOF_IPC_TPLG_BUFFER_NEW */ 90 struct sof_ipc_buffer { 91 struct sof_ipc_comp comp; 92 uint32_t size; /**< buffer size in bytes */ 93 uint32_t caps; /**< SOF_MEM_CAPS_ */ 94 uint32_t flags; /**< SOF_BUF_ flags defined above */ 95 uint32_t reserved; /**< reserved for future use */ 96 } __packed; 97 98 /* generic component config data - must always be after struct sof_ipc_comp */ 99 struct sof_ipc_comp_config { 100 struct sof_ipc_cmd_hdr hdr; 101 uint32_t periods_sink; /**< 0 means variable */ 102 uint32_t periods_source;/**< 0 means variable */ 103 uint32_t reserved1; /**< reserved */ 104 uint32_t frame_fmt; /**< SOF_IPC_FRAME_ */ 105 uint32_t xrun_action; 106 107 /* reserved for future use */ 108 uint32_t reserved[2]; 109 } __packed; 110 111 /* generic host component */ 112 struct sof_ipc_comp_host { 113 struct sof_ipc_comp comp; 114 struct sof_ipc_comp_config config; 115 uint32_t direction; /**< SOF_IPC_STREAM_ */ 116 uint32_t no_irq; /**< don't send periodic IRQ to host/DSP */ 117 uint32_t dmac_config; /**< DMA engine specific */ 118 } __packed; 119 120 /* generic DAI component */ 121 struct sof_ipc_comp_dai { 122 struct sof_ipc_comp comp; 123 struct sof_ipc_comp_config config; 124 uint32_t direction; /**< SOF_IPC_STREAM_ */ 125 uint32_t dai_index; /**< index of this type dai */ 126 uint32_t type; /**< DAI type - SOF_DAI_ */ 127 uint32_t reserved; /**< reserved */ 128 } __packed; 129 130 /* generic mixer component */ 131 struct sof_ipc_comp_mixer { 132 struct sof_ipc_comp comp; 133 struct sof_ipc_comp_config config; 134 } __packed; 135 136 /* volume ramping types */ 137 enum sof_volume_ramp { 138 SOF_VOLUME_LINEAR = 0, 139 SOF_VOLUME_LOG, 140 SOF_VOLUME_LINEAR_ZC, 141 SOF_VOLUME_LOG_ZC, 142 }; 143 144 /* generic volume component */ 145 struct sof_ipc_comp_volume { 146 struct sof_ipc_comp comp; 147 struct sof_ipc_comp_config config; 148 uint32_t channels; 149 uint32_t min_value; 150 uint32_t max_value; 151 uint32_t ramp; /**< SOF_VOLUME_ */ 152 uint32_t initial_ramp; /**< ramp space in ms */ 153 } __packed; 154 155 /* generic SRC component */ 156 struct sof_ipc_comp_src { 157 struct sof_ipc_comp comp; 158 struct sof_ipc_comp_config config; 159 /* either source or sink rate must be non zero */ 160 uint32_t source_rate; /**< source rate or 0 for variable */ 161 uint32_t sink_rate; /**< sink rate or 0 for variable */ 162 uint32_t rate_mask; /**< SOF_RATE_ supported rates */ 163 } __packed; 164 165 /* generic ASRC component */ 166 struct sof_ipc_comp_asrc { 167 struct sof_ipc_comp comp; 168 struct sof_ipc_comp_config config; 169 /* either source or sink rate must be non zero */ 170 uint32_t source_rate; /**< Define fixed source rate or */ 171 /**< use 0 to indicate need to get */ 172 /**< the rate from stream */ 173 uint32_t sink_rate; /**< Define fixed sink rate or */ 174 /**< use 0 to indicate need to get */ 175 /**< the rate from stream */ 176 uint32_t asynchronous_mode; /**< synchronous 0, asynchronous 1 */ 177 /**< When 1 the ASRC tracks and */ 178 /**< compensates for drift. */ 179 uint32_t operation_mode; /**< push 0, pull 1, In push mode the */ 180 /**< ASRC consumes a defined number */ 181 /**< of frames at input, with varying */ 182 /**< number of frames at output. */ 183 /**< In pull mode the ASRC outputs */ 184 /**< a defined number of frames while */ 185 /**< number of input frames varies. */ 186 187 /* reserved for future use */ 188 uint32_t reserved[4]; 189 } __attribute__((packed)); 190 191 /* generic MUX component */ 192 struct sof_ipc_comp_mux { 193 struct sof_ipc_comp comp; 194 struct sof_ipc_comp_config config; 195 } __packed; 196 197 /* generic tone generator component */ 198 struct sof_ipc_comp_tone { 199 struct sof_ipc_comp comp; 200 struct sof_ipc_comp_config config; 201 int32_t sample_rate; 202 int32_t frequency; 203 int32_t amplitude; 204 int32_t freq_mult; 205 int32_t ampl_mult; 206 int32_t length; 207 int32_t period; 208 int32_t repeats; 209 int32_t ramp_step; 210 } __packed; 211 212 /** \brief Types of processing components */ 213 enum sof_ipc_process_type { 214 SOF_PROCESS_NONE = 0, /**< None */ 215 SOF_PROCESS_EQFIR, /**< Intel FIR */ 216 SOF_PROCESS_EQIIR, /**< Intel IIR */ 217 SOF_PROCESS_KEYWORD_DETECT, /**< Keyword Detection */ 218 SOF_PROCESS_KPB, /**< KeyPhrase Buffer Manager */ 219 SOF_PROCESS_CHAN_SELECTOR, /**< Channel Selector */ 220 SOF_PROCESS_MUX, 221 SOF_PROCESS_DEMUX, 222 SOF_PROCESS_DCBLOCK, 223 }; 224 225 /* generic "effect", "codec" or proprietary processing component */ 226 struct sof_ipc_comp_process { 227 struct sof_ipc_comp comp; 228 struct sof_ipc_comp_config config; 229 uint32_t size; /**< size of bespoke data section in bytes */ 230 uint32_t type; /**< sof_ipc_process_type */ 231 232 /* reserved for future use */ 233 uint32_t reserved[7]; 234 235 uint8_t data[0]; 236 } __packed; 237 238 /* frees components, buffers and pipelines 239 * SOF_IPC_TPLG_COMP_FREE, SOF_IPC_TPLG_PIPE_FREE, SOF_IPC_TPLG_BUFFER_FREE 240 */ 241 struct sof_ipc_free { 242 struct sof_ipc_cmd_hdr hdr; 243 uint32_t id; 244 } __packed; 245 246 struct sof_ipc_comp_reply { 247 struct sof_ipc_reply rhdr; 248 uint32_t id; 249 uint32_t offset; 250 } __packed; 251 252 /* 253 * Pipeline 254 */ 255 256 /** \brief Types of pipeline scheduling time domains */ 257 enum sof_ipc_pipe_sched_time_domain { 258 SOF_TIME_DOMAIN_DMA = 0, /**< DMA interrupt */ 259 SOF_TIME_DOMAIN_TIMER, /**< Timer interrupt */ 260 }; 261 262 /* new pipeline - SOF_IPC_TPLG_PIPE_NEW */ 263 struct sof_ipc_pipe_new { 264 struct sof_ipc_cmd_hdr hdr; 265 uint32_t comp_id; /**< component id for pipeline */ 266 uint32_t pipeline_id; /**< pipeline id */ 267 uint32_t sched_id; /**< Scheduling component id */ 268 uint32_t core; /**< core we run on */ 269 uint32_t period; /**< execution period in us*/ 270 uint32_t priority; /**< priority level 0 (low) to 10 (max) */ 271 uint32_t period_mips; /**< worst case instruction count per period */ 272 uint32_t frames_per_sched;/**< output frames of pipeline, 0 is variable */ 273 uint32_t xrun_limit_usecs; /**< report xruns greater than limit */ 274 uint32_t time_domain; /**< scheduling time domain */ 275 } __packed; 276 277 /* pipeline construction complete - SOF_IPC_TPLG_PIPE_COMPLETE */ 278 struct sof_ipc_pipe_ready { 279 struct sof_ipc_cmd_hdr hdr; 280 uint32_t comp_id; 281 } __packed; 282 283 struct sof_ipc_pipe_free { 284 struct sof_ipc_cmd_hdr hdr; 285 uint32_t comp_id; 286 } __packed; 287 288 /* connect two components in pipeline - SOF_IPC_TPLG_COMP_CONNECT */ 289 struct sof_ipc_pipe_comp_connect { 290 struct sof_ipc_cmd_hdr hdr; 291 uint32_t source_id; 292 uint32_t sink_id; 293 } __packed; 294 295 /* external events */ 296 enum sof_event_types { 297 SOF_EVENT_NONE = 0, 298 SOF_KEYWORD_DETECT_DAPM_EVENT, 299 }; 300 301 #endif 302