1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ 2 /* 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * Copyright(c) 2018 Intel Corporation. All rights reserved. 7 */ 8 9 #ifndef __INCLUDE_SOUND_SOF_TOPOLOGY_H__ 10 #define __INCLUDE_SOUND_SOF_TOPOLOGY_H__ 11 12 #include <sound/sof/header.h> 13 14 /* 15 * Component 16 */ 17 18 /* types of component */ 19 enum sof_comp_type { 20 SOF_COMP_NONE = 0, 21 SOF_COMP_HOST, 22 SOF_COMP_DAI, 23 SOF_COMP_SG_HOST, /**< scatter gather variant */ 24 SOF_COMP_SG_DAI, /**< scatter gather variant */ 25 SOF_COMP_VOLUME, 26 SOF_COMP_MIXER, 27 SOF_COMP_MUX, 28 SOF_COMP_SRC, 29 SOF_COMP_SPLITTER, 30 SOF_COMP_TONE, 31 SOF_COMP_SWITCH, 32 SOF_COMP_BUFFER, 33 SOF_COMP_EQ_IIR, 34 SOF_COMP_EQ_FIR, 35 SOF_COMP_KEYWORD_DETECT, 36 SOF_COMP_KPB, /* A key phrase buffer component */ 37 SOF_COMP_SELECTOR, /**< channel selector component */ 38 SOF_COMP_DEMUX, 39 SOF_COMP_ASRC, /**< Asynchronous sample rate converter */ 40 /* keep FILEREAD/FILEWRITE as the last ones */ 41 SOF_COMP_FILEREAD = 10000, /**< host test based file IO */ 42 SOF_COMP_FILEWRITE = 10001, /**< host test based file IO */ 43 }; 44 45 /* XRUN action for component */ 46 #define SOF_XRUN_STOP 1 /**< stop stream */ 47 #define SOF_XRUN_UNDER_ZERO 2 /**< send 0s to sink */ 48 #define SOF_XRUN_OVER_NULL 4 /**< send data to NULL */ 49 50 /* create new generic component - SOF_IPC_TPLG_COMP_NEW */ 51 struct sof_ipc_comp { 52 struct sof_ipc_cmd_hdr hdr; 53 uint32_t id; 54 enum sof_comp_type type; 55 uint32_t pipeline_id; 56 57 /* reserved for future use */ 58 uint32_t reserved[2]; 59 } __packed; 60 61 /* 62 * Component Buffers 63 */ 64 65 /* 66 * SOF memory capabilities, add new ones at the end 67 */ 68 #define SOF_MEM_CAPS_RAM (1 << 0) 69 #define SOF_MEM_CAPS_ROM (1 << 1) 70 #define SOF_MEM_CAPS_EXT (1 << 2) /**< external */ 71 #define SOF_MEM_CAPS_LP (1 << 3) /**< low power */ 72 #define SOF_MEM_CAPS_HP (1 << 4) /**< high performance */ 73 #define SOF_MEM_CAPS_DMA (1 << 5) /**< DMA'able */ 74 #define SOF_MEM_CAPS_CACHE (1 << 6) /**< cacheable */ 75 #define SOF_MEM_CAPS_EXEC (1 << 7) /**< executable */ 76 77 /* create new component buffer - SOF_IPC_TPLG_BUFFER_NEW */ 78 struct sof_ipc_buffer { 79 struct sof_ipc_comp comp; 80 uint32_t size; /**< buffer size in bytes */ 81 uint32_t caps; /**< SOF_MEM_CAPS_ */ 82 } __packed; 83 84 /* generic component config data - must always be after struct sof_ipc_comp */ 85 struct sof_ipc_comp_config { 86 struct sof_ipc_cmd_hdr hdr; 87 uint32_t periods_sink; /**< 0 means variable */ 88 uint32_t periods_source;/**< 0 means variable */ 89 uint32_t reserved1; /**< reserved */ 90 uint32_t frame_fmt; /**< SOF_IPC_FRAME_ */ 91 uint32_t xrun_action; 92 93 /* reserved for future use */ 94 uint32_t reserved[2]; 95 } __packed; 96 97 /* generic host component */ 98 struct sof_ipc_comp_host { 99 struct sof_ipc_comp comp; 100 struct sof_ipc_comp_config config; 101 uint32_t direction; /**< SOF_IPC_STREAM_ */ 102 uint32_t no_irq; /**< don't send periodic IRQ to host/DSP */ 103 uint32_t dmac_config; /**< DMA engine specific */ 104 } __packed; 105 106 /* generic DAI component */ 107 struct sof_ipc_comp_dai { 108 struct sof_ipc_comp comp; 109 struct sof_ipc_comp_config config; 110 uint32_t direction; /**< SOF_IPC_STREAM_ */ 111 uint32_t dai_index; /**< index of this type dai */ 112 uint32_t type; /**< DAI type - SOF_DAI_ */ 113 uint32_t reserved; /**< reserved */ 114 } __packed; 115 116 /* generic mixer component */ 117 struct sof_ipc_comp_mixer { 118 struct sof_ipc_comp comp; 119 struct sof_ipc_comp_config config; 120 } __packed; 121 122 /* volume ramping types */ 123 enum sof_volume_ramp { 124 SOF_VOLUME_LINEAR = 0, 125 SOF_VOLUME_LOG, 126 SOF_VOLUME_LINEAR_ZC, 127 SOF_VOLUME_LOG_ZC, 128 }; 129 130 /* generic volume component */ 131 struct sof_ipc_comp_volume { 132 struct sof_ipc_comp comp; 133 struct sof_ipc_comp_config config; 134 uint32_t channels; 135 uint32_t min_value; 136 uint32_t max_value; 137 uint32_t ramp; /**< SOF_VOLUME_ */ 138 uint32_t initial_ramp; /**< ramp space in ms */ 139 } __packed; 140 141 /* generic SRC component */ 142 struct sof_ipc_comp_src { 143 struct sof_ipc_comp comp; 144 struct sof_ipc_comp_config config; 145 /* either source or sink rate must be non zero */ 146 uint32_t source_rate; /**< source rate or 0 for variable */ 147 uint32_t sink_rate; /**< sink rate or 0 for variable */ 148 uint32_t rate_mask; /**< SOF_RATE_ supported rates */ 149 } __packed; 150 151 /* generic ASRC component */ 152 struct sof_ipc_comp_asrc { 153 struct sof_ipc_comp comp; 154 struct sof_ipc_comp_config config; 155 /* either source or sink rate must be non zero */ 156 uint32_t source_rate; /**< Define fixed source rate or */ 157 /**< use 0 to indicate need to get */ 158 /**< the rate from stream */ 159 uint32_t sink_rate; /**< Define fixed sink rate or */ 160 /**< use 0 to indicate need to get */ 161 /**< the rate from stream */ 162 uint32_t asynchronous_mode; /**< synchronous 0, asynchronous 1 */ 163 /**< When 1 the ASRC tracks and */ 164 /**< compensates for drift. */ 165 uint32_t operation_mode; /**< push 0, pull 1, In push mode the */ 166 /**< ASRC consumes a defined number */ 167 /**< of frames at input, with varying */ 168 /**< number of frames at output. */ 169 /**< In pull mode the ASRC outputs */ 170 /**< a defined number of frames while */ 171 /**< number of input frames varies. */ 172 173 /* reserved for future use */ 174 uint32_t reserved[4]; 175 } __attribute__((packed)); 176 177 /* generic MUX component */ 178 struct sof_ipc_comp_mux { 179 struct sof_ipc_comp comp; 180 struct sof_ipc_comp_config config; 181 } __packed; 182 183 /* generic tone generator component */ 184 struct sof_ipc_comp_tone { 185 struct sof_ipc_comp comp; 186 struct sof_ipc_comp_config config; 187 int32_t sample_rate; 188 int32_t frequency; 189 int32_t amplitude; 190 int32_t freq_mult; 191 int32_t ampl_mult; 192 int32_t length; 193 int32_t period; 194 int32_t repeats; 195 int32_t ramp_step; 196 } __packed; 197 198 /** \brief Types of processing components */ 199 enum sof_ipc_process_type { 200 SOF_PROCESS_NONE = 0, /**< None */ 201 SOF_PROCESS_EQFIR, /**< Intel FIR */ 202 SOF_PROCESS_EQIIR, /**< Intel IIR */ 203 SOF_PROCESS_KEYWORD_DETECT, /**< Keyword Detection */ 204 SOF_PROCESS_KPB, /**< KeyPhrase Buffer Manager */ 205 SOF_PROCESS_CHAN_SELECTOR, /**< Channel Selector */ 206 SOF_PROCESS_MUX, 207 SOF_PROCESS_DEMUX, 208 }; 209 210 /* generic "effect", "codec" or proprietary processing component */ 211 struct sof_ipc_comp_process { 212 struct sof_ipc_comp comp; 213 struct sof_ipc_comp_config config; 214 uint32_t size; /**< size of bespoke data section in bytes */ 215 uint32_t type; /**< sof_ipc_process_type */ 216 217 /* reserved for future use */ 218 uint32_t reserved[7]; 219 220 unsigned char data[0]; 221 } __packed; 222 223 /* frees components, buffers and pipelines 224 * SOF_IPC_TPLG_COMP_FREE, SOF_IPC_TPLG_PIPE_FREE, SOF_IPC_TPLG_BUFFER_FREE 225 */ 226 struct sof_ipc_free { 227 struct sof_ipc_cmd_hdr hdr; 228 uint32_t id; 229 } __packed; 230 231 struct sof_ipc_comp_reply { 232 struct sof_ipc_reply rhdr; 233 uint32_t id; 234 uint32_t offset; 235 } __packed; 236 237 /* 238 * Pipeline 239 */ 240 241 /** \brief Types of pipeline scheduling time domains */ 242 enum sof_ipc_pipe_sched_time_domain { 243 SOF_TIME_DOMAIN_DMA = 0, /**< DMA interrupt */ 244 SOF_TIME_DOMAIN_TIMER, /**< Timer interrupt */ 245 }; 246 247 /* new pipeline - SOF_IPC_TPLG_PIPE_NEW */ 248 struct sof_ipc_pipe_new { 249 struct sof_ipc_cmd_hdr hdr; 250 uint32_t comp_id; /**< component id for pipeline */ 251 uint32_t pipeline_id; /**< pipeline id */ 252 uint32_t sched_id; /**< Scheduling component id */ 253 uint32_t core; /**< core we run on */ 254 uint32_t period; /**< execution period in us*/ 255 uint32_t priority; /**< priority level 0 (low) to 10 (max) */ 256 uint32_t period_mips; /**< worst case instruction count per period */ 257 uint32_t frames_per_sched;/**< output frames of pipeline, 0 is variable */ 258 uint32_t xrun_limit_usecs; /**< report xruns greater than limit */ 259 uint32_t time_domain; /**< scheduling time domain */ 260 } __packed; 261 262 /* pipeline construction complete - SOF_IPC_TPLG_PIPE_COMPLETE */ 263 struct sof_ipc_pipe_ready { 264 struct sof_ipc_cmd_hdr hdr; 265 uint32_t comp_id; 266 } __packed; 267 268 struct sof_ipc_pipe_free { 269 struct sof_ipc_cmd_hdr hdr; 270 uint32_t comp_id; 271 } __packed; 272 273 /* connect two components in pipeline - SOF_IPC_TPLG_COMP_CONNECT */ 274 struct sof_ipc_pipe_comp_connect { 275 struct sof_ipc_cmd_hdr hdr; 276 uint32_t source_id; 277 uint32_t sink_id; 278 } __packed; 279 280 /* external events */ 281 enum sof_event_types { 282 SOF_EVENT_NONE = 0, 283 SOF_KEYWORD_DETECT_DAPM_EVENT, 284 }; 285 286 #endif 287