1e149ca29SPierre-Louis Bossart /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2311ce4feSLiam Girdwood /* 3311ce4feSLiam Girdwood * This file is provided under a dual BSD/GPLv2 license. When using or 4311ce4feSLiam Girdwood * redistributing this file, you may do so under either license. 5311ce4feSLiam Girdwood * 6311ce4feSLiam Girdwood * Copyright(c) 2018 Intel Corporation. All rights reserved. 7311ce4feSLiam Girdwood */ 8311ce4feSLiam Girdwood 9311ce4feSLiam Girdwood #ifndef __INCLUDE_SOUND_SOF_TOPOLOGY_H__ 10311ce4feSLiam Girdwood #define __INCLUDE_SOUND_SOF_TOPOLOGY_H__ 11311ce4feSLiam Girdwood 12311ce4feSLiam Girdwood #include <sound/sof/header.h> 13311ce4feSLiam Girdwood 14311ce4feSLiam Girdwood /* 15311ce4feSLiam Girdwood * Component 16311ce4feSLiam Girdwood */ 17311ce4feSLiam Girdwood 18311ce4feSLiam Girdwood /* types of component */ 19311ce4feSLiam Girdwood enum sof_comp_type { 20311ce4feSLiam Girdwood SOF_COMP_NONE = 0, 21311ce4feSLiam Girdwood SOF_COMP_HOST, 22311ce4feSLiam Girdwood SOF_COMP_DAI, 23311ce4feSLiam Girdwood SOF_COMP_SG_HOST, /**< scatter gather variant */ 24311ce4feSLiam Girdwood SOF_COMP_SG_DAI, /**< scatter gather variant */ 25311ce4feSLiam Girdwood SOF_COMP_VOLUME, 26311ce4feSLiam Girdwood SOF_COMP_MIXER, 27311ce4feSLiam Girdwood SOF_COMP_MUX, 28311ce4feSLiam Girdwood SOF_COMP_SRC, 29*8dc97ccfSCurtis Malainey SOF_COMP_DEPRECATED0, /* Formerly SOF_COMP_SPLITTER */ 30311ce4feSLiam Girdwood SOF_COMP_TONE, 31*8dc97ccfSCurtis Malainey SOF_COMP_DEPRECATED1, /* Formerly SOF_COMP_SWITCH */ 32311ce4feSLiam Girdwood SOF_COMP_BUFFER, 33311ce4feSLiam Girdwood SOF_COMP_EQ_IIR, 34311ce4feSLiam Girdwood SOF_COMP_EQ_FIR, 35311ce4feSLiam Girdwood SOF_COMP_KEYWORD_DETECT, 36311ce4feSLiam Girdwood SOF_COMP_KPB, /* A key phrase buffer component */ 37311ce4feSLiam Girdwood SOF_COMP_SELECTOR, /**< channel selector component */ 3866358069SJaska Uimonen SOF_COMP_DEMUX, 39433363e7SSeppo Ingalsuo SOF_COMP_ASRC, /**< Asynchronous sample rate converter */ 40542adb2aSSebastiano Carlucci SOF_COMP_DCBLOCK, 4182e8c00fSKeyon Jie SOF_COMP_SMART_AMP, /**< smart amplifier component */ 42311ce4feSLiam Girdwood /* keep FILEREAD/FILEWRITE as the last ones */ 43311ce4feSLiam Girdwood SOF_COMP_FILEREAD = 10000, /**< host test based file IO */ 44311ce4feSLiam Girdwood SOF_COMP_FILEWRITE = 10001, /**< host test based file IO */ 45311ce4feSLiam Girdwood }; 46311ce4feSLiam Girdwood 47311ce4feSLiam Girdwood /* XRUN action for component */ 48311ce4feSLiam Girdwood #define SOF_XRUN_STOP 1 /**< stop stream */ 49311ce4feSLiam Girdwood #define SOF_XRUN_UNDER_ZERO 2 /**< send 0s to sink */ 50311ce4feSLiam Girdwood #define SOF_XRUN_OVER_NULL 4 /**< send data to NULL */ 51311ce4feSLiam Girdwood 52311ce4feSLiam Girdwood /* create new generic component - SOF_IPC_TPLG_COMP_NEW */ 53311ce4feSLiam Girdwood struct sof_ipc_comp { 54311ce4feSLiam Girdwood struct sof_ipc_cmd_hdr hdr; 55311ce4feSLiam Girdwood uint32_t id; 56311ce4feSLiam Girdwood enum sof_comp_type type; 57311ce4feSLiam Girdwood uint32_t pipeline_id; 581a2289fdSTomasz Lauda uint32_t core; 59311ce4feSLiam Girdwood 6050b55fd4SKeyon Jie /* extended data length, 0 if no extended data */ 6150b55fd4SKeyon Jie uint32_t ext_data_length; 62311ce4feSLiam Girdwood } __packed; 63311ce4feSLiam Girdwood 64311ce4feSLiam Girdwood /* 65311ce4feSLiam Girdwood * Component Buffers 66311ce4feSLiam Girdwood */ 67311ce4feSLiam Girdwood 68311ce4feSLiam Girdwood /* 69311ce4feSLiam Girdwood * SOF memory capabilities, add new ones at the end 70311ce4feSLiam Girdwood */ 71311ce4feSLiam Girdwood #define SOF_MEM_CAPS_RAM (1 << 0) 72311ce4feSLiam Girdwood #define SOF_MEM_CAPS_ROM (1 << 1) 73311ce4feSLiam Girdwood #define SOF_MEM_CAPS_EXT (1 << 2) /**< external */ 74311ce4feSLiam Girdwood #define SOF_MEM_CAPS_LP (1 << 3) /**< low power */ 75311ce4feSLiam Girdwood #define SOF_MEM_CAPS_HP (1 << 4) /**< high performance */ 76311ce4feSLiam Girdwood #define SOF_MEM_CAPS_DMA (1 << 5) /**< DMA'able */ 77311ce4feSLiam Girdwood #define SOF_MEM_CAPS_CACHE (1 << 6) /**< cacheable */ 78311ce4feSLiam Girdwood #define SOF_MEM_CAPS_EXEC (1 << 7) /**< executable */ 79311ce4feSLiam Girdwood 807893df67SArtur Kloniecki /* 817893df67SArtur Kloniecki * overrun will cause ring buffer overwrite, instead of XRUN. 827893df67SArtur Kloniecki */ 837893df67SArtur Kloniecki #define SOF_BUF_OVERRUN_PERMITTED BIT(0) 847893df67SArtur Kloniecki 857893df67SArtur Kloniecki /* 867893df67SArtur Kloniecki * underrun will cause readback of 0s, instead of XRUN. 877893df67SArtur Kloniecki */ 887893df67SArtur Kloniecki #define SOF_BUF_UNDERRUN_PERMITTED BIT(1) 897893df67SArtur Kloniecki 90311ce4feSLiam Girdwood /* create new component buffer - SOF_IPC_TPLG_BUFFER_NEW */ 91311ce4feSLiam Girdwood struct sof_ipc_buffer { 92311ce4feSLiam Girdwood struct sof_ipc_comp comp; 93311ce4feSLiam Girdwood uint32_t size; /**< buffer size in bytes */ 94311ce4feSLiam Girdwood uint32_t caps; /**< SOF_MEM_CAPS_ */ 957893df67SArtur Kloniecki uint32_t flags; /**< SOF_BUF_ flags defined above */ 967893df67SArtur Kloniecki uint32_t reserved; /**< reserved for future use */ 97311ce4feSLiam Girdwood } __packed; 98311ce4feSLiam Girdwood 99311ce4feSLiam Girdwood /* generic component config data - must always be after struct sof_ipc_comp */ 100311ce4feSLiam Girdwood struct sof_ipc_comp_config { 101311ce4feSLiam Girdwood struct sof_ipc_cmd_hdr hdr; 102311ce4feSLiam Girdwood uint32_t periods_sink; /**< 0 means variable */ 103311ce4feSLiam Girdwood uint32_t periods_source;/**< 0 means variable */ 104311ce4feSLiam Girdwood uint32_t reserved1; /**< reserved */ 105311ce4feSLiam Girdwood uint32_t frame_fmt; /**< SOF_IPC_FRAME_ */ 106311ce4feSLiam Girdwood uint32_t xrun_action; 107311ce4feSLiam Girdwood 108311ce4feSLiam Girdwood /* reserved for future use */ 109311ce4feSLiam Girdwood uint32_t reserved[2]; 110311ce4feSLiam Girdwood } __packed; 111311ce4feSLiam Girdwood 112311ce4feSLiam Girdwood /* generic host component */ 113311ce4feSLiam Girdwood struct sof_ipc_comp_host { 114311ce4feSLiam Girdwood struct sof_ipc_comp comp; 115311ce4feSLiam Girdwood struct sof_ipc_comp_config config; 116311ce4feSLiam Girdwood uint32_t direction; /**< SOF_IPC_STREAM_ */ 117311ce4feSLiam Girdwood uint32_t no_irq; /**< don't send periodic IRQ to host/DSP */ 118311ce4feSLiam Girdwood uint32_t dmac_config; /**< DMA engine specific */ 119311ce4feSLiam Girdwood } __packed; 120311ce4feSLiam Girdwood 121311ce4feSLiam Girdwood /* generic DAI component */ 122311ce4feSLiam Girdwood struct sof_ipc_comp_dai { 123311ce4feSLiam Girdwood struct sof_ipc_comp comp; 124311ce4feSLiam Girdwood struct sof_ipc_comp_config config; 125311ce4feSLiam Girdwood uint32_t direction; /**< SOF_IPC_STREAM_ */ 126311ce4feSLiam Girdwood uint32_t dai_index; /**< index of this type dai */ 127311ce4feSLiam Girdwood uint32_t type; /**< DAI type - SOF_DAI_ */ 128311ce4feSLiam Girdwood uint32_t reserved; /**< reserved */ 129311ce4feSLiam Girdwood } __packed; 130311ce4feSLiam Girdwood 131311ce4feSLiam Girdwood /* generic mixer component */ 132311ce4feSLiam Girdwood struct sof_ipc_comp_mixer { 133311ce4feSLiam Girdwood struct sof_ipc_comp comp; 134311ce4feSLiam Girdwood struct sof_ipc_comp_config config; 135311ce4feSLiam Girdwood } __packed; 136311ce4feSLiam Girdwood 137311ce4feSLiam Girdwood /* volume ramping types */ 138311ce4feSLiam Girdwood enum sof_volume_ramp { 139311ce4feSLiam Girdwood SOF_VOLUME_LINEAR = 0, 140311ce4feSLiam Girdwood SOF_VOLUME_LOG, 141311ce4feSLiam Girdwood SOF_VOLUME_LINEAR_ZC, 142311ce4feSLiam Girdwood SOF_VOLUME_LOG_ZC, 143311ce4feSLiam Girdwood }; 144311ce4feSLiam Girdwood 145311ce4feSLiam Girdwood /* generic volume component */ 146311ce4feSLiam Girdwood struct sof_ipc_comp_volume { 147311ce4feSLiam Girdwood struct sof_ipc_comp comp; 148311ce4feSLiam Girdwood struct sof_ipc_comp_config config; 149311ce4feSLiam Girdwood uint32_t channels; 150311ce4feSLiam Girdwood uint32_t min_value; 151311ce4feSLiam Girdwood uint32_t max_value; 152311ce4feSLiam Girdwood uint32_t ramp; /**< SOF_VOLUME_ */ 153311ce4feSLiam Girdwood uint32_t initial_ramp; /**< ramp space in ms */ 154311ce4feSLiam Girdwood } __packed; 155311ce4feSLiam Girdwood 156311ce4feSLiam Girdwood /* generic SRC component */ 157311ce4feSLiam Girdwood struct sof_ipc_comp_src { 158311ce4feSLiam Girdwood struct sof_ipc_comp comp; 159311ce4feSLiam Girdwood struct sof_ipc_comp_config config; 160311ce4feSLiam Girdwood /* either source or sink rate must be non zero */ 161311ce4feSLiam Girdwood uint32_t source_rate; /**< source rate or 0 for variable */ 162311ce4feSLiam Girdwood uint32_t sink_rate; /**< sink rate or 0 for variable */ 163311ce4feSLiam Girdwood uint32_t rate_mask; /**< SOF_RATE_ supported rates */ 164311ce4feSLiam Girdwood } __packed; 165311ce4feSLiam Girdwood 166433363e7SSeppo Ingalsuo /* generic ASRC component */ 167433363e7SSeppo Ingalsuo struct sof_ipc_comp_asrc { 168433363e7SSeppo Ingalsuo struct sof_ipc_comp comp; 169433363e7SSeppo Ingalsuo struct sof_ipc_comp_config config; 170433363e7SSeppo Ingalsuo /* either source or sink rate must be non zero */ 171433363e7SSeppo Ingalsuo uint32_t source_rate; /**< Define fixed source rate or */ 172433363e7SSeppo Ingalsuo /**< use 0 to indicate need to get */ 173433363e7SSeppo Ingalsuo /**< the rate from stream */ 174433363e7SSeppo Ingalsuo uint32_t sink_rate; /**< Define fixed sink rate or */ 175433363e7SSeppo Ingalsuo /**< use 0 to indicate need to get */ 176433363e7SSeppo Ingalsuo /**< the rate from stream */ 177433363e7SSeppo Ingalsuo uint32_t asynchronous_mode; /**< synchronous 0, asynchronous 1 */ 178433363e7SSeppo Ingalsuo /**< When 1 the ASRC tracks and */ 179433363e7SSeppo Ingalsuo /**< compensates for drift. */ 180433363e7SSeppo Ingalsuo uint32_t operation_mode; /**< push 0, pull 1, In push mode the */ 181433363e7SSeppo Ingalsuo /**< ASRC consumes a defined number */ 182433363e7SSeppo Ingalsuo /**< of frames at input, with varying */ 183433363e7SSeppo Ingalsuo /**< number of frames at output. */ 184433363e7SSeppo Ingalsuo /**< In pull mode the ASRC outputs */ 185433363e7SSeppo Ingalsuo /**< a defined number of frames while */ 186433363e7SSeppo Ingalsuo /**< number of input frames varies. */ 187433363e7SSeppo Ingalsuo 188433363e7SSeppo Ingalsuo /* reserved for future use */ 189433363e7SSeppo Ingalsuo uint32_t reserved[4]; 190433363e7SSeppo Ingalsuo } __attribute__((packed)); 191433363e7SSeppo Ingalsuo 192311ce4feSLiam Girdwood /* generic MUX component */ 193311ce4feSLiam Girdwood struct sof_ipc_comp_mux { 194311ce4feSLiam Girdwood struct sof_ipc_comp comp; 195311ce4feSLiam Girdwood struct sof_ipc_comp_config config; 196311ce4feSLiam Girdwood } __packed; 197311ce4feSLiam Girdwood 198311ce4feSLiam Girdwood /* generic tone generator component */ 199311ce4feSLiam Girdwood struct sof_ipc_comp_tone { 200311ce4feSLiam Girdwood struct sof_ipc_comp comp; 201311ce4feSLiam Girdwood struct sof_ipc_comp_config config; 202311ce4feSLiam Girdwood int32_t sample_rate; 203311ce4feSLiam Girdwood int32_t frequency; 204311ce4feSLiam Girdwood int32_t amplitude; 205311ce4feSLiam Girdwood int32_t freq_mult; 206311ce4feSLiam Girdwood int32_t ampl_mult; 207311ce4feSLiam Girdwood int32_t length; 208311ce4feSLiam Girdwood int32_t period; 209311ce4feSLiam Girdwood int32_t repeats; 210311ce4feSLiam Girdwood int32_t ramp_step; 211311ce4feSLiam Girdwood } __packed; 212311ce4feSLiam Girdwood 213311ce4feSLiam Girdwood /** \brief Types of processing components */ 214311ce4feSLiam Girdwood enum sof_ipc_process_type { 215311ce4feSLiam Girdwood SOF_PROCESS_NONE = 0, /**< None */ 216311ce4feSLiam Girdwood SOF_PROCESS_EQFIR, /**< Intel FIR */ 217311ce4feSLiam Girdwood SOF_PROCESS_EQIIR, /**< Intel IIR */ 218311ce4feSLiam Girdwood SOF_PROCESS_KEYWORD_DETECT, /**< Keyword Detection */ 219311ce4feSLiam Girdwood SOF_PROCESS_KPB, /**< KeyPhrase Buffer Manager */ 220311ce4feSLiam Girdwood SOF_PROCESS_CHAN_SELECTOR, /**< Channel Selector */ 22166358069SJaska Uimonen SOF_PROCESS_MUX, 22266358069SJaska Uimonen SOF_PROCESS_DEMUX, 223542adb2aSSebastiano Carlucci SOF_PROCESS_DCBLOCK, 22482e8c00fSKeyon Jie SOF_PROCESS_SMART_AMP, /**< Smart Amplifier */ 225311ce4feSLiam Girdwood }; 226311ce4feSLiam Girdwood 227311ce4feSLiam Girdwood /* generic "effect", "codec" or proprietary processing component */ 228311ce4feSLiam Girdwood struct sof_ipc_comp_process { 229311ce4feSLiam Girdwood struct sof_ipc_comp comp; 230311ce4feSLiam Girdwood struct sof_ipc_comp_config config; 231311ce4feSLiam Girdwood uint32_t size; /**< size of bespoke data section in bytes */ 232311ce4feSLiam Girdwood uint32_t type; /**< sof_ipc_process_type */ 233311ce4feSLiam Girdwood 234311ce4feSLiam Girdwood /* reserved for future use */ 235311ce4feSLiam Girdwood uint32_t reserved[7]; 236311ce4feSLiam Girdwood 2374fe6a630SStephen Kitt uint8_t data[]; 238311ce4feSLiam Girdwood } __packed; 239311ce4feSLiam Girdwood 240311ce4feSLiam Girdwood /* frees components, buffers and pipelines 241311ce4feSLiam Girdwood * SOF_IPC_TPLG_COMP_FREE, SOF_IPC_TPLG_PIPE_FREE, SOF_IPC_TPLG_BUFFER_FREE 242311ce4feSLiam Girdwood */ 243311ce4feSLiam Girdwood struct sof_ipc_free { 244311ce4feSLiam Girdwood struct sof_ipc_cmd_hdr hdr; 245311ce4feSLiam Girdwood uint32_t id; 246311ce4feSLiam Girdwood } __packed; 247311ce4feSLiam Girdwood 248311ce4feSLiam Girdwood struct sof_ipc_comp_reply { 249311ce4feSLiam Girdwood struct sof_ipc_reply rhdr; 250311ce4feSLiam Girdwood uint32_t id; 251311ce4feSLiam Girdwood uint32_t offset; 252311ce4feSLiam Girdwood } __packed; 253311ce4feSLiam Girdwood 254311ce4feSLiam Girdwood /* 255311ce4feSLiam Girdwood * Pipeline 256311ce4feSLiam Girdwood */ 257311ce4feSLiam Girdwood 258311ce4feSLiam Girdwood /** \brief Types of pipeline scheduling time domains */ 259311ce4feSLiam Girdwood enum sof_ipc_pipe_sched_time_domain { 260311ce4feSLiam Girdwood SOF_TIME_DOMAIN_DMA = 0, /**< DMA interrupt */ 261311ce4feSLiam Girdwood SOF_TIME_DOMAIN_TIMER, /**< Timer interrupt */ 262311ce4feSLiam Girdwood }; 263311ce4feSLiam Girdwood 264311ce4feSLiam Girdwood /* new pipeline - SOF_IPC_TPLG_PIPE_NEW */ 265311ce4feSLiam Girdwood struct sof_ipc_pipe_new { 266311ce4feSLiam Girdwood struct sof_ipc_cmd_hdr hdr; 267311ce4feSLiam Girdwood uint32_t comp_id; /**< component id for pipeline */ 268311ce4feSLiam Girdwood uint32_t pipeline_id; /**< pipeline id */ 269311ce4feSLiam Girdwood uint32_t sched_id; /**< Scheduling component id */ 270311ce4feSLiam Girdwood uint32_t core; /**< core we run on */ 271311ce4feSLiam Girdwood uint32_t period; /**< execution period in us*/ 272311ce4feSLiam Girdwood uint32_t priority; /**< priority level 0 (low) to 10 (max) */ 273311ce4feSLiam Girdwood uint32_t period_mips; /**< worst case instruction count per period */ 274311ce4feSLiam Girdwood uint32_t frames_per_sched;/**< output frames of pipeline, 0 is variable */ 275311ce4feSLiam Girdwood uint32_t xrun_limit_usecs; /**< report xruns greater than limit */ 276311ce4feSLiam Girdwood uint32_t time_domain; /**< scheduling time domain */ 277311ce4feSLiam Girdwood } __packed; 278311ce4feSLiam Girdwood 279311ce4feSLiam Girdwood /* pipeline construction complete - SOF_IPC_TPLG_PIPE_COMPLETE */ 280311ce4feSLiam Girdwood struct sof_ipc_pipe_ready { 281311ce4feSLiam Girdwood struct sof_ipc_cmd_hdr hdr; 282311ce4feSLiam Girdwood uint32_t comp_id; 283311ce4feSLiam Girdwood } __packed; 284311ce4feSLiam Girdwood 285311ce4feSLiam Girdwood struct sof_ipc_pipe_free { 286311ce4feSLiam Girdwood struct sof_ipc_cmd_hdr hdr; 287311ce4feSLiam Girdwood uint32_t comp_id; 288311ce4feSLiam Girdwood } __packed; 289311ce4feSLiam Girdwood 290311ce4feSLiam Girdwood /* connect two components in pipeline - SOF_IPC_TPLG_COMP_CONNECT */ 291311ce4feSLiam Girdwood struct sof_ipc_pipe_comp_connect { 292311ce4feSLiam Girdwood struct sof_ipc_cmd_hdr hdr; 293311ce4feSLiam Girdwood uint32_t source_id; 294311ce4feSLiam Girdwood uint32_t sink_id; 295311ce4feSLiam Girdwood } __packed; 296311ce4feSLiam Girdwood 297311ce4feSLiam Girdwood /* external events */ 298311ce4feSLiam Girdwood enum sof_event_types { 299311ce4feSLiam Girdwood SOF_EVENT_NONE = 0, 300311ce4feSLiam Girdwood SOF_KEYWORD_DETECT_DAPM_EVENT, 301311ce4feSLiam Girdwood }; 302311ce4feSLiam Girdwood 303311ce4feSLiam Girdwood #endif 304