1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2 /* 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * Copyright(c) 2018 Intel Corporation. All rights reserved. 7 */ 8 9 #ifndef __INCLUDE_SOUND_SOF_DAI_INTEL_H__ 10 #define __INCLUDE_SOUND_SOF_DAI_INTEL_H__ 11 12 #include <sound/sof/header.h> 13 14 /* ssc1: TINTE */ 15 #define SOF_DAI_INTEL_SSP_QUIRK_TINTE (1 << 0) 16 /* ssc1: PINTE */ 17 #define SOF_DAI_INTEL_SSP_QUIRK_PINTE (1 << 1) 18 /* ssc2: SMTATF */ 19 #define SOF_DAI_INTEL_SSP_QUIRK_SMTATF (1 << 2) 20 /* ssc2: MMRATF */ 21 #define SOF_DAI_INTEL_SSP_QUIRK_MMRATF (1 << 3) 22 /* ssc2: PSPSTWFDFD */ 23 #define SOF_DAI_INTEL_SSP_QUIRK_PSPSTWFDFD (1 << 4) 24 /* ssc2: PSPSRWFDFD */ 25 #define SOF_DAI_INTEL_SSP_QUIRK_PSPSRWFDFD (1 << 5) 26 /* ssc1: LBM */ 27 #define SOF_DAI_INTEL_SSP_QUIRK_LBM (1 << 6) 28 29 /* here is the possibility to define others aux macros */ 30 31 #define SOF_DAI_INTEL_SSP_FRAME_PULSE_WIDTH_MAX 38 32 #define SOF_DAI_INTEL_SSP_SLOT_PADDING_MAX 31 33 34 /* SSP clocks control settings 35 * 36 * Macros for clks_control field in sof_ipc_dai_ssp_params struct. 37 */ 38 39 /* mclk 0 disable */ 40 #define SOF_DAI_INTEL_SSP_MCLK_0_DISABLE BIT(0) 41 /* mclk 1 disable */ 42 #define SOF_DAI_INTEL_SSP_MCLK_1_DISABLE BIT(1) 43 /* mclk keep active */ 44 #define SOF_DAI_INTEL_SSP_CLKCTRL_MCLK_KA BIT(2) 45 /* bclk keep active */ 46 #define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_KA BIT(3) 47 /* fs keep active */ 48 #define SOF_DAI_INTEL_SSP_CLKCTRL_FS_KA BIT(4) 49 /* bclk idle */ 50 #define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_IDLE_HIGH BIT(5) 51 /* mclk early start */ 52 #define SOF_DAI_INTEL_SSP_CLKCTRL_MCLK_ES BIT(6) 53 /* bclk early start */ 54 #define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_ES BIT(7) 55 56 /* DMIC max. four controllers for eight microphone channels */ 57 #define SOF_DAI_INTEL_DMIC_NUM_CTRL 4 58 59 /* SSP Configuration Request - SOF_IPC_DAI_SSP_CONFIG */ 60 struct sof_ipc_dai_ssp_params { 61 struct sof_ipc_hdr hdr; 62 uint16_t reserved1; 63 uint16_t mclk_id; 64 65 uint32_t mclk_rate; /* mclk frequency in Hz */ 66 uint32_t fsync_rate; /* fsync frequency in Hz */ 67 uint32_t bclk_rate; /* bclk frequency in Hz */ 68 69 /* TDM */ 70 uint32_t tdm_slots; 71 uint32_t rx_slots; 72 uint32_t tx_slots; 73 74 /* data */ 75 uint32_t sample_valid_bits; 76 uint16_t tdm_slot_width; 77 uint16_t reserved2; /* alignment */ 78 79 /* MCLK */ 80 uint32_t mclk_direction; 81 82 uint16_t frame_pulse_width; 83 uint16_t tdm_per_slot_padding_flag; 84 uint32_t clks_control; 85 uint32_t quirks; 86 uint32_t bclk_delay; /* guaranteed time (ms) for which BCLK 87 * will be driven, before sending data 88 */ 89 } __packed; 90 91 /* HDA Configuration Request - SOF_IPC_DAI_HDA_CONFIG */ 92 struct sof_ipc_dai_hda_params { 93 struct sof_ipc_hdr hdr; 94 uint32_t link_dma_ch; 95 uint32_t rate; 96 uint32_t channels; 97 } __packed; 98 99 /* ALH Configuration Request - SOF_IPC_DAI_ALH_CONFIG */ 100 struct sof_ipc_dai_alh_params { 101 struct sof_ipc_hdr hdr; 102 uint32_t stream_id; 103 uint32_t rate; 104 uint32_t channels; 105 106 /* reserved for future use */ 107 uint32_t reserved[13]; 108 } __packed; 109 110 /* DMIC Configuration Request - SOF_IPC_DAI_DMIC_CONFIG */ 111 112 /* This struct is defined per 2ch PDM controller available in the platform. 113 * Normally it is sufficient to set the used microphone specific enables to 1 114 * and keep other parameters as zero. The customizations are: 115 * 116 * 1. If a device mixes different microphones types with different polarity 117 * and/or the absolute polarity matters the PCM signal from a microphone 118 * can be inverted with the controls. 119 * 120 * 2. If the microphones in a stereo pair do not appear in captured stream 121 * in desired order due to board schematics choises they can be swapped with 122 * the clk_edge parameter. 123 * 124 * 3. If PDM bit errors are seen in capture (poor quality) the skew parameter 125 * that delays the sampling time of data by half cycles of DMIC source clock 126 * can be tried for improvement. However there is no guarantee for this to fix 127 * data integrity problems. 128 */ 129 struct sof_ipc_dai_dmic_pdm_ctrl { 130 struct sof_ipc_hdr hdr; 131 uint16_t id; /**< PDM controller ID */ 132 133 uint16_t enable_mic_a; /**< Use A (left) channel mic (0 or 1)*/ 134 uint16_t enable_mic_b; /**< Use B (right) channel mic (0 or 1)*/ 135 136 uint16_t polarity_mic_a; /**< Optionally invert mic A signal (0 or 1) */ 137 uint16_t polarity_mic_b; /**< Optionally invert mic B signal (0 or 1) */ 138 139 uint16_t clk_edge; /**< Optionally swap data clock edge (0 or 1) */ 140 uint16_t skew; /**< Adjust PDM data sampling vs. clock (0..15) */ 141 142 uint16_t reserved[3]; /**< Make sure the total size is 4 bytes aligned */ 143 } __packed; 144 145 /* This struct contains the global settings for all 2ch PDM controllers. The 146 * version number used in configuration data is checked vs. version used by 147 * device driver src/drivers/dmic.c need to match. It is incremented from 148 * initial value 1 if updates done for the to driver would alter the operation 149 * of the microphone. 150 * 151 * Note: The microphone clock (pdmclk_min, pdmclk_max, duty_min, duty_max) 152 * parameters need to be set as defined in microphone data sheet. E.g. clock 153 * range 1.0 - 3.2 MHz is usually supported microphones. Some microphones are 154 * multi-mode capable and there may be denied mic clock frequencies between 155 * the modes. In such case set the clock range limits of the desired mode to 156 * avoid the driver to set clock to an illegal rate. 157 * 158 * The duty cycle could be set to 48-52% if not known. Generally these 159 * parameters can be altered within data sheet specified limits to match 160 * required audio application performance power. 161 * 162 * The microphone clock needs to be usually about 50-80 times the used audio 163 * sample rate. With highest sample rates above 48 kHz this can relaxed 164 * somewhat. 165 * 166 * The parameter wake_up_time describes how long time the microphone needs 167 * for the data line to produce valid output from mic clock start. The driver 168 * will mute the captured audio for the given time. The min_clock_on_time 169 * parameter is used to prevent too short clock bursts to happen. The driver 170 * will keep the clock active after capture stop if this time is not yet 171 * met. The unit for both is microseconds (us). Exceed of 100 ms will be 172 * treated as an error. 173 */ 174 struct sof_ipc_dai_dmic_params { 175 struct sof_ipc_hdr hdr; 176 uint32_t driver_ipc_version; /**< Version (1..N) */ 177 178 uint32_t pdmclk_min; /**< Minimum microphone clock in Hz (100000..N) */ 179 uint32_t pdmclk_max; /**< Maximum microphone clock in Hz (min...N) */ 180 181 uint32_t fifo_fs; /**< FIFO sample rate in Hz (8000..96000) */ 182 uint32_t reserved_1; /**< Reserved */ 183 uint16_t fifo_bits; /**< FIFO word length (16 or 32) */ 184 uint16_t fifo_bits_b; /**< Deprecated since firmware ABI 3.0.1 */ 185 186 uint16_t duty_min; /**< Min. mic clock duty cycle in % (20..80) */ 187 uint16_t duty_max; /**< Max. mic clock duty cycle in % (min..80) */ 188 189 uint32_t num_pdm_active; /**< Number of active pdm controllers. */ 190 /**< Range is 1..SOF_DAI_INTEL_DMIC_NUM_CTRL */ 191 192 uint32_t wake_up_time; /**< Time from clock start to data (us) */ 193 uint32_t min_clock_on_time; /**< Min. time that clk is kept on (us) */ 194 uint32_t unmute_ramp_time; /**< Length of logarithmic gain ramp (ms) */ 195 196 /* reserved for future use */ 197 uint32_t reserved[5]; 198 199 /**< PDM controllers configuration */ 200 struct sof_ipc_dai_dmic_pdm_ctrl pdm[SOF_DAI_INTEL_DMIC_NUM_CTRL]; 201 } __packed; 202 203 #endif 204