1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ 2 /* 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * Copyright(c) 2018 Intel Corporation. All rights reserved. 7 */ 8 9 #ifndef __INCLUDE_SOUND_SOF_DAI_INTEL_H__ 10 #define __INCLUDE_SOUND_SOF_DAI_INTEL_H__ 11 12 #include <sound/sof/header.h> 13 14 /* ssc1: TINTE */ 15 #define SOF_DAI_INTEL_SSP_QUIRK_TINTE (1 << 0) 16 /* ssc1: PINTE */ 17 #define SOF_DAI_INTEL_SSP_QUIRK_PINTE (1 << 1) 18 /* ssc2: SMTATF */ 19 #define SOF_DAI_INTEL_SSP_QUIRK_SMTATF (1 << 2) 20 /* ssc2: MMRATF */ 21 #define SOF_DAI_INTEL_SSP_QUIRK_MMRATF (1 << 3) 22 /* ssc2: PSPSTWFDFD */ 23 #define SOF_DAI_INTEL_SSP_QUIRK_PSPSTWFDFD (1 << 4) 24 /* ssc2: PSPSRWFDFD */ 25 #define SOF_DAI_INTEL_SSP_QUIRK_PSPSRWFDFD (1 << 5) 26 /* ssc1: LBM */ 27 #define SOF_DAI_INTEL_SSP_QUIRK_LBM (1 << 6) 28 29 /* here is the possibility to define others aux macros */ 30 31 #define SOF_DAI_INTEL_SSP_FRAME_PULSE_WIDTH_MAX 38 32 #define SOF_DAI_INTEL_SSP_SLOT_PADDING_MAX 31 33 34 /* SSP clocks control settings 35 * 36 * Macros for clks_control field in sof_ipc_dai_ssp_params struct. 37 */ 38 39 /* mclk 0 disable */ 40 #define SOF_DAI_INTEL_SSP_MCLK_0_DISABLE BIT(0) 41 /* mclk 1 disable */ 42 #define SOF_DAI_INTEL_SSP_MCLK_1_DISABLE BIT(1) 43 /* mclk keep active */ 44 #define SOF_DAI_INTEL_SSP_CLKCTRL_MCLK_KA BIT(2) 45 /* bclk keep active */ 46 #define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_KA BIT(3) 47 /* fs keep active */ 48 #define SOF_DAI_INTEL_SSP_CLKCTRL_FS_KA BIT(4) 49 /* bclk idle */ 50 #define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_IDLE_HIGH BIT(5) 51 52 /* SSP Configuration Request - SOF_IPC_DAI_SSP_CONFIG */ 53 struct sof_ipc_dai_ssp_params { 54 struct sof_ipc_hdr hdr; 55 uint16_t reserved1; 56 uint16_t mclk_id; 57 58 uint32_t mclk_rate; /* mclk frequency in Hz */ 59 uint32_t fsync_rate; /* fsync frequency in Hz */ 60 uint32_t bclk_rate; /* bclk frequency in Hz */ 61 62 /* TDM */ 63 uint32_t tdm_slots; 64 uint32_t rx_slots; 65 uint32_t tx_slots; 66 67 /* data */ 68 uint32_t sample_valid_bits; 69 uint16_t tdm_slot_width; 70 uint16_t reserved2; /* alignment */ 71 72 /* MCLK */ 73 uint32_t mclk_direction; 74 75 uint16_t frame_pulse_width; 76 uint16_t tdm_per_slot_padding_flag; 77 uint32_t clks_control; 78 uint32_t quirks; 79 uint32_t bclk_delay; /* guaranteed time (ms) for which BCLK 80 * will be driven, before sending data 81 */ 82 } __packed; 83 84 /* HDA Configuration Request - SOF_IPC_DAI_HDA_CONFIG */ 85 struct sof_ipc_dai_hda_params { 86 struct sof_ipc_hdr hdr; 87 uint32_t link_dma_ch; 88 } __packed; 89 90 /* DMIC Configuration Request - SOF_IPC_DAI_DMIC_CONFIG */ 91 92 /* This struct is defined per 2ch PDM controller available in the platform. 93 * Normally it is sufficient to set the used microphone specific enables to 1 94 * and keep other parameters as zero. The customizations are: 95 * 96 * 1. If a device mixes different microphones types with different polarity 97 * and/or the absolute polarity matters the PCM signal from a microphone 98 * can be inverted with the controls. 99 * 100 * 2. If the microphones in a stereo pair do not appear in captured stream 101 * in desired order due to board schematics choises they can be swapped with 102 * the clk_edge parameter. 103 * 104 * 3. If PDM bit errors are seen in capture (poor quality) the skew parameter 105 * that delays the sampling time of data by half cycles of DMIC source clock 106 * can be tried for improvement. However there is no guarantee for this to fix 107 * data integrity problems. 108 */ 109 struct sof_ipc_dai_dmic_pdm_ctrl { 110 struct sof_ipc_hdr hdr; 111 uint16_t id; /**< PDM controller ID */ 112 113 uint16_t enable_mic_a; /**< Use A (left) channel mic (0 or 1)*/ 114 uint16_t enable_mic_b; /**< Use B (right) channel mic (0 or 1)*/ 115 116 uint16_t polarity_mic_a; /**< Optionally invert mic A signal (0 or 1) */ 117 uint16_t polarity_mic_b; /**< Optionally invert mic B signal (0 or 1) */ 118 119 uint16_t clk_edge; /**< Optionally swap data clock edge (0 or 1) */ 120 uint16_t skew; /**< Adjust PDM data sampling vs. clock (0..15) */ 121 122 uint16_t reserved[3]; /**< Make sure the total size is 4 bytes aligned */ 123 } __packed; 124 125 /* This struct contains the global settings for all 2ch PDM controllers. The 126 * version number used in configuration data is checked vs. version used by 127 * device driver src/drivers/dmic.c need to match. It is incremented from 128 * initial value 1 if updates done for the to driver would alter the operation 129 * of the microhone. 130 * 131 * Note: The microphone clock (pdmclk_min, pdmclk_max, duty_min, duty_max) 132 * parameters need to be set as defined in microphone data sheet. E.g. clock 133 * range 1.0 - 3.2 MHz is usually supported microphones. Some microphones are 134 * multi-mode capable and there may be denied mic clock frequencies between 135 * the modes. In such case set the clock range limits of the desired mode to 136 * avoid the driver to set clock to an illegal rate. 137 * 138 * The duty cycle could be set to 48-52% if not known. Generally these 139 * parameters can be altered within data sheet specified limits to match 140 * required audio application performance power. 141 * 142 * The microphone clock needs to be usually about 50-80 times the used audio 143 * sample rate. With highest sample rates above 48 kHz this can relaxed 144 * somewhat. 145 * 146 * The parameter wake_up_time describes how long time the microphone needs 147 * for the data line to produce valid output from mic clock start. The driver 148 * will mute the captured audio for the given time. The min_clock_on_time 149 * parameter is used to prevent too short clock bursts to happen. The driver 150 * will keep the clock active after capture stop if this time is not yet 151 * met. The unit for both is microseconds (us). Exceed of 100 ms will be 152 * treated as an error. 153 */ 154 struct sof_ipc_dai_dmic_params { 155 struct sof_ipc_hdr hdr; 156 uint32_t driver_ipc_version; /**< Version (1..N) */ 157 158 uint32_t pdmclk_min; /**< Minimum microphone clock in Hz (100000..N) */ 159 uint32_t pdmclk_max; /**< Maximum microphone clock in Hz (min...N) */ 160 161 uint32_t fifo_fs; /**< FIFO sample rate in Hz (8000..96000) */ 162 uint32_t reserved_1; /**< Reserved */ 163 uint16_t fifo_bits; /**< FIFO word length (16 or 32) */ 164 uint16_t reserved_2; /**< Reserved */ 165 166 uint16_t duty_min; /**< Min. mic clock duty cycle in % (20..80) */ 167 uint16_t duty_max; /**< Max. mic clock duty cycle in % (min..80) */ 168 169 uint32_t num_pdm_active; /**< Number of active pdm controllers */ 170 171 uint32_t wake_up_time; /**< Time from clock start to data (us) */ 172 uint32_t min_clock_on_time; /**< Min. time that clk is kept on (us) */ 173 uint32_t unmute_ramp_time; /**< Length of logarithmic gain ramp (ms) */ 174 175 /* reserved for future use */ 176 uint32_t reserved[5]; 177 178 /**< variable number of pdm controller config */ 179 struct sof_ipc_dai_dmic_pdm_ctrl pdm[0]; 180 } __packed; 181 182 /* ALH Configuration Request - SOF_IPC_DAI_ALH_CONFIG */ 183 struct sof_ipc_dai_alh_params { 184 struct sof_ipc_hdr hdr; 185 uint32_t stream_id; 186 187 /* reserved for future use */ 188 uint32_t reserved[15]; 189 } __packed; 190 191 #endif 192