1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * HD-audio core stuff 4 */ 5 6 #ifndef __SOUND_HDAUDIO_H 7 #define __SOUND_HDAUDIO_H 8 9 #include <linux/device.h> 10 #include <linux/interrupt.h> 11 #include <linux/timecounter.h> 12 #include <sound/core.h> 13 #include <sound/memalloc.h> 14 #include <sound/hda_verbs.h> 15 #include <drm/i915_component.h> 16 17 /* codec node id */ 18 typedef u16 hda_nid_t; 19 20 struct hdac_bus; 21 struct hdac_stream; 22 struct hdac_device; 23 struct hdac_driver; 24 struct hdac_widget_tree; 25 struct hda_device_id; 26 27 /* 28 * exported bus type 29 */ 30 extern struct bus_type snd_hda_bus_type; 31 32 /* 33 * generic arrays 34 */ 35 struct snd_array { 36 unsigned int used; 37 unsigned int alloced; 38 unsigned int elem_size; 39 unsigned int alloc_align; 40 void *list; 41 }; 42 43 /* 44 * HD-audio codec base device 45 */ 46 struct hdac_device { 47 struct device dev; 48 int type; 49 struct hdac_bus *bus; 50 unsigned int addr; /* codec address */ 51 struct list_head list; /* list point for bus codec_list */ 52 53 hda_nid_t afg; /* AFG node id */ 54 hda_nid_t mfg; /* MFG node id */ 55 56 /* ids */ 57 unsigned int vendor_id; 58 unsigned int subsystem_id; 59 unsigned int revision_id; 60 unsigned int afg_function_id; 61 unsigned int mfg_function_id; 62 unsigned int afg_unsol:1; 63 unsigned int mfg_unsol:1; 64 65 unsigned int power_caps; /* FG power caps */ 66 67 const char *vendor_name; /* codec vendor name */ 68 const char *chip_name; /* codec chip name */ 69 70 /* verb exec op override */ 71 int (*exec_verb)(struct hdac_device *dev, unsigned int cmd, 72 unsigned int flags, unsigned int *res); 73 74 /* widgets */ 75 unsigned int num_nodes; 76 hda_nid_t start_nid, end_nid; 77 78 /* misc flags */ 79 atomic_t in_pm; /* suspend/resume being performed */ 80 bool link_power_control:1; 81 82 /* sysfs */ 83 struct hdac_widget_tree *widgets; 84 85 /* regmap */ 86 struct regmap *regmap; 87 struct snd_array vendor_verbs; 88 bool lazy_cache:1; /* don't wake up for writes */ 89 bool caps_overwriting:1; /* caps overwrite being in process */ 90 bool cache_coef:1; /* cache COEF read/write too */ 91 }; 92 93 /* device/driver type used for matching */ 94 enum { 95 HDA_DEV_CORE, 96 HDA_DEV_LEGACY, 97 HDA_DEV_ASOC, 98 }; 99 100 /* direction */ 101 enum { 102 HDA_INPUT, HDA_OUTPUT 103 }; 104 105 #define dev_to_hdac_dev(_dev) container_of(_dev, struct hdac_device, dev) 106 107 int snd_hdac_device_init(struct hdac_device *dev, struct hdac_bus *bus, 108 const char *name, unsigned int addr); 109 void snd_hdac_device_exit(struct hdac_device *dev); 110 int snd_hdac_device_register(struct hdac_device *codec); 111 void snd_hdac_device_unregister(struct hdac_device *codec); 112 int snd_hdac_device_set_chip_name(struct hdac_device *codec, const char *name); 113 int snd_hdac_codec_modalias(struct hdac_device *hdac, char *buf, size_t size); 114 115 int snd_hdac_refresh_widgets(struct hdac_device *codec, bool sysfs); 116 117 unsigned int snd_hdac_make_cmd(struct hdac_device *codec, hda_nid_t nid, 118 unsigned int verb, unsigned int parm); 119 int snd_hdac_exec_verb(struct hdac_device *codec, unsigned int cmd, 120 unsigned int flags, unsigned int *res); 121 int snd_hdac_read(struct hdac_device *codec, hda_nid_t nid, 122 unsigned int verb, unsigned int parm, unsigned int *res); 123 int _snd_hdac_read_parm(struct hdac_device *codec, hda_nid_t nid, int parm, 124 unsigned int *res); 125 int snd_hdac_read_parm_uncached(struct hdac_device *codec, hda_nid_t nid, 126 int parm); 127 int snd_hdac_override_parm(struct hdac_device *codec, hda_nid_t nid, 128 unsigned int parm, unsigned int val); 129 int snd_hdac_get_connections(struct hdac_device *codec, hda_nid_t nid, 130 hda_nid_t *conn_list, int max_conns); 131 int snd_hdac_get_sub_nodes(struct hdac_device *codec, hda_nid_t nid, 132 hda_nid_t *start_id); 133 unsigned int snd_hdac_calc_stream_format(unsigned int rate, 134 unsigned int channels, 135 unsigned int format, 136 unsigned int maxbps, 137 unsigned short spdif_ctls); 138 int snd_hdac_query_supported_pcm(struct hdac_device *codec, hda_nid_t nid, 139 u32 *ratesp, u64 *formatsp, unsigned int *bpsp); 140 bool snd_hdac_is_supported_format(struct hdac_device *codec, hda_nid_t nid, 141 unsigned int format); 142 143 int snd_hdac_codec_read(struct hdac_device *hdac, hda_nid_t nid, 144 int flags, unsigned int verb, unsigned int parm); 145 int snd_hdac_codec_write(struct hdac_device *hdac, hda_nid_t nid, 146 int flags, unsigned int verb, unsigned int parm); 147 bool snd_hdac_check_power_state(struct hdac_device *hdac, 148 hda_nid_t nid, unsigned int target_state); 149 /** 150 * snd_hdac_read_parm - read a codec parameter 151 * @codec: the codec object 152 * @nid: NID to read a parameter 153 * @parm: parameter to read 154 * 155 * Returns -1 for error. If you need to distinguish the error more 156 * strictly, use _snd_hdac_read_parm() directly. 157 */ 158 static inline int snd_hdac_read_parm(struct hdac_device *codec, hda_nid_t nid, 159 int parm) 160 { 161 unsigned int val; 162 163 return _snd_hdac_read_parm(codec, nid, parm, &val) < 0 ? -1 : val; 164 } 165 166 #ifdef CONFIG_PM 167 int snd_hdac_power_up(struct hdac_device *codec); 168 int snd_hdac_power_down(struct hdac_device *codec); 169 int snd_hdac_power_up_pm(struct hdac_device *codec); 170 int snd_hdac_power_down_pm(struct hdac_device *codec); 171 int snd_hdac_keep_power_up(struct hdac_device *codec); 172 #else 173 static inline int snd_hdac_power_up(struct hdac_device *codec) { return 0; } 174 static inline int snd_hdac_power_down(struct hdac_device *codec) { return 0; } 175 static inline int snd_hdac_power_up_pm(struct hdac_device *codec) { return 0; } 176 static inline int snd_hdac_power_down_pm(struct hdac_device *codec) { return 0; } 177 static inline int snd_hdac_keep_power_up(struct hdac_device *codec) { return 0; } 178 #endif 179 180 /* 181 * HD-audio codec base driver 182 */ 183 struct hdac_driver { 184 struct device_driver driver; 185 int type; 186 const struct hda_device_id *id_table; 187 int (*match)(struct hdac_device *dev, struct hdac_driver *drv); 188 void (*unsol_event)(struct hdac_device *dev, unsigned int event); 189 }; 190 191 #define drv_to_hdac_driver(_drv) container_of(_drv, struct hdac_driver, driver) 192 193 const struct hda_device_id * 194 hdac_get_device_id(struct hdac_device *hdev, struct hdac_driver *drv); 195 196 /* 197 * Bus verb operators 198 */ 199 struct hdac_bus_ops { 200 /* send a single command */ 201 int (*command)(struct hdac_bus *bus, unsigned int cmd); 202 /* get a response from the last command */ 203 int (*get_response)(struct hdac_bus *bus, unsigned int addr, 204 unsigned int *res); 205 /* control the link power */ 206 int (*link_power)(struct hdac_bus *bus, bool enable); 207 }; 208 209 /* 210 * Lowlevel I/O operators 211 */ 212 struct hdac_io_ops { 213 /* mapped register accesses */ 214 void (*reg_writel)(u32 value, u32 __iomem *addr); 215 u32 (*reg_readl)(u32 __iomem *addr); 216 void (*reg_writew)(u16 value, u16 __iomem *addr); 217 u16 (*reg_readw)(u16 __iomem *addr); 218 void (*reg_writeb)(u8 value, u8 __iomem *addr); 219 u8 (*reg_readb)(u8 __iomem *addr); 220 /* Allocation ops */ 221 int (*dma_alloc_pages)(struct hdac_bus *bus, int type, size_t size, 222 struct snd_dma_buffer *buf); 223 void (*dma_free_pages)(struct hdac_bus *bus, 224 struct snd_dma_buffer *buf); 225 }; 226 227 #define HDA_UNSOL_QUEUE_SIZE 64 228 #define HDA_MAX_CODECS 8 /* limit by controller side */ 229 230 /* HD Audio class code */ 231 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403 232 233 /* 234 * CORB/RIRB 235 * 236 * Each CORB entry is 4byte, RIRB is 8byte 237 */ 238 struct hdac_rb { 239 __le32 *buf; /* virtual address of CORB/RIRB buffer */ 240 dma_addr_t addr; /* physical address of CORB/RIRB buffer */ 241 unsigned short rp, wp; /* RIRB read/write pointers */ 242 int cmds[HDA_MAX_CODECS]; /* number of pending requests */ 243 u32 res[HDA_MAX_CODECS]; /* last read value */ 244 }; 245 246 /* 247 * HD-audio bus base driver 248 * 249 * @ppcap: pp capabilities pointer 250 * @spbcap: SPIB capabilities pointer 251 * @mlcap: MultiLink capabilities pointer 252 * @gtscap: gts capabilities pointer 253 * @drsmcap: dma resume capabilities pointer 254 */ 255 struct hdac_bus { 256 struct device *dev; 257 const struct hdac_bus_ops *ops; 258 const struct hdac_io_ops *io_ops; 259 260 /* h/w resources */ 261 unsigned long addr; 262 void __iomem *remap_addr; 263 int irq; 264 265 void __iomem *ppcap; 266 void __iomem *spbcap; 267 void __iomem *mlcap; 268 void __iomem *gtscap; 269 void __iomem *drsmcap; 270 271 /* codec linked list */ 272 struct list_head codec_list; 273 unsigned int num_codecs; 274 275 /* link caddr -> codec */ 276 struct hdac_device *caddr_tbl[HDA_MAX_CODEC_ADDRESS + 1]; 277 278 /* unsolicited event queue */ 279 u32 unsol_queue[HDA_UNSOL_QUEUE_SIZE * 2]; /* ring buffer */ 280 unsigned int unsol_rp, unsol_wp; 281 struct work_struct unsol_work; 282 283 /* bit flags of detected codecs */ 284 unsigned long codec_mask; 285 286 /* bit flags of powered codecs */ 287 unsigned long codec_powered; 288 289 /* CORB/RIRB */ 290 struct hdac_rb corb; 291 struct hdac_rb rirb; 292 unsigned int last_cmd[HDA_MAX_CODECS]; /* last sent command */ 293 294 /* CORB/RIRB and position buffers */ 295 struct snd_dma_buffer rb; 296 struct snd_dma_buffer posbuf; 297 298 /* hdac_stream linked list */ 299 struct list_head stream_list; 300 301 /* operation state */ 302 bool chip_init:1; /* h/w initialized */ 303 304 /* behavior flags */ 305 bool sync_write:1; /* sync after verb write */ 306 bool use_posbuf:1; /* use position buffer */ 307 bool snoop:1; /* enable snooping */ 308 bool align_bdle_4k:1; /* BDLE align 4K boundary */ 309 bool reverse_assign:1; /* assign devices in reverse order */ 310 bool corbrp_self_clear:1; /* CORBRP clears itself after reset */ 311 312 int bdl_pos_adj; /* BDL position adjustment */ 313 314 /* locks */ 315 spinlock_t reg_lock; 316 struct mutex cmd_mutex; 317 318 /* i915 component interface */ 319 struct i915_audio_component *audio_component; 320 int i915_power_refcount; 321 }; 322 323 int snd_hdac_bus_init(struct hdac_bus *bus, struct device *dev, 324 const struct hdac_bus_ops *ops, 325 const struct hdac_io_ops *io_ops); 326 void snd_hdac_bus_exit(struct hdac_bus *bus); 327 int snd_hdac_bus_exec_verb(struct hdac_bus *bus, unsigned int addr, 328 unsigned int cmd, unsigned int *res); 329 int snd_hdac_bus_exec_verb_unlocked(struct hdac_bus *bus, unsigned int addr, 330 unsigned int cmd, unsigned int *res); 331 void snd_hdac_bus_queue_event(struct hdac_bus *bus, u32 res, u32 res_ex); 332 333 int snd_hdac_bus_add_device(struct hdac_bus *bus, struct hdac_device *codec); 334 void snd_hdac_bus_remove_device(struct hdac_bus *bus, 335 struct hdac_device *codec); 336 337 static inline void snd_hdac_codec_link_up(struct hdac_device *codec) 338 { 339 set_bit(codec->addr, &codec->bus->codec_powered); 340 } 341 342 static inline void snd_hdac_codec_link_down(struct hdac_device *codec) 343 { 344 clear_bit(codec->addr, &codec->bus->codec_powered); 345 } 346 347 int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val); 348 int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr, 349 unsigned int *res); 350 int snd_hdac_bus_parse_capabilities(struct hdac_bus *bus); 351 int snd_hdac_link_power(struct hdac_device *codec, bool enable); 352 353 bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset); 354 void snd_hdac_bus_stop_chip(struct hdac_bus *bus); 355 void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus); 356 void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus); 357 void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus); 358 void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus); 359 360 void snd_hdac_bus_update_rirb(struct hdac_bus *bus); 361 int snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status, 362 void (*ack)(struct hdac_bus *, 363 struct hdac_stream *)); 364 365 int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus); 366 void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus); 367 368 /* 369 * macros for easy use 370 */ 371 #define _snd_hdac_chip_writeb(chip, reg, value) \ 372 ((chip)->io_ops->reg_writeb(value, (chip)->remap_addr + (reg))) 373 #define _snd_hdac_chip_readb(chip, reg) \ 374 ((chip)->io_ops->reg_readb((chip)->remap_addr + (reg))) 375 #define _snd_hdac_chip_writew(chip, reg, value) \ 376 ((chip)->io_ops->reg_writew(value, (chip)->remap_addr + (reg))) 377 #define _snd_hdac_chip_readw(chip, reg) \ 378 ((chip)->io_ops->reg_readw((chip)->remap_addr + (reg))) 379 #define _snd_hdac_chip_writel(chip, reg, value) \ 380 ((chip)->io_ops->reg_writel(value, (chip)->remap_addr + (reg))) 381 #define _snd_hdac_chip_readl(chip, reg) \ 382 ((chip)->io_ops->reg_readl((chip)->remap_addr + (reg))) 383 384 /* read/write a register, pass without AZX_REG_ prefix */ 385 #define snd_hdac_chip_writel(chip, reg, value) \ 386 _snd_hdac_chip_writel(chip, AZX_REG_ ## reg, value) 387 #define snd_hdac_chip_writew(chip, reg, value) \ 388 _snd_hdac_chip_writew(chip, AZX_REG_ ## reg, value) 389 #define snd_hdac_chip_writeb(chip, reg, value) \ 390 _snd_hdac_chip_writeb(chip, AZX_REG_ ## reg, value) 391 #define snd_hdac_chip_readl(chip, reg) \ 392 _snd_hdac_chip_readl(chip, AZX_REG_ ## reg) 393 #define snd_hdac_chip_readw(chip, reg) \ 394 _snd_hdac_chip_readw(chip, AZX_REG_ ## reg) 395 #define snd_hdac_chip_readb(chip, reg) \ 396 _snd_hdac_chip_readb(chip, AZX_REG_ ## reg) 397 398 /* update a register, pass without AZX_REG_ prefix */ 399 #define snd_hdac_chip_updatel(chip, reg, mask, val) \ 400 snd_hdac_chip_writel(chip, reg, \ 401 (snd_hdac_chip_readl(chip, reg) & ~(mask)) | (val)) 402 #define snd_hdac_chip_updatew(chip, reg, mask, val) \ 403 snd_hdac_chip_writew(chip, reg, \ 404 (snd_hdac_chip_readw(chip, reg) & ~(mask)) | (val)) 405 #define snd_hdac_chip_updateb(chip, reg, mask, val) \ 406 snd_hdac_chip_writeb(chip, reg, \ 407 (snd_hdac_chip_readb(chip, reg) & ~(mask)) | (val)) 408 409 /* 410 * HD-audio stream 411 */ 412 struct hdac_stream { 413 struct hdac_bus *bus; 414 struct snd_dma_buffer bdl; /* BDL buffer */ 415 __le32 *posbuf; /* position buffer pointer */ 416 int direction; /* playback / capture (SNDRV_PCM_STREAM_*) */ 417 418 unsigned int bufsize; /* size of the play buffer in bytes */ 419 unsigned int period_bytes; /* size of the period in bytes */ 420 unsigned int frags; /* number for period in the play buffer */ 421 unsigned int fifo_size; /* FIFO size */ 422 423 void __iomem *sd_addr; /* stream descriptor pointer */ 424 425 u32 sd_int_sta_mask; /* stream int status mask */ 426 427 /* pcm support */ 428 struct snd_pcm_substream *substream; /* assigned substream, 429 * set in PCM open 430 */ 431 unsigned int format_val; /* format value to be set in the 432 * controller and the codec 433 */ 434 unsigned char stream_tag; /* assigned stream */ 435 unsigned char index; /* stream index */ 436 int assigned_key; /* last device# key assigned to */ 437 438 bool opened:1; 439 bool running:1; 440 bool prepared:1; 441 bool no_period_wakeup:1; 442 bool locked:1; 443 444 /* timestamp */ 445 unsigned long start_wallclk; /* start + minimum wallclk */ 446 unsigned long period_wallclk; /* wallclk for period */ 447 struct timecounter tc; 448 struct cyclecounter cc; 449 int delay_negative_threshold; 450 451 struct list_head list; 452 #ifdef CONFIG_SND_HDA_DSP_LOADER 453 /* DSP access mutex */ 454 struct mutex dsp_mutex; 455 #endif 456 }; 457 458 void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev, 459 int idx, int direction, int tag); 460 struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus, 461 struct snd_pcm_substream *substream); 462 void snd_hdac_stream_release(struct hdac_stream *azx_dev); 463 struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus, 464 int dir, int stream_tag); 465 466 int snd_hdac_stream_setup(struct hdac_stream *azx_dev); 467 void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev); 468 int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev); 469 int snd_hdac_stream_set_params(struct hdac_stream *azx_dev, 470 unsigned int format_val); 471 void snd_hdac_stream_start(struct hdac_stream *azx_dev, bool fresh_start); 472 void snd_hdac_stream_clear(struct hdac_stream *azx_dev); 473 void snd_hdac_stream_stop(struct hdac_stream *azx_dev); 474 void snd_hdac_stream_reset(struct hdac_stream *azx_dev); 475 void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set, 476 unsigned int streams, unsigned int reg); 477 void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start, 478 unsigned int streams); 479 void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev, 480 unsigned int streams); 481 /* 482 * macros for easy use 483 */ 484 #define _snd_hdac_stream_write(type, dev, reg, value) \ 485 ((dev)->bus->io_ops->reg_write ## type(value, (dev)->sd_addr + (reg))) 486 #define _snd_hdac_stream_read(type, dev, reg) \ 487 ((dev)->bus->io_ops->reg_read ## type((dev)->sd_addr + (reg))) 488 489 /* read/write a register, pass without AZX_REG_ prefix */ 490 #define snd_hdac_stream_writel(dev, reg, value) \ 491 _snd_hdac_stream_write(l, dev, AZX_REG_ ## reg, value) 492 #define snd_hdac_stream_writew(dev, reg, value) \ 493 _snd_hdac_stream_write(w, dev, AZX_REG_ ## reg, value) 494 #define snd_hdac_stream_writeb(dev, reg, value) \ 495 _snd_hdac_stream_write(b, dev, AZX_REG_ ## reg, value) 496 #define snd_hdac_stream_readl(dev, reg) \ 497 _snd_hdac_stream_read(l, dev, AZX_REG_ ## reg) 498 #define snd_hdac_stream_readw(dev, reg) \ 499 _snd_hdac_stream_read(w, dev, AZX_REG_ ## reg) 500 #define snd_hdac_stream_readb(dev, reg) \ 501 _snd_hdac_stream_read(b, dev, AZX_REG_ ## reg) 502 503 /* update a register, pass without AZX_REG_ prefix */ 504 #define snd_hdac_stream_updatel(dev, reg, mask, val) \ 505 snd_hdac_stream_writel(dev, reg, \ 506 (snd_hdac_stream_readl(dev, reg) & \ 507 ~(mask)) | (val)) 508 #define snd_hdac_stream_updatew(dev, reg, mask, val) \ 509 snd_hdac_stream_writew(dev, reg, \ 510 (snd_hdac_stream_readw(dev, reg) & \ 511 ~(mask)) | (val)) 512 #define snd_hdac_stream_updateb(dev, reg, mask, val) \ 513 snd_hdac_stream_writeb(dev, reg, \ 514 (snd_hdac_stream_readb(dev, reg) & \ 515 ~(mask)) | (val)) 516 517 #ifdef CONFIG_SND_HDA_DSP_LOADER 518 /* DSP lock helpers */ 519 #define snd_hdac_dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex) 520 #define snd_hdac_dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex) 521 #define snd_hdac_dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex) 522 #define snd_hdac_stream_is_locked(dev) ((dev)->locked) 523 /* DSP loader helpers */ 524 int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format, 525 unsigned int byte_size, struct snd_dma_buffer *bufp); 526 void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start); 527 void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev, 528 struct snd_dma_buffer *dmab); 529 #else /* CONFIG_SND_HDA_DSP_LOADER */ 530 #define snd_hdac_dsp_lock_init(dev) do {} while (0) 531 #define snd_hdac_dsp_lock(dev) do {} while (0) 532 #define snd_hdac_dsp_unlock(dev) do {} while (0) 533 #define snd_hdac_stream_is_locked(dev) 0 534 535 static inline int 536 snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format, 537 unsigned int byte_size, struct snd_dma_buffer *bufp) 538 { 539 return 0; 540 } 541 542 static inline void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start) 543 { 544 } 545 546 static inline void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev, 547 struct snd_dma_buffer *dmab) 548 { 549 } 550 #endif /* CONFIG_SND_HDA_DSP_LOADER */ 551 552 553 /* 554 * generic array helpers 555 */ 556 void *snd_array_new(struct snd_array *array); 557 void snd_array_free(struct snd_array *array); 558 static inline void snd_array_init(struct snd_array *array, unsigned int size, 559 unsigned int align) 560 { 561 array->elem_size = size; 562 array->alloc_align = align; 563 } 564 565 static inline void *snd_array_elem(struct snd_array *array, unsigned int idx) 566 { 567 return array->list + idx * array->elem_size; 568 } 569 570 static inline unsigned int snd_array_index(struct snd_array *array, void *ptr) 571 { 572 return (unsigned long)(ptr - array->list) / array->elem_size; 573 } 574 575 #endif /* __SOUND_HDAUDIO_H */ 576