1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>, 4 * Creative Labs, Inc. 5 * Definitions for EMU10K1 (SB Live!) chips 6 */ 7 #ifndef __SOUND_EMU10K1_H 8 #define __SOUND_EMU10K1_H 9 10 11 #include <sound/pcm.h> 12 #include <sound/rawmidi.h> 13 #include <sound/hwdep.h> 14 #include <sound/ac97_codec.h> 15 #include <sound/util_mem.h> 16 #include <sound/pcm-indirect.h> 17 #include <sound/timer.h> 18 #include <linux/interrupt.h> 19 #include <linux/mutex.h> 20 #include <linux/firmware.h> 21 #include <linux/io.h> 22 23 #include <uapi/sound/emu10k1.h> 24 25 /* ------------------- DEFINES -------------------- */ 26 27 #define EMUPAGESIZE 4096 28 #define MAXPAGES0 4096 /* 32 bit mode */ 29 #define MAXPAGES1 8192 /* 31 bit mode */ 30 #define NUM_G 64 /* use all channels */ 31 #define NUM_EFX_PLAYBACK 16 32 33 /* FIXME? - according to the OSS driver the EMU10K1 needs a 29 bit DMA mask */ 34 #define EMU10K1_DMA_MASK 0x7fffffffUL /* 31bit */ 35 #define AUDIGY_DMA_MASK 0xffffffffUL /* 32bit mode */ 36 37 #define TMEMSIZE 256*1024 38 39 #define IP_TO_CP(ip) ((ip == 0) ? 0 : (((0x00001000uL | (ip & 0x00000FFFL)) << (((ip >> 12) & 0x000FL) + 4)) & 0xFFFF0000uL)) 40 41 // This is used to define hardware bit-fields (sub-registers) by combining 42 // the bit shift and count with the actual register address. The passed 43 // mask must represent a single run of adjacent bits. 44 // The non-concatenating (_NC) variant should be used directly only for 45 // sub-registers that do not follow the <register>_<field> naming pattern. 46 #define SUB_REG_NC(reg, field, mask) \ 47 enum { \ 48 field ## _MASK = mask, \ 49 field = reg | \ 50 (__builtin_ctz(mask) << 16) | \ 51 (__builtin_popcount(mask) << 24), \ 52 }; 53 #define SUB_REG(reg, field, mask) SUB_REG_NC(reg, reg ## _ ## field, mask) 54 55 // Macros for manipulating values of bit-fields declared using the above macros. 56 // Best used with constant register addresses, as otherwise quite some code is 57 // generated. The actual register read/write functions handle combined addresses 58 // automatically, so use of these macros conveys no advantage when accessing a 59 // single sub-register at a time. 60 #define REG_SHIFT(r) (((r) >> 16) & 0x1f) 61 #define REG_SIZE(r) (((r) >> 24) & 0x1f) 62 #define REG_MASK0(r) ((1U << REG_SIZE(r)) - 1U) 63 #define REG_MASK(r) (REG_MASK0(r) << REG_SHIFT(r)) 64 #define REG_VAL_GET(r, v) ((v & REG_MASK(r)) >> REG_SHIFT(r)) 65 #define REG_VAL_PUT(r, v) ((v) << REG_SHIFT(r)) 66 67 // List terminator for snd_emu10k1_ptr_write_multiple() 68 #define REGLIST_END ~0 69 70 // Audigy specify registers are prefixed with 'A_' 71 72 /************************************************************************************************/ 73 /* PCI function 0 registers, address = <val> + PCIBASE0 */ 74 /************************************************************************************************/ 75 76 #define PTR 0x00 /* Indexed register set pointer register */ 77 /* NOTE: The CHANNELNUM and ADDRESS words can */ 78 /* be modified independently of each other. */ 79 #define PTR_CHANNELNUM_MASK 0x0000003f /* For each per-channel register, indicates the */ 80 /* channel number of the register to be */ 81 /* accessed. For non per-channel registers the */ 82 /* value should be set to zero. */ 83 #define PTR_ADDRESS_MASK 0x07ff0000 /* Register index */ 84 #define A_PTR_ADDRESS_MASK 0x0fff0000 85 86 #define DATA 0x04 /* Indexed register set data register */ 87 88 #define IPR 0x08 /* Global interrupt pending register */ 89 /* Clear pending interrupts by writing a 1 to */ 90 /* the relevant bits and zero to the other bits */ 91 #define IPR_P16V 0x80000000 /* Bit set when the CA0151 P16V chip wishes 92 to interrupt */ 93 #define IPR_WATERMARK_REACHED 0x40000000 94 #define IPR_A_GPIO 0x20000000 /* GPIO input pin change */ 95 96 /* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */ 97 #define IPR_A_MIDITRANSBUFEMPTY2 0x10000000 /* MIDI UART transmit buffer empty */ 98 #define IPR_A_MIDIRECVBUFEMPTY2 0x08000000 /* MIDI UART receive buffer empty */ 99 100 #define IPR_SPDIFBUFFULL 0x04000000 /* SPDIF capture related, 10k2 only? (RE) */ 101 #define IPR_SPDIFBUFHALFFULL 0x02000000 /* SPDIF capture related? (RE) */ 102 103 #define IPR_SAMPLERATETRACKER 0x01000000 /* Sample rate tracker lock status change */ 104 #define IPR_FXDSP 0x00800000 /* Enable FX DSP interrupts */ 105 #define IPR_FORCEINT 0x00400000 /* Force Sound Blaster interrupt */ 106 #define IPR_PCIERROR 0x00200000 /* PCI bus error */ 107 #define IPR_VOLINCR 0x00100000 /* Volume increment button pressed */ 108 #define IPR_VOLDECR 0x00080000 /* Volume decrement button pressed */ 109 #define IPR_MUTE 0x00040000 /* Mute button pressed */ 110 #define IPR_MICBUFFULL 0x00020000 /* Microphone buffer full */ 111 #define IPR_MICBUFHALFFULL 0x00010000 /* Microphone buffer half full */ 112 #define IPR_ADCBUFFULL 0x00008000 /* ADC buffer full */ 113 #define IPR_ADCBUFHALFFULL 0x00004000 /* ADC buffer half full */ 114 #define IPR_EFXBUFFULL 0x00002000 /* Effects buffer full */ 115 #define IPR_EFXBUFHALFFULL 0x00001000 /* Effects buffer half full */ 116 #define IPR_GPSPDIFSTATUSCHANGE 0x00000800 /* GPSPDIF channel status change */ 117 #define IPR_CDROMSTATUSCHANGE 0x00000400 /* CD-ROM channel status change */ 118 #define IPR_INTERVALTIMER 0x00000200 /* Interval timer terminal count */ 119 #define IPR_MIDITRANSBUFEMPTY 0x00000100 /* MIDI UART transmit buffer empty */ 120 #define IPR_MIDIRECVBUFEMPTY 0x00000080 /* MIDI UART receive buffer empty */ 121 #define IPR_CHANNELLOOP 0x00000040 /* Channel (half) loop interrupt(s) pending */ 122 /* The interrupt is triggered shortly after */ 123 /* CCR_READADDRESS has crossed the boundary; */ 124 /* due to the cache, this runs ahead of the */ 125 /* actual playback position. */ 126 #define IPR_CHANNELNUMBERMASK 0x0000003f /* When IPR_CHANNELLOOP is set, indicates the */ 127 /* highest set channel in CLIPL, CLIPH, HLIPL, */ 128 /* or HLIPH. When IPR is written with CL set, */ 129 /* the bit in H/CLIPL or H/CLIPH corresponding */ 130 /* to the CN value written will be cleared. */ 131 132 #define INTE 0x0c /* Interrupt enable register */ 133 #define INTE_VIRTUALSB_MASK 0xc0000000 /* Virtual Soundblaster I/O port capture */ 134 #define INTE_VIRTUALSB_220 0x00000000 /* Capture at I/O base address 0x220-0x22f */ 135 #define INTE_VIRTUALSB_240 0x40000000 /* Capture at I/O base address 0x240 */ 136 #define INTE_VIRTUALSB_260 0x80000000 /* Capture at I/O base address 0x260 */ 137 #define INTE_VIRTUALSB_280 0xc0000000 /* Capture at I/O base address 0x280 */ 138 #define INTE_VIRTUALMPU_MASK 0x30000000 /* Virtual MPU I/O port capture */ 139 #define INTE_VIRTUALMPU_300 0x00000000 /* Capture at I/O base address 0x300-0x301 */ 140 #define INTE_VIRTUALMPU_310 0x10000000 /* Capture at I/O base address 0x310 */ 141 #define INTE_VIRTUALMPU_320 0x20000000 /* Capture at I/O base address 0x320 */ 142 #define INTE_VIRTUALMPU_330 0x30000000 /* Capture at I/O base address 0x330 */ 143 #define INTE_MASTERDMAENABLE 0x08000000 /* Master DMA emulation at 0x000-0x00f */ 144 #define INTE_SLAVEDMAENABLE 0x04000000 /* Slave DMA emulation at 0x0c0-0x0df */ 145 #define INTE_MASTERPICENABLE 0x02000000 /* Master PIC emulation at 0x020-0x021 */ 146 #define INTE_SLAVEPICENABLE 0x01000000 /* Slave PIC emulation at 0x0a0-0x0a1 */ 147 #define INTE_VSBENABLE 0x00800000 /* Enable virtual Soundblaster */ 148 #define INTE_ADLIBENABLE 0x00400000 /* Enable AdLib emulation at 0x388-0x38b */ 149 #define INTE_MPUENABLE 0x00200000 /* Enable virtual MPU */ 150 #define INTE_FORCEINT 0x00100000 /* Continuously assert INTAN */ 151 152 #define INTE_MRHANDENABLE 0x00080000 /* Enable the "Mr. Hand" logic */ 153 /* NOTE: There is no reason to use this under */ 154 /* Linux, and it will cause odd hardware */ 155 /* behavior and possibly random segfaults and */ 156 /* lockups if enabled. */ 157 158 #define INTE_A_GPIOENABLE 0x00040000 /* Enable GPIO input change interrupts */ 159 160 /* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */ 161 #define INTE_A_MIDITXENABLE2 0x00020000 /* Enable MIDI transmit-buffer-empty interrupts */ 162 #define INTE_A_MIDIRXENABLE2 0x00010000 /* Enable MIDI receive-buffer-empty interrupts */ 163 164 #define INTE_A_SPDIF_BUFFULL_ENABLE 0x00008000 165 #define INTE_A_SPDIF_HALFBUFFULL_ENABLE 0x00004000 166 167 #define INTE_SAMPLERATETRACKER 0x00002000 /* Enable sample rate tracker interrupts */ 168 /* NOTE: This bit must always be enabled */ 169 #define INTE_FXDSPENABLE 0x00001000 /* Enable FX DSP interrupts */ 170 #define INTE_PCIERRORENABLE 0x00000800 /* Enable PCI bus error interrupts */ 171 #define INTE_VOLINCRENABLE 0x00000400 /* Enable volume increment button interrupts */ 172 #define INTE_VOLDECRENABLE 0x00000200 /* Enable volume decrement button interrupts */ 173 #define INTE_MUTEENABLE 0x00000100 /* Enable mute button interrupts */ 174 #define INTE_MICBUFENABLE 0x00000080 /* Enable microphone buffer interrupts */ 175 #define INTE_ADCBUFENABLE 0x00000040 /* Enable ADC buffer interrupts */ 176 #define INTE_EFXBUFENABLE 0x00000020 /* Enable Effects buffer interrupts */ 177 #define INTE_GPSPDIFENABLE 0x00000010 /* Enable GPSPDIF status interrupts */ 178 #define INTE_CDSPDIFENABLE 0x00000008 /* Enable CDSPDIF status interrupts */ 179 #define INTE_INTERVALTIMERENB 0x00000004 /* Enable interval timer interrupts */ 180 #define INTE_MIDITXENABLE 0x00000002 /* Enable MIDI transmit-buffer-empty interrupts */ 181 #define INTE_MIDIRXENABLE 0x00000001 /* Enable MIDI receive-buffer-empty interrupts */ 182 183 #define WC 0x10 /* Wall Clock register */ 184 SUB_REG(WC, SAMPLECOUNTER, 0x03FFFFC0) /* Sample periods elapsed since reset */ 185 SUB_REG(WC, CURRENTCHANNEL, 0x0000003F) /* Channel [0..63] currently being serviced */ 186 /* NOTE: Each channel takes 1/64th of a sample */ 187 /* period to be serviced. */ 188 189 #define HCFG 0x14 /* Hardware config register */ 190 /* NOTE: There is no reason to use the legacy */ 191 /* SoundBlaster emulation stuff described below */ 192 /* under Linux, and all kinds of weird hardware */ 193 /* behavior can result if you try. Don't. */ 194 #define HCFG_LEGACYFUNC_MASK 0xe0000000 /* Legacy function number */ 195 #define HCFG_LEGACYFUNC_MPU 0x00000000 /* Legacy MPU */ 196 #define HCFG_LEGACYFUNC_SB 0x40000000 /* Legacy SB */ 197 #define HCFG_LEGACYFUNC_AD 0x60000000 /* Legacy AD */ 198 #define HCFG_LEGACYFUNC_MPIC 0x80000000 /* Legacy MPIC */ 199 #define HCFG_LEGACYFUNC_MDMA 0xa0000000 /* Legacy MDMA */ 200 #define HCFG_LEGACYFUNC_SPCI 0xc0000000 /* Legacy SPCI */ 201 #define HCFG_LEGACYFUNC_SDMA 0xe0000000 /* Legacy SDMA */ 202 #define HCFG_IOCAPTUREADDR 0x1f000000 /* The 4 LSBs of the captured I/O address. */ 203 #define HCFG_LEGACYWRITE 0x00800000 /* 1 = write, 0 = read */ 204 #define HCFG_LEGACYWORD 0x00400000 /* 1 = word, 0 = byte */ 205 #define HCFG_LEGACYINT 0x00200000 /* 1 = legacy event captured. Write 1 to clear. */ 206 /* NOTE: The rest of the bits in this register */ 207 /* _are_ relevant under Linux. */ 208 #define HCFG_PUSH_BUTTON_ENABLE 0x00100000 /* Enables Volume Inc/Dec and Mute functions */ 209 #define HCFG_BAUD_RATE 0x00080000 /* 0 = 48kHz, 1 = 44.1kHz */ 210 #define HCFG_EXPANDED_MEM 0x00040000 /* 1 = any 16M of 4G addr, 0 = 32M of 2G addr */ 211 #define HCFG_CODECFORMAT_MASK 0x00030000 /* CODEC format */ 212 213 /* Specific to Alice2, CA0102 */ 214 215 #define HCFG_CODECFORMAT_AC97_1 0x00000000 /* AC97 CODEC format -- Ver 1.03 */ 216 #define HCFG_CODECFORMAT_AC97_2 0x00010000 /* AC97 CODEC format -- Ver 2.1 */ 217 #define HCFG_AUTOMUTE_ASYNC 0x00008000 /* When set, the async sample rate convertors */ 218 /* will automatically mute their output when */ 219 /* they are not rate-locked to the external */ 220 /* async audio source */ 221 #define HCFG_AUTOMUTE_SPDIF 0x00004000 /* When set, the async sample rate convertors */ 222 /* will automatically mute their output when */ 223 /* the SPDIF V-bit indicates invalid audio */ 224 #define HCFG_EMU32_SLAVE 0x00002000 /* 0 = Master, 1 = Slave. Slave for EMU1010 */ 225 #define HCFG_SLOW_RAMP 0x00001000 /* Increases Send Smoothing time constant */ 226 /* 0x00000800 not used on Alice2 */ 227 #define HCFG_PHASE_TRACK_MASK 0x00000700 /* When set, forces corresponding input to */ 228 /* phase track the previous input. */ 229 /* I2S0 can phase track the last S/PDIF input */ 230 #define HCFG_I2S_ASRC_ENABLE 0x00000070 /* When set, enables asynchronous sample rate */ 231 /* conversion for the corresponding */ 232 /* I2S format input */ 233 /* Rest of HCFG 0x0000000f same as below. LOCKSOUNDCACHE etc. */ 234 235 /* Older chips */ 236 237 #define HCFG_CODECFORMAT_AC97 0x00000000 /* AC97 CODEC format -- Primary Output */ 238 #define HCFG_CODECFORMAT_I2S 0x00010000 /* I2S CODEC format -- Secondary (Rear) Output */ 239 #define HCFG_GPINPUT0 0x00004000 /* External pin112 */ 240 #define HCFG_GPINPUT1 0x00002000 /* External pin110 */ 241 #define HCFG_GPOUTPUT_MASK 0x00001c00 /* External pins which may be controlled */ 242 #define HCFG_GPOUT0 0x00001000 /* External pin? (spdif enable on 5.1) */ 243 #define HCFG_GPOUT1 0x00000800 /* External pin? (IR) */ 244 #define HCFG_GPOUT2 0x00000400 /* External pin? (IR) */ 245 #define HCFG_JOYENABLE 0x00000200 /* Internal joystick enable */ 246 #define HCFG_PHASETRACKENABLE 0x00000100 /* Phase tracking enable */ 247 /* 1 = Force all 3 async digital inputs to use */ 248 /* the same async sample rate tracker (ZVIDEO) */ 249 #define HCFG_AC3ENABLE_MASK 0x000000e0 /* AC3 async input control - Not implemented */ 250 #define HCFG_AC3ENABLE_ZVIDEO 0x00000080 /* Channels 0 and 1 replace ZVIDEO */ 251 #define HCFG_AC3ENABLE_CDSPDIF 0x00000040 /* Channels 0 and 1 replace CDSPDIF */ 252 #define HCFG_AC3ENABLE_GPSPDIF 0x00000020 /* Channels 0 and 1 replace GPSPDIF */ 253 #define HCFG_AUTOMUTE 0x00000010 /* When set, the async sample rate convertors */ 254 /* will automatically mute their output when */ 255 /* they are not rate-locked to the external */ 256 /* async audio source */ 257 #define HCFG_LOCKSOUNDCACHE 0x00000008 /* 1 = Cancel bustmaster accesses to soundcache */ 258 /* NOTE: This should generally never be used. */ 259 SUB_REG(HCFG, LOCKTANKCACHE, 0x00000004) /* 1 = Cancel bustmaster accesses to tankcache */ 260 /* NOTE: This should generally never be used. */ 261 #define HCFG_MUTEBUTTONENABLE 0x00000002 /* 1 = Master mute button sets AUDIOENABLE = 0. */ 262 /* NOTE: This is a 'cheap' way to implement a */ 263 /* master mute function on the mute button, and */ 264 /* in general should not be used unless a more */ 265 /* sophisticated master mute function has not */ 266 /* been written. */ 267 #define HCFG_AUDIOENABLE 0x00000001 /* 0 = CODECs transmit zero-valued samples */ 268 /* Should be set to 1 when the EMU10K1 is */ 269 /* completely initialized. */ 270 271 // On Audigy, the MPU port moved to the 0x70-0x74 ptr registers 272 273 #define MUDATA 0x18 /* MPU401 data register (8 bits) */ 274 275 #define MUCMD 0x19 /* MPU401 command register (8 bits) */ 276 #define MUCMD_RESET 0xff /* RESET command */ 277 #define MUCMD_ENTERUARTMODE 0x3f /* Enter_UART_mode command */ 278 /* NOTE: All other commands are ignored */ 279 280 #define MUSTAT MUCMD /* MPU401 status register (8 bits) */ 281 #define MUSTAT_IRDYN 0x80 /* 0 = MIDI data or command ACK */ 282 #define MUSTAT_ORDYN 0x40 /* 0 = MUDATA can accept a command or data */ 283 284 #define A_GPIO 0x18 /* GPIO on Audigy card (16bits) */ 285 #define A_GPINPUT_MASK 0xff00 /* Alice/2 has 8 input pins */ 286 #define A3_GPINPUT_MASK 0x3f00 /* ... while Tina/2 has only 6 */ 287 #define A_GPOUTPUT_MASK 0x00ff 288 289 // The GPIO port is used for I/O config on Sound Blasters; 290 // card-specific info can be found in the emu_chip_details table. 291 // On E-MU cards the port is used as the interface to the FPGA. 292 293 // Audigy output/GPIO stuff taken from the kX drivers 294 #define A_IOCFG A_GPIO 295 #define A_IOCFG_GPOUT0 0x0044 /* analog/digital */ 296 #define A_IOCFG_DISABLE_ANALOG 0x0040 /* = 'enable' for Audigy2 (chiprev=4) */ 297 #define A_IOCFG_ENABLE_DIGITAL 0x0004 298 #define A_IOCFG_ENABLE_DIGITAL_AUDIGY4 0x0080 299 #define A_IOCFG_UNKNOWN_20 0x0020 300 #define A_IOCFG_DISABLE_AC97_FRONT 0x0080 /* turn off ac97 front -> front (10k2.1) */ 301 #define A_IOCFG_GPOUT1 0x0002 /* IR? drive's internal bypass (?) */ 302 #define A_IOCFG_GPOUT2 0x0001 /* IR */ 303 #define A_IOCFG_MULTIPURPOSE_JACK 0x2000 /* center+lfe+rear_center (a2/a2ex) */ 304 /* + digital for generic 10k2 */ 305 #define A_IOCFG_DIGITAL_JACK 0x1000 /* digital for a2 platinum */ 306 #define A_IOCFG_FRONT_JACK 0x4000 307 #define A_IOCFG_REAR_JACK 0x8000 308 #define A_IOCFG_PHONES_JACK 0x0100 /* LiveDrive */ 309 310 #define TIMER 0x1a /* Timer terminal count register */ 311 /* NOTE: After the rate is changed, a maximum */ 312 /* of 1024 sample periods should be allowed */ 313 /* before the new rate is guaranteed accurate. */ 314 #define TIMER_RATE_MASK 0x03ff /* Timer interrupt rate in sample periods */ 315 /* 0 == 1024 periods, [1..4] are not useful */ 316 317 #define AC97DATA 0x1c /* AC97 register set data register (16 bit) */ 318 319 #define AC97ADDRESS 0x1e /* AC97 register set address register (8 bit) */ 320 #define AC97ADDRESS_READY 0x80 /* Read-only bit, reflects CODEC READY signal */ 321 #define AC97ADDRESS_ADDRESS 0x7f /* Address of indexed AC97 register */ 322 323 /* Available on the Audigy 2 and Audigy 4 only. This is the P16V chip. */ 324 #define PTR2 0x20 /* Indexed register set pointer register */ 325 #define DATA2 0x24 /* Indexed register set data register */ 326 #define IPR2 0x28 /* P16V interrupt pending register */ 327 #define IPR2_PLAYBACK_CH_0_LOOP 0x00001000 /* Playback Channel 0 loop */ 328 #define IPR2_PLAYBACK_CH_0_HALF_LOOP 0x00000100 /* Playback Channel 0 half loop */ 329 #define IPR2_CAPTURE_CH_0_LOOP 0x00100000 /* Capture Channel 0 loop */ 330 #define IPR2_CAPTURE_CH_0_HALF_LOOP 0x00010000 /* Capture Channel 0 half loop */ 331 /* 0x00000100 Playback. Only in once per period. 332 * 0x00110000 Capture. Int on half buffer. 333 */ 334 #define INTE2 0x2c /* P16V Interrupt enable register. */ 335 #define INTE2_PLAYBACK_CH_0_LOOP 0x00001000 /* Playback Channel 0 loop */ 336 #define INTE2_PLAYBACK_CH_0_HALF_LOOP 0x00000100 /* Playback Channel 0 half loop */ 337 #define INTE2_PLAYBACK_CH_1_LOOP 0x00002000 /* Playback Channel 1 loop */ 338 #define INTE2_PLAYBACK_CH_1_HALF_LOOP 0x00000200 /* Playback Channel 1 half loop */ 339 #define INTE2_PLAYBACK_CH_2_LOOP 0x00004000 /* Playback Channel 2 loop */ 340 #define INTE2_PLAYBACK_CH_2_HALF_LOOP 0x00000400 /* Playback Channel 2 half loop */ 341 #define INTE2_PLAYBACK_CH_3_LOOP 0x00008000 /* Playback Channel 3 loop */ 342 #define INTE2_PLAYBACK_CH_3_HALF_LOOP 0x00000800 /* Playback Channel 3 half loop */ 343 #define INTE2_CAPTURE_CH_0_LOOP 0x00100000 /* Capture Channel 0 loop */ 344 #define INTE2_CAPTURE_CH_0_HALF_LOOP 0x00010000 /* Caputre Channel 0 half loop */ 345 #define HCFG2 0x34 /* Defaults: 0, win2000 sets it to 00004201 */ 346 /* 0x00000000 2-channel output. */ 347 /* 0x00000200 8-channel output. */ 348 /* 0x00000004 pauses stream/irq fail. */ 349 /* Rest of bits do nothing to sound output */ 350 /* bit 0: Enable P16V audio. 351 * bit 1: Lock P16V record memory cache. 352 * bit 2: Lock P16V playback memory cache. 353 * bit 3: Dummy record insert zero samples. 354 * bit 8: Record 8-channel in phase. 355 * bit 9: Playback 8-channel in phase. 356 * bit 11-12: Playback mixer attenuation: 0=0dB, 1=-6dB, 2=-12dB, 3=Mute. 357 * bit 13: Playback mixer enable. 358 * bit 14: Route SRC48 mixer output to fx engine. 359 * bit 15: Enable IEEE 1394 chip. 360 */ 361 #define IPR3 0x38 /* Cdif interrupt pending register */ 362 #define INTE3 0x3c /* Cdif interrupt enable register. */ 363 364 /************************************************************************************************/ 365 /* PCI function 1 registers, address = <val> + PCIBASE1 */ 366 /************************************************************************************************/ 367 368 #define JOYSTICK1 0x00 /* Analog joystick port register */ 369 #define JOYSTICK2 0x01 /* Analog joystick port register */ 370 #define JOYSTICK3 0x02 /* Analog joystick port register */ 371 #define JOYSTICK4 0x03 /* Analog joystick port register */ 372 #define JOYSTICK5 0x04 /* Analog joystick port register */ 373 #define JOYSTICK6 0x05 /* Analog joystick port register */ 374 #define JOYSTICK7 0x06 /* Analog joystick port register */ 375 #define JOYSTICK8 0x07 /* Analog joystick port register */ 376 377 /* When writing, any write causes JOYSTICK_COMPARATOR output enable to be pulsed on write. */ 378 /* When reading, use these bitfields: */ 379 #define JOYSTICK_BUTTONS 0x0f /* Joystick button data */ 380 #define JOYSTICK_COMPARATOR 0xf0 /* Joystick comparator data */ 381 382 /********************************************************************************************************/ 383 /* Emu10k1 pointer-offset register set, accessed through the PTR and DATA registers */ 384 /********************************************************************************************************/ 385 386 // No official documentation was released for EMU10K1, but some info 387 // about playback can be extrapolated from the EMU8K documents: 388 // "AWE32/EMU8000 Programmer’s Guide" (emu8kpgm.pdf) - registers 389 // "AWE32 Developer's Information Pack" (adip301.pdf) - high-level view 390 391 // The short version: 392 // - The engine has 64 playback channels, also called voices. The channels 393 // operate independently, except when paired for stereo (see below). 394 // - PCM samples are fetched into the cache; see description of CD0 below. 395 // - Samples are consumed at the rate CPF_CURRENTPITCH. 396 // - 8-bit samples are transformed upon use: cooked = (raw ^ 0x80) << 8 397 // - 8 samples are read at CCR_READADDRESS:CPF_FRACADDRESS and interpolated 398 // according to CCCA_INTERPROM_*. With CCCA_INTERPROM_0 selected and a zero 399 // CPF_FRACADDRESS, this results in CCR_READADDRESS[3] being used verbatim. 400 // - The value is multiplied by CVCF_CURRENTVOL. 401 // - The value goes through a filter with cutoff CVCF_CURRENTFILTER; 402 // delay stages Z1 and Z2. 403 // - The value is added by so-called `sends` to 4 (EMU10K1) / 8 (EMU10K2) 404 // of the 16 (EMU10K1) / 64 (EMU10K2) FX bus accumulators via FXRT*, 405 // multiplied by a per-send amount (*_FXSENDAMOUNT_*). 406 // The scaling of the send amounts is exponential-ish. 407 // - The DSP has a go at FXBUS* and outputs the values to EXTOUT* or EMU32OUT*. 408 // - The pitch, volume, and filter cutoff can be modulated by two envelope 409 // engines and two low frequency oscillators. 410 // - To avoid abrupt changes to the parameters (which may cause audible 411 // distortion), the modulation engine sets the target registers, towards 412 // which the current registers "swerve" gradually. 413 414 // For the odd channel in a stereo pair, these registers are meaningless: 415 // CPF_STEREO, CPF_CURRENTPITCH, PTRX_PITCHTARGET, CCR_CACHEINVALIDSIZE, 416 // PSST_LOOPSTARTADDR, DSL_LOOPENDADDR, CCCA_CURRADDR 417 // The somewhat non-obviously still meaningful ones are: 418 // CPF_STOP, CPF_FRACADDRESS, CCR_READADDRESS (!), 419 // CCCA_INTERPROM, CCCA_8BITSELECT (!) 420 // (The envelope engine is ignored here, as stereo matters only for verbatim playback.) 421 422 #define CPF 0x00 /* Current pitch and fraction register */ 423 SUB_REG(CPF, CURRENTPITCH, 0xffff0000) /* Current pitch (linear, 0x4000 == unity pitch shift) */ 424 #define CPF_STEREO_MASK 0x00008000 /* 1 = Even channel interleave, odd channel locked */ 425 SUB_REG(CPF, STOP, 0x00004000) /* 1 = Current pitch forced to 0 */ 426 /* Can be set only while matching bit in SOLEx is 1 */ 427 #define CPF_FRACADDRESS_MASK 0x00003fff /* Linear fractional address of the current channel */ 428 429 #define PTRX 0x01 /* Pitch target and send A/B amounts register */ 430 SUB_REG(PTRX, PITCHTARGET, 0xffff0000) /* Pitch target of specified channel */ 431 SUB_REG(PTRX, FXSENDAMOUNT_A, 0x0000ff00) /* Linear level of channel output sent to FX send bus A */ 432 SUB_REG(PTRX, FXSENDAMOUNT_B, 0x000000ff) /* Linear level of channel output sent to FX send bus B */ 433 434 // Note: the volumes are raw multpliers, so real 100% is impossible. 435 #define CVCF 0x02 /* Current volume and filter cutoff register */ 436 SUB_REG(CVCF, CURRENTVOL, 0xffff0000) /* Current linear volume of specified channel */ 437 SUB_REG(CVCF, CURRENTFILTER, 0x0000ffff) /* Current filter cutoff frequency of specified channel */ 438 439 #define VTFT 0x03 /* Volume target and filter cutoff target register */ 440 SUB_REG(VTFT, VOLUMETARGET, 0xffff0000) /* Volume target of specified channel */ 441 SUB_REG(VTFT, FILTERTARGET, 0x0000ffff) /* Filter cutoff target of specified channel */ 442 443 #define Z1 0x05 /* Filter delay memory 1 register */ 444 445 #define Z2 0x04 /* Filter delay memory 2 register */ 446 447 #define PSST 0x06 /* Send C amount and loop start address register */ 448 SUB_REG(PSST, FXSENDAMOUNT_C, 0xff000000) /* Linear level of channel output sent to FX send bus C */ 449 SUB_REG(PSST, LOOPSTARTADDR, 0x00ffffff) /* Loop start address of the specified channel */ 450 451 #define DSL 0x07 /* Send D amount and loop end address register */ 452 SUB_REG(DSL, FXSENDAMOUNT_D, 0xff000000) /* Linear level of channel output sent to FX send bus D */ 453 SUB_REG(DSL, LOOPENDADDR, 0x00ffffff) /* Loop end address of the specified channel */ 454 455 #define CCCA 0x08 /* Filter Q, interp. ROM, byte size, cur. addr register */ 456 SUB_REG(CCCA, RESONANCE, 0xf0000000) /* Lowpass filter resonance (Q) height */ 457 #define CCCA_INTERPROM_MASK 0x0e000000 /* Selects passband of interpolation ROM */ 458 /* 1 == full band, 7 == lowpass */ 459 /* ROM 0 is used when pitch shifting downward or less */ 460 /* then 3 semitones upward. Increasingly higher ROM */ 461 /* numbers are used, typically in steps of 3 semitones, */ 462 /* as upward pitch shifting is performed. */ 463 #define CCCA_INTERPROM_0 0x00000000 /* Select interpolation ROM 0 */ 464 #define CCCA_INTERPROM_1 0x02000000 /* Select interpolation ROM 1 */ 465 #define CCCA_INTERPROM_2 0x04000000 /* Select interpolation ROM 2 */ 466 #define CCCA_INTERPROM_3 0x06000000 /* Select interpolation ROM 3 */ 467 #define CCCA_INTERPROM_4 0x08000000 /* Select interpolation ROM 4 */ 468 #define CCCA_INTERPROM_5 0x0a000000 /* Select interpolation ROM 5 */ 469 #define CCCA_INTERPROM_6 0x0c000000 /* Select interpolation ROM 6 */ 470 #define CCCA_INTERPROM_7 0x0e000000 /* Select interpolation ROM 7 */ 471 #define CCCA_8BITSELECT 0x01000000 /* 1 = Sound memory for this channel uses 8-bit samples */ 472 /* 8-bit samples are unsigned, 16-bit ones signed */ 473 SUB_REG(CCCA, CURRADDR, 0x00ffffff) /* Current address of the selected channel */ 474 475 #define CCR 0x09 /* Cache control register */ 476 SUB_REG(CCR, CACHEINVALIDSIZE, 0xfe000000) /* Number of invalid samples before the read address */ 477 #define CCR_CACHELOOPFLAG 0x01000000 /* 1 = Cache has a loop service pending */ 478 #define CCR_INTERLEAVEDSAMPLES 0x00800000 /* 1 = A cache service will fetch interleaved samples */ 479 /* Auto-set from CPF_STEREO_MASK */ 480 #define CCR_WORDSIZEDSAMPLES 0x00400000 /* 1 = A cache service will fetch word sized samples */ 481 /* Auto-set from CCCA_8BITSELECT */ 482 SUB_REG(CCR, READADDRESS, 0x003f0000) /* Next cached sample to play */ 483 SUB_REG(CCR, LOOPINVALSIZE, 0x0000fe00) /* Number of invalid samples in cache prior to loop */ 484 /* NOTE: This is valid only if CACHELOOPFLAG is set */ 485 #define CCR_LOOPFLAG 0x00000100 /* Set for a single sample period when a loop occurs */ 486 SUB_REG(CCR, CACHELOOPADDRHI, 0x000000ff) /* CLP_LOOPSTARTADDR's hi byte if CACHELOOPFLAG is set */ 487 488 #define CLP 0x0a /* Cache loop register (valid if CCR_CACHELOOPFLAG = 1) */ 489 /* NOTE: This register is normally not used */ 490 SUB_REG(CLP, CACHELOOPADDR, 0x0000ffff) /* Cache loop address low word */ 491 492 #define FXRT 0x0b /* Effects send routing register */ 493 /* NOTE: It is illegal to assign the same routing to */ 494 /* two effects sends. */ 495 #define FXRT_CHANNELA 0x000f0000 /* Effects send bus number for channel's effects send A */ 496 #define FXRT_CHANNELB 0x00f00000 /* Effects send bus number for channel's effects send B */ 497 #define FXRT_CHANNELC 0x0f000000 /* Effects send bus number for channel's effects send C */ 498 #define FXRT_CHANNELD 0xf0000000 /* Effects send bus number for channel's effects send D */ 499 500 #define MAPA 0x0c /* Cache map A */ 501 #define MAPB 0x0d /* Cache map B */ 502 503 #define MAP_PTE_MASK0 0xfffff000 /* The 20 MSBs of the PTE indexed by the PTI */ 504 #define MAP_PTI_MASK0 0x00000fff /* The 12 bit index to one of the 4096 PTE dwords */ 505 506 #define MAP_PTE_MASK1 0xffffe000 /* The 19 MSBs of the PTE indexed by the PTI */ 507 #define MAP_PTI_MASK1 0x00001fff /* The 13 bit index to one of the 8192 PTE dwords */ 508 509 /* 0x0e, 0x0f: Internal state, at least on Audigy */ 510 511 #define ENVVOL 0x10 /* Volume envelope register */ 512 #define ENVVOL_MASK 0x0000ffff /* Current value of volume envelope state variable */ 513 /* 0x8000-n == 666*n usec delay */ 514 515 #define ATKHLDV 0x11 /* Volume envelope hold and attack register */ 516 #define ATKHLDV_PHASE0_MASK 0x00008000 /* 0 = Begin attack phase */ 517 #define ATKHLDV_HOLDTIME_MASK 0x00007f00 /* Envelope hold time (127-n == n*88.2msec) */ 518 #define ATKHLDV_ATTACKTIME_MASK 0x0000007f /* Envelope attack time, log encoded */ 519 /* 0 = infinite, 1 = 10.9msec, ... 0x7f = 5.5msec */ 520 521 #define DCYSUSV 0x12 /* Volume envelope sustain and decay register */ 522 #define DCYSUSV_PHASE1_MASK 0x00008000 /* 0 = Begin decay phase, 1 = begin release phase */ 523 #define DCYSUSV_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */ 524 #define DCYSUSV_CHANNELENABLE_MASK 0x00000080 /* 0 = Inhibit envelope engine from writing values in */ 525 /* this channel and from writing to pitch, filter and */ 526 /* volume targets. */ 527 #define DCYSUSV_DECAYTIME_MASK 0x0000007f /* Volume envelope decay time, log encoded */ 528 /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */ 529 530 #define LFOVAL1 0x13 /* Modulation LFO value */ 531 #define LFOVAL_MASK 0x0000ffff /* Current value of modulation LFO state variable */ 532 /* 0x8000-n == 666*n usec delay */ 533 534 #define ENVVAL 0x14 /* Modulation envelope register */ 535 #define ENVVAL_MASK 0x0000ffff /* Current value of modulation envelope state variable */ 536 /* 0x8000-n == 666*n usec delay */ 537 538 #define ATKHLDM 0x15 /* Modulation envelope hold and attack register */ 539 #define ATKHLDM_PHASE0_MASK 0x00008000 /* 0 = Begin attack phase */ 540 #define ATKHLDM_HOLDTIME 0x00007f00 /* Envelope hold time (127-n == n*42msec) */ 541 #define ATKHLDM_ATTACKTIME 0x0000007f /* Envelope attack time, log encoded */ 542 /* 0 = infinite, 1 = 11msec, ... 0x7f = 5.5msec */ 543 544 #define DCYSUSM 0x16 /* Modulation envelope decay and sustain register */ 545 #define DCYSUSM_PHASE1_MASK 0x00008000 /* 0 = Begin decay phase, 1 = begin release phase */ 546 #define DCYSUSM_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */ 547 #define DCYSUSM_DECAYTIME_MASK 0x0000007f /* Envelope decay time, log encoded */ 548 /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */ 549 550 #define LFOVAL2 0x17 /* Vibrato LFO register */ 551 #define LFOVAL2_MASK 0x0000ffff /* Current value of vibrato LFO state variable */ 552 /* 0x8000-n == 666*n usec delay */ 553 554 #define IP 0x18 /* Initial pitch register */ 555 #define IP_MASK 0x0000ffff /* Exponential initial pitch shift */ 556 /* 4 bits of octave, 12 bits of fractional octave */ 557 #define IP_UNITY 0x0000e000 /* Unity pitch shift */ 558 559 #define IFATN 0x19 /* Initial filter cutoff and attenuation register */ 560 SUB_REG(IFATN, FILTERCUTOFF, 0x0000ff00) /* Initial filter cutoff frequency in exponential units */ 561 /* 6 most significant bits are semitones */ 562 /* 2 least significant bits are fractions */ 563 SUB_REG(IFATN, ATTENUATION, 0x000000ff) /* Initial attenuation in 0.375dB steps */ 564 565 #define PEFE 0x1a /* Pitch envelope and filter envelope amount register */ 566 SUB_REG(PEFE, PITCHAMOUNT, 0x0000ff00) /* Pitch envlope amount */ 567 /* Signed 2's complement, +/- one octave peak extremes */ 568 SUB_REG(PEFE, FILTERAMOUNT, 0x000000ff) /* Filter envlope amount */ 569 /* Signed 2's complement, +/- six octaves peak extremes */ 570 571 572 #define FMMOD 0x1b /* Vibrato/filter modulation from LFO register */ 573 #define FMMOD_MODVIBRATO 0x0000ff00 /* Vibrato LFO modulation depth */ 574 /* Signed 2's complement, +/- one octave extremes */ 575 #define FMMOD_MOFILTER 0x000000ff /* Filter LFO modulation depth */ 576 /* Signed 2's complement, +/- three octave extremes */ 577 578 #define TREMFRQ 0x1c /* Tremolo amount and modulation LFO frequency register */ 579 #define TREMFRQ_DEPTH 0x0000ff00 /* Tremolo depth */ 580 /* Signed 2's complement, with +/- 12dB extremes */ 581 #define TREMFRQ_FREQUENCY 0x000000ff /* Tremolo LFO frequency */ 582 /* ??Hz steps, maximum of ?? Hz. */ 583 584 #define FM2FRQ2 0x1d /* Vibrato amount and vibrato LFO frequency register */ 585 #define FM2FRQ2_DEPTH 0x0000ff00 /* Vibrato LFO vibrato depth */ 586 /* Signed 2's complement, +/- one octave extremes */ 587 #define FM2FRQ2_FREQUENCY 0x000000ff /* Vibrato LFO frequency */ 588 /* 0.039Hz steps, maximum of 9.85 Hz. */ 589 590 #define TEMPENV 0x1e /* Tempory envelope register */ 591 #define TEMPENV_MASK 0x0000ffff /* 16-bit value */ 592 /* NOTE: All channels contain internal variables; do */ 593 /* not write to these locations. */ 594 595 /* 0x1f: not used */ 596 597 // 32 cache registers (== 128 bytes) per channel follow. 598 // In stereo mode, the two channels' caches are concatenated into one, 599 // and hold the interleaved frames. 600 // The cache holds 64 frames, so the upper half is not used in 8-bit mode. 601 // All registers mentioned below count in frames. 602 // The cache is a ring buffer; CCR_READADDRESS operates modulo 64. 603 // The cache is filled from (CCCA_CURRADDR - CCR_CACHEINVALIDSIZE) 604 // into (CCR_READADDRESS - CCR_CACHEINVALIDSIZE). 605 // The engine has a fetch threshold of 32 bytes, so it tries to keep 606 // CCR_CACHEINVALIDSIZE below 8 (16-bit stereo), 16 (16-bit mono, 607 // 8-bit stereo), or 32 (8-bit mono). The actual transfers are pretty 608 // unpredictable, especially if several voices are running. 609 // Frames are consumed at CCR_READADDRESS, which is incremented afterwards, 610 // along with CCCA_CURRADDR and CCR_CACHEINVALIDSIZE. This implies that the 611 // actual playback position always lags CCCA_CURRADDR by exactly 64 frames. 612 #define CD0 0x20 /* Cache data registers 0 .. 0x1f */ 613 614 #define PTB 0x40 /* Page table base register */ 615 #define PTB_MASK 0xfffff000 /* Physical address of the page table in host memory */ 616 617 #define TCB 0x41 /* Tank cache base register */ 618 #define TCB_MASK 0xfffff000 /* Physical address of the bottom of host based TRAM */ 619 620 #define ADCCR 0x42 /* ADC sample rate/stereo control register */ 621 #define ADCCR_RCHANENABLE 0x00000010 /* Enables right channel for writing to the host */ 622 #define ADCCR_LCHANENABLE 0x00000008 /* Enables left channel for writing to the host */ 623 /* NOTE: To guarantee phase coherency, both channels */ 624 /* must be disabled prior to enabling both channels. */ 625 #define A_ADCCR_RCHANENABLE 0x00000020 626 #define A_ADCCR_LCHANENABLE 0x00000010 627 628 #define A_ADCCR_SAMPLERATE_MASK 0x0000000F /* Audigy sample rate convertor output rate */ 629 #define ADCCR_SAMPLERATE_MASK 0x00000007 /* Sample rate convertor output rate */ 630 #define ADCCR_SAMPLERATE_48 0x00000000 /* 48kHz sample rate */ 631 #define ADCCR_SAMPLERATE_44 0x00000001 /* 44.1kHz sample rate */ 632 #define ADCCR_SAMPLERATE_32 0x00000002 /* 32kHz sample rate */ 633 #define ADCCR_SAMPLERATE_24 0x00000003 /* 24kHz sample rate */ 634 #define ADCCR_SAMPLERATE_22 0x00000004 /* 22.05kHz sample rate */ 635 #define ADCCR_SAMPLERATE_16 0x00000005 /* 16kHz sample rate */ 636 #define ADCCR_SAMPLERATE_11 0x00000006 /* 11.025kHz sample rate */ 637 #define ADCCR_SAMPLERATE_8 0x00000007 /* 8kHz sample rate */ 638 #define A_ADCCR_SAMPLERATE_12 0x00000006 /* 12kHz sample rate */ 639 #define A_ADCCR_SAMPLERATE_11 0x00000007 /* 11.025kHz sample rate */ 640 #define A_ADCCR_SAMPLERATE_8 0x00000008 /* 8kHz sample rate */ 641 642 #define FXWC 0x43 /* FX output write channels register */ 643 /* When set, each bit enables the writing of the */ 644 /* corresponding FX output channel (internal registers */ 645 /* 0x20-0x3f) to host memory. This mode of recording */ 646 /* is 16bit, 48KHz only. All 32 channels can be enabled */ 647 /* simultaneously. */ 648 649 #define A_TBLSZ 0x43 /* Effects Tank Internal Table Size. Only low byte or register used */ 650 651 #define TCBS 0x44 /* Tank cache buffer size register */ 652 #define TCBS_MASK 0x00000007 /* Tank cache buffer size field */ 653 #define TCBS_BUFFSIZE_16K 0x00000000 654 #define TCBS_BUFFSIZE_32K 0x00000001 655 #define TCBS_BUFFSIZE_64K 0x00000002 656 #define TCBS_BUFFSIZE_128K 0x00000003 657 #define TCBS_BUFFSIZE_256K 0x00000004 658 #define TCBS_BUFFSIZE_512K 0x00000005 659 #define TCBS_BUFFSIZE_1024K 0x00000006 660 #define TCBS_BUFFSIZE_2048K 0x00000007 661 662 #define MICBA 0x45 /* AC97 microphone buffer address register */ 663 #define MICBA_MASK 0xfffff000 /* 20 bit base address */ 664 665 #define ADCBA 0x46 /* ADC buffer address register */ 666 #define ADCBA_MASK 0xfffff000 /* 20 bit base address */ 667 668 #define FXBA 0x47 /* FX Buffer Address */ 669 #define FXBA_MASK 0xfffff000 /* 20 bit base address */ 670 671 #define A_HWM 0x48 /* High PCI Water Mark - word access, defaults to 3f */ 672 673 #define MICBS 0x49 /* Microphone buffer size register */ 674 675 #define ADCBS 0x4a /* ADC buffer size register */ 676 677 #define FXBS 0x4b /* FX buffer size register */ 678 679 /* The following mask values define the size of the ADC, MIC and FX buffers in bytes */ 680 #define ADCBS_BUFSIZE_NONE 0x00000000 681 #define ADCBS_BUFSIZE_384 0x00000001 682 #define ADCBS_BUFSIZE_448 0x00000002 683 #define ADCBS_BUFSIZE_512 0x00000003 684 #define ADCBS_BUFSIZE_640 0x00000004 685 #define ADCBS_BUFSIZE_768 0x00000005 686 #define ADCBS_BUFSIZE_896 0x00000006 687 #define ADCBS_BUFSIZE_1024 0x00000007 688 #define ADCBS_BUFSIZE_1280 0x00000008 689 #define ADCBS_BUFSIZE_1536 0x00000009 690 #define ADCBS_BUFSIZE_1792 0x0000000a 691 #define ADCBS_BUFSIZE_2048 0x0000000b 692 #define ADCBS_BUFSIZE_2560 0x0000000c 693 #define ADCBS_BUFSIZE_3072 0x0000000d 694 #define ADCBS_BUFSIZE_3584 0x0000000e 695 #define ADCBS_BUFSIZE_4096 0x0000000f 696 #define ADCBS_BUFSIZE_5120 0x00000010 697 #define ADCBS_BUFSIZE_6144 0x00000011 698 #define ADCBS_BUFSIZE_7168 0x00000012 699 #define ADCBS_BUFSIZE_8192 0x00000013 700 #define ADCBS_BUFSIZE_10240 0x00000014 701 #define ADCBS_BUFSIZE_12288 0x00000015 702 #define ADCBS_BUFSIZE_14366 0x00000016 703 #define ADCBS_BUFSIZE_16384 0x00000017 704 #define ADCBS_BUFSIZE_20480 0x00000018 705 #define ADCBS_BUFSIZE_24576 0x00000019 706 #define ADCBS_BUFSIZE_28672 0x0000001a 707 #define ADCBS_BUFSIZE_32768 0x0000001b 708 #define ADCBS_BUFSIZE_40960 0x0000001c 709 #define ADCBS_BUFSIZE_49152 0x0000001d 710 #define ADCBS_BUFSIZE_57344 0x0000001e 711 #define ADCBS_BUFSIZE_65536 0x0000001f 712 713 // On Audigy, the FX send amounts are not applied instantly, but determine 714 // targets towards which the following registers swerve gradually. 715 #define A_CSBA 0x4c /* FX send B & A current amounts */ 716 #define A_CSDC 0x4d /* FX send D & C current amounts */ 717 #define A_CSFE 0x4e /* FX send F & E current amounts */ 718 #define A_CSHG 0x4f /* FX send H & G current amounts */ 719 720 // NOTE: 0x50,51,52: 64-bit (split over voices 0 & 1) 721 #define CDCS 0x50 /* CD-ROM digital channel status register */ 722 723 #define GPSCS 0x51 /* General Purpose SPDIF channel status register */ 724 725 // Corresponding EMU10K1_DBG_* constants are in the public header 726 #define DBG 0x52 727 728 #define A_SPSC 0x52 /* S/PDIF Input C Channel Status */ 729 730 #define REG53 0x53 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */ 731 732 // Corresponding A_DBG_* constants are in the public header 733 #define A_DBG 0x53 734 735 // NOTE: 0x54,55,56: 64-bit (split over voices 0 & 1) 736 #define SPCS0 0x54 /* SPDIF output Channel Status 0 register */ 737 738 #define SPCS1 0x55 /* SPDIF output Channel Status 1 register */ 739 740 #define SPCS2 0x56 /* SPDIF output Channel Status 2 register */ 741 742 #define SPCS_CLKACCYMASK 0x30000000 /* Clock accuracy */ 743 #define SPCS_CLKACCY_1000PPM 0x00000000 /* 1000 parts per million */ 744 #define SPCS_CLKACCY_50PPM 0x10000000 /* 50 parts per million */ 745 #define SPCS_CLKACCY_VARIABLE 0x20000000 /* Variable accuracy */ 746 #define SPCS_SAMPLERATEMASK 0x0f000000 /* Sample rate */ 747 #define SPCS_SAMPLERATE_44 0x00000000 /* 44.1kHz sample rate */ 748 #define SPCS_SAMPLERATE_48 0x02000000 /* 48kHz sample rate */ 749 #define SPCS_SAMPLERATE_32 0x03000000 /* 32kHz sample rate */ 750 #define SPCS_CHANNELNUMMASK 0x00f00000 /* Channel number */ 751 #define SPCS_CHANNELNUM_UNSPEC 0x00000000 /* Unspecified channel number */ 752 #define SPCS_CHANNELNUM_LEFT 0x00100000 /* Left channel */ 753 #define SPCS_CHANNELNUM_RIGHT 0x00200000 /* Right channel */ 754 #define SPCS_SOURCENUMMASK 0x000f0000 /* Source number */ 755 #define SPCS_SOURCENUM_UNSPEC 0x00000000 /* Unspecified source number */ 756 #define SPCS_GENERATIONSTATUS 0x00008000 /* Originality flag (see IEC-958 spec) */ 757 #define SPCS_CATEGORYCODEMASK 0x00007f00 /* Category code (see IEC-958 spec) */ 758 #define SPCS_MODEMASK 0x000000c0 /* Mode (see IEC-958 spec) */ 759 #define SPCS_EMPHASISMASK 0x00000038 /* Emphasis */ 760 #define SPCS_EMPHASIS_NONE 0x00000000 /* No emphasis */ 761 #define SPCS_EMPHASIS_50_15 0x00000008 /* 50/15 usec 2 channel */ 762 #define SPCS_COPYRIGHT 0x00000004 /* Copyright asserted flag -- do not modify */ 763 #define SPCS_NOTAUDIODATA 0x00000002 /* 0 = Digital audio, 1 = not audio */ 764 #define SPCS_PROFESSIONAL 0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */ 765 766 /* 0x57: Not used */ 767 768 /* The 32-bit CLIx and SOLEx registers all have one bit per channel control/status */ 769 #define CLIEL 0x58 /* Channel loop interrupt enable low register */ 770 #define CLIEH 0x59 /* Channel loop interrupt enable high register */ 771 772 #define CLIPL 0x5a /* Channel loop interrupt pending low register */ 773 #define CLIPH 0x5b /* Channel loop interrupt pending high register */ 774 775 // These cause CPF_STOP_MASK to be set shortly after CCCA_CURRADDR passes DSL_LOOPENDADDR. 776 // Subsequent changes to the address registers don't resume; clearing the bit here or in CPF does. 777 // The registers are NOT synchronized; the next serviced channel picks up immediately. 778 #define SOLEL 0x5c /* Stop on loop enable low register */ 779 #define SOLEH 0x5d /* Stop on loop enable high register */ 780 781 #define SPBYPASS 0x5e /* SPDIF BYPASS mode register */ 782 #define SPBYPASS_SPDIF0_MASK 0x00000003 /* SPDIF 0 bypass mode */ 783 #define SPBYPASS_SPDIF1_MASK 0x0000000c /* SPDIF 1 bypass mode */ 784 /* bypass mode: 0 - DSP; 1 - SPDIF A, 2 - SPDIF B, 3 - SPDIF C */ 785 #define SPBYPASS_FORMAT 0x00000f00 /* If 1, SPDIF XX uses 24 bit, if 0 - 20 bit */ 786 787 #define AC97SLOT 0x5f /* additional AC97 slots enable bits */ 788 #define AC97SLOT_REAR_RIGHT 0x01 /* Rear left */ 789 #define AC97SLOT_REAR_LEFT 0x02 /* Rear right */ 790 #define AC97SLOT_CNTR 0x10 /* Center enable */ 791 #define AC97SLOT_LFE 0x20 /* LFE enable */ 792 793 #define A_PCB 0x5f /* PCB Revision */ 794 795 // NOTE: 0x60,61,62: 64-bit 796 #define CDSRCS 0x60 /* CD-ROM Sample Rate Converter status register */ 797 798 #define GPSRCS 0x61 /* General Purpose SPDIF sample rate cvt status */ 799 800 #define ZVSRCS 0x62 /* ZVideo sample rate converter status */ 801 /* NOTE: This one has no SPDIFLOCKED field */ 802 /* Assumes sample lock */ 803 804 /* These three bitfields apply to CDSRCS, GPSRCS, and (except as noted) ZVSRCS. */ 805 #define SRCS_SPDIFVALID 0x04000000 /* SPDIF stream valid */ 806 #define SRCS_SPDIFLOCKED 0x02000000 /* SPDIF stream locked */ 807 #define SRCS_RATELOCKED 0x01000000 /* Sample rate locked */ 808 #define SRCS_ESTSAMPLERATE 0x0007ffff /* Do not modify this field. */ 809 810 /* Note that these values can vary +/- by a small amount */ 811 #define SRCS_SPDIFRATE_44 0x0003acd9 812 #define SRCS_SPDIFRATE_48 0x00040000 813 #define SRCS_SPDIFRATE_96 0x00080000 814 815 #define MICIDX 0x63 /* Microphone recording buffer index register */ 816 SUB_REG(MICIDX, IDX, 0x0000ffff) 817 818 #define ADCIDX 0x64 /* ADC recording buffer index register */ 819 SUB_REG(ADCIDX, IDX, 0x0000ffff) 820 821 #define A_ADCIDX 0x63 822 SUB_REG(A_ADCIDX, IDX, 0x0000ffff) 823 824 #define A_MICIDX 0x64 825 SUB_REG(A_MICIDX, IDX, 0x0000ffff) 826 827 #define FXIDX 0x65 /* FX recording buffer index register */ 828 SUB_REG(FXIDX, IDX, 0x0000ffff) 829 830 /* The 32-bit HLIEx and HLIPx registers all have one bit per channel control/status */ 831 #define HLIEL 0x66 /* Channel half loop interrupt enable low register */ 832 #define HLIEH 0x67 /* Channel half loop interrupt enable high register */ 833 834 #define HLIPL 0x68 /* Channel half loop interrupt pending low register */ 835 #define HLIPH 0x69 /* Channel half loop interrupt pending high register */ 836 837 #define A_SPRI 0x6a /* S/PDIF Host Record Index (bypasses SRC) */ 838 #define A_SPRA 0x6b /* S/PDIF Host Record Address */ 839 #define A_SPRC 0x6c /* S/PDIF Host Record Control */ 840 841 #define A_DICE 0x6d /* Delayed Interrupt Counter & Enable */ 842 843 #define A_TTB 0x6e /* Tank Table Base */ 844 #define A_TDOF 0x6f /* Tank Delay Offset */ 845 846 /* This is the MPU port on the card (via the game port) */ 847 #define A_MUDATA1 0x70 848 #define A_MUCMD1 0x71 849 #define A_MUSTAT1 A_MUCMD1 850 851 /* This is the MPU port on the Audigy Drive */ 852 #define A_MUDATA2 0x72 853 #define A_MUCMD2 0x73 854 #define A_MUSTAT2 A_MUCMD2 855 856 /* The next two are the Audigy equivalent of FXWC */ 857 /* the Audigy can record any output (16bit, 48kHz, up to 64 channels simultaneously) */ 858 /* Each bit selects a channel for recording */ 859 #define A_FXWC1 0x74 /* Selects 0x7f-0x60 for FX recording */ 860 #define A_FXWC2 0x75 /* Selects 0x9f-0x80 for FX recording */ 861 862 #define A_EHC 0x76 /* Extended Hardware Control */ 863 864 #define A_SPDIF_SAMPLERATE A_EHC /* Set the sample rate of SPDIF output */ 865 #define A_SPDIF_RATE_MASK 0x000000e0 /* Any other values for rates, just use 48000 */ 866 #define A_SPDIF_48000 0x00000000 /* kX calls this BYPASS */ 867 #define A_SPDIF_192000 0x00000020 868 #define A_SPDIF_96000 0x00000040 869 #define A_SPDIF_44100 0x00000080 870 #define A_SPDIF_MUTED 0x000000c0 871 872 SUB_REG_NC(A_EHC, A_I2S_CAPTURE_RATE, 0x00000e00) /* This sets the capture PCM rate, but it is */ 873 /* unclear if this sets the ADC rate as well. */ 874 #define A_I2S_CAPTURE_48000 0x0 875 #define A_I2S_CAPTURE_192000 0x1 876 #define A_I2S_CAPTURE_96000 0x2 877 #define A_I2S_CAPTURE_44100 0x4 878 879 #define A_EHC_SRC48_MASK 0x0000e000 /* This sets the playback PCM rate on the P16V */ 880 #define A_EHC_SRC48_BYPASS 0x00000000 881 #define A_EHC_SRC48_192 0x00002000 882 #define A_EHC_SRC48_96 0x00004000 883 #define A_EHC_SRC48_44 0x00008000 884 #define A_EHC_SRC48_MUTED 0x0000c000 885 886 #define A_EHC_P17V_TVM 0x00000001 /* Tank virtual memory mode */ 887 #define A_EHC_P17V_SEL0_MASK 0x00030000 /* Aka A_EHC_P16V_PB_RATE; 00: 48, 01: 44.1, 10: 96, 11: 192 */ 888 #define A_EHC_P17V_SEL1_MASK 0x000c0000 889 #define A_EHC_P17V_SEL2_MASK 0x00300000 890 #define A_EHC_P17V_SEL3_MASK 0x00c00000 891 892 #define A_EHC_ASYNC_BYPASS 0x80000000 893 894 #define A_SRT3 0x77 /* I2S0 Sample Rate Tracker Status */ 895 #define A_SRT4 0x78 /* I2S1 Sample Rate Tracker Status */ 896 #define A_SRT5 0x79 /* I2S2 Sample Rate Tracker Status */ 897 /* - default to 0x01080000 on my audigy 2 ZS --rlrevell */ 898 899 #define A_SRT_ESTSAMPLERATE 0x001fffff 900 #define A_SRT_RATELOCKED 0x01000000 901 902 #define A_TTDA 0x7a /* Tank Table DMA Address */ 903 #define A_TTDD 0x7b /* Tank Table DMA Data */ 904 905 #define A_FXRT2 0x7c 906 #define A_FXRT_CHANNELE 0x0000003f /* Effects send bus number for channel's effects send E */ 907 #define A_FXRT_CHANNELF 0x00003f00 /* Effects send bus number for channel's effects send F */ 908 #define A_FXRT_CHANNELG 0x003f0000 /* Effects send bus number for channel's effects send G */ 909 #define A_FXRT_CHANNELH 0x3f000000 /* Effects send bus number for channel's effects send H */ 910 911 #define A_SENDAMOUNTS 0x7d 912 #define A_FXSENDAMOUNT_E_MASK 0xFF000000 913 #define A_FXSENDAMOUNT_F_MASK 0x00FF0000 914 #define A_FXSENDAMOUNT_G_MASK 0x0000FF00 915 #define A_FXSENDAMOUNT_H_MASK 0x000000FF 916 917 /* 0x7c, 0x7e "high bit is used for filtering" */ 918 919 /* The send amounts for this one are the same as used with the emu10k1 */ 920 #define A_FXRT1 0x7e 921 #define A_FXRT_CHANNELA 0x0000003f 922 #define A_FXRT_CHANNELB 0x00003f00 923 #define A_FXRT_CHANNELC 0x003f0000 924 #define A_FXRT_CHANNELD 0x3f000000 925 926 /* 0x7f: Not used */ 927 928 /* The public header defines the GPR and TRAM base addresses that 929 * are valid for _both_ CPU and DSP addressing. */ 930 931 /* Each DSP microcode instruction is mapped into 2 doublewords */ 932 /* NOTE: When writing, always write the LO doubleword first. Reads can be in either order. */ 933 #define MICROCODEBASE 0x400 /* Microcode data base address */ 934 #define A_MICROCODEBASE 0x600 935 936 937 /************************************************************************************************/ 938 /* E-MU Digital Audio System overview */ 939 /************************************************************************************************/ 940 941 // - These cards use a regular PCI-attached Audigy chip (Alice2/Tina/Tina2); 942 // the PCIe variants simply put the Audigy chip behind a PCI bridge. 943 // - All physical PCM I/O is routed through an additional FPGA; the regular 944 // EXTIN/EXTOUT ports are unconnected. 945 // - The FPGA has a signal routing matrix, to connect each destination (output 946 // socket or capture channel) to a source (input socket or playback channel). 947 // - The FPGA is controlled via Audigy's GPIO port, while sample data is 948 // transmitted via proprietary EMU32 serial links. On first-generation 949 // E-MU 1010 cards, Audigy's I2S inputs are also used for sample data. 950 // - The Audio/Micro Dock is attached to Hana via EDI, a "network" link. 951 // - The Audigy chip operates in slave mode; the clock is supplied by the FPGA. 952 // Gen1 E-MU 1010 cards have two crystals (for 44.1 kHz and 48 kHz multiples), 953 // while the later cards use a single crystal and a PLL chip. 954 // - The whole card is switched to 2x/4x mode to achieve 88.2/96/176.4/192 kHz 955 // sample rates. Alice2/Tina keeps running at 44.1/48 kHz, but multiple channels 956 // are bundled. 957 // - The number of available EMU32/EDI channels is hit in 2x/4x mode, so the total 958 // number of usable inputs/outputs is limited, esp. with ADAT in use. 959 // - S/PDIF is unavailable in 4x mode (only over TOSLINK on newer 1010 cards) due 960 // to being unspecified at 176.4/192 kHz. Therefore, the Dock's S/PDIF channels 961 // can overlap with the Dock's ADC/DAC's high channels. 962 // - The code names are mentioned below and in the emu_chip_details table. 963 964 /************************************************************************************************/ 965 /* EMU1010 FPGA registers */ 966 /************************************************************************************************/ 967 968 #define EMU_HANA_DESTHI 0x00 /* 0000xxx 3 bits Link Destination */ 969 #define EMU_HANA_DESTLO 0x01 /* 00xxxxx 5 bits */ 970 971 #define EMU_HANA_SRCHI 0x02 /* 0000xxx 3 bits Link Source */ 972 #define EMU_HANA_SRCLO 0x03 /* 00xxxxx 5 bits */ 973 974 #define EMU_HANA_DOCK_PWR 0x04 /* 000000x 1 bits Audio Dock power */ 975 #define EMU_HANA_DOCK_PWR_ON 0x01 /* Audio Dock power on */ 976 977 #define EMU_HANA_WCLOCK 0x05 /* 0000xxx 3 bits Word Clock source select */ 978 /* Must be written after power on to reset DLL */ 979 /* One is unable to detect the Audio dock without this */ 980 #define EMU_HANA_WCLOCK_SRC_MASK 0x07 981 #define EMU_HANA_WCLOCK_INT_48K 0x00 982 #define EMU_HANA_WCLOCK_INT_44_1K 0x01 983 #define EMU_HANA_WCLOCK_HANA_SPDIF_IN 0x02 984 #define EMU_HANA_WCLOCK_HANA_ADAT_IN 0x03 985 #define EMU_HANA_WCLOCK_SYNC_BNC 0x04 986 #define EMU_HANA_WCLOCK_2ND_HANA 0x05 987 #define EMU_HANA_WCLOCK_SRC_RESERVED 0x06 988 #define EMU_HANA_WCLOCK_OFF 0x07 /* For testing, forces fallback to DEFCLOCK */ 989 #define EMU_HANA_WCLOCK_MULT_MASK 0x18 990 #define EMU_HANA_WCLOCK_1X 0x00 991 #define EMU_HANA_WCLOCK_2X 0x08 992 #define EMU_HANA_WCLOCK_4X 0x10 993 #define EMU_HANA_WCLOCK_MULT_RESERVED 0x18 994 995 #define EMU_HANA_DEFCLOCK 0x06 /* 000000x 1 bits Default Word Clock */ 996 #define EMU_HANA_DEFCLOCK_48K 0x00 997 #define EMU_HANA_DEFCLOCK_44_1K 0x01 998 999 #define EMU_HANA_UNMUTE 0x07 /* 000000x 1 bits Mute all audio outputs */ 1000 #define EMU_MUTE 0x00 1001 #define EMU_UNMUTE 0x01 1002 1003 #define EMU_HANA_FPGA_CONFIG 0x08 /* 00000xx 2 bits Config control of FPGAs */ 1004 #define EMU_HANA_FPGA_CONFIG_AUDIODOCK 0x01 /* Set in order to program FPGA on Audio Dock */ 1005 #define EMU_HANA_FPGA_CONFIG_HANA 0x02 /* Set in order to program FPGA on Hana */ 1006 1007 #define EMU_HANA_IRQ_ENABLE 0x09 /* 000xxxx 4 bits IRQ Enable */ 1008 #define EMU_HANA_IRQ_WCLK_CHANGED 0x01 1009 #define EMU_HANA_IRQ_ADAT 0x02 1010 #define EMU_HANA_IRQ_DOCK 0x04 1011 #define EMU_HANA_IRQ_DOCK_LOST 0x08 1012 1013 #define EMU_HANA_SPDIF_MODE 0x0a /* 00xxxxx 5 bits SPDIF MODE */ 1014 #define EMU_HANA_SPDIF_MODE_TX_CONSUMER 0x00 1015 #define EMU_HANA_SPDIF_MODE_TX_PRO 0x01 1016 #define EMU_HANA_SPDIF_MODE_TX_NOCOPY 0x02 1017 #define EMU_HANA_SPDIF_MODE_RX_CONSUMER 0x00 1018 #define EMU_HANA_SPDIF_MODE_RX_PRO 0x04 1019 #define EMU_HANA_SPDIF_MODE_RX_NOCOPY 0x08 1020 #define EMU_HANA_SPDIF_MODE_RX_INVALID 0x10 1021 1022 #define EMU_HANA_OPTICAL_TYPE 0x0b /* 00000xx 2 bits ADAT or SPDIF in/out */ 1023 #define EMU_HANA_OPTICAL_IN_SPDIF 0x00 1024 #define EMU_HANA_OPTICAL_IN_ADAT 0x01 1025 #define EMU_HANA_OPTICAL_OUT_SPDIF 0x00 1026 #define EMU_HANA_OPTICAL_OUT_ADAT 0x02 1027 1028 #define EMU_HANA_MIDI_IN 0x0c /* 000000x 1 bit Control MIDI */ 1029 #define EMU_HANA_MIDI_INA_FROM_HAMOA 0x01 /* HAMOA MIDI in to Alice 2 MIDI A */ 1030 #define EMU_HANA_MIDI_INA_FROM_DOCK1 0x02 /* Audio Dock-1 MIDI in to Alice 2 MIDI A */ 1031 #define EMU_HANA_MIDI_INA_FROM_DOCK2 0x03 /* Audio Dock-2 MIDI in to Alice 2 MIDI A */ 1032 #define EMU_HANA_MIDI_INB_FROM_HAMOA 0x08 /* HAMOA MIDI in to Alice 2 MIDI B */ 1033 #define EMU_HANA_MIDI_INB_FROM_DOCK1 0x10 /* Audio Dock-1 MIDI in to Alice 2 MIDI B */ 1034 #define EMU_HANA_MIDI_INB_FROM_DOCK2 0x18 /* Audio Dock-2 MIDI in to Alice 2 MIDI B */ 1035 1036 #define EMU_HANA_DOCK_LEDS_1 0x0d /* 000xxxx 4 bit Audio Dock LEDs */ 1037 #define EMU_HANA_DOCK_LEDS_1_MIDI1 0x01 /* MIDI 1 LED on */ 1038 #define EMU_HANA_DOCK_LEDS_1_MIDI2 0x02 /* MIDI 2 LED on */ 1039 #define EMU_HANA_DOCK_LEDS_1_SMPTE_IN 0x04 /* SMPTE IN LED on */ 1040 #define EMU_HANA_DOCK_LEDS_1_SMPTE_OUT 0x08 /* SMPTE OUT LED on */ 1041 1042 #define EMU_HANA_DOCK_LEDS_2 0x0e /* 0xxxxxx 6 bit Audio Dock LEDs */ 1043 #define EMU_HANA_DOCK_LEDS_2_44K 0x01 /* 44.1 kHz LED on */ 1044 #define EMU_HANA_DOCK_LEDS_2_48K 0x02 /* 48 kHz LED on */ 1045 #define EMU_HANA_DOCK_LEDS_2_96K 0x04 /* 96 kHz LED on */ 1046 #define EMU_HANA_DOCK_LEDS_2_192K 0x08 /* 192 kHz LED on */ 1047 #define EMU_HANA_DOCK_LEDS_2_LOCK 0x10 /* LOCK LED on */ 1048 #define EMU_HANA_DOCK_LEDS_2_EXT 0x20 /* EXT LED on */ 1049 1050 #define EMU_HANA_DOCK_LEDS_3 0x0f /* 0xxxxxx 6 bit Audio Dock LEDs */ 1051 #define EMU_HANA_DOCK_LEDS_3_CLIP_A 0x01 /* Mic A Clip LED on */ 1052 #define EMU_HANA_DOCK_LEDS_3_CLIP_B 0x02 /* Mic B Clip LED on */ 1053 #define EMU_HANA_DOCK_LEDS_3_SIGNAL_A 0x04 /* Signal A Clip LED on */ 1054 #define EMU_HANA_DOCK_LEDS_3_SIGNAL_B 0x08 /* Signal B Clip LED on */ 1055 #define EMU_HANA_DOCK_LEDS_3_MANUAL_CLIP 0x10 /* Manual Clip detection */ 1056 #define EMU_HANA_DOCK_LEDS_3_MANUAL_SIGNAL 0x20 /* Manual Signal detection */ 1057 1058 #define EMU_HANA_ADC_PADS 0x10 /* 0000xxx 3 bit Audio Dock ADC 14dB pads */ 1059 #define EMU_HANA_DOCK_ADC_PAD1 0x01 /* 14dB Attenuation on Audio Dock ADC 1 */ 1060 #define EMU_HANA_DOCK_ADC_PAD2 0x02 /* 14dB Attenuation on Audio Dock ADC 2 */ 1061 #define EMU_HANA_DOCK_ADC_PAD3 0x04 /* 14dB Attenuation on Audio Dock ADC 3 */ 1062 #define EMU_HANA_0202_ADC_PAD1 0x08 /* 14dB Attenuation on 0202 ADC 1 */ 1063 1064 #define EMU_HANA_DOCK_MISC 0x11 /* 0xxxxxx 6 bit Audio Dock misc bits */ 1065 #define EMU_HANA_DOCK_DAC1_MUTE 0x01 /* DAC 1 Mute */ 1066 #define EMU_HANA_DOCK_DAC2_MUTE 0x02 /* DAC 2 Mute */ 1067 #define EMU_HANA_DOCK_DAC3_MUTE 0x04 /* DAC 3 Mute */ 1068 #define EMU_HANA_DOCK_DAC4_MUTE 0x08 /* DAC 4 Mute */ 1069 #define EMU_HANA_DOCK_PHONES_192_DAC1 0x00 /* DAC 1 Headphones source at 192kHz */ 1070 #define EMU_HANA_DOCK_PHONES_192_DAC2 0x10 /* DAC 2 Headphones source at 192kHz */ 1071 #define EMU_HANA_DOCK_PHONES_192_DAC3 0x20 /* DAC 3 Headphones source at 192kHz */ 1072 #define EMU_HANA_DOCK_PHONES_192_DAC4 0x30 /* DAC 4 Headphones source at 192kHz */ 1073 1074 #define EMU_HANA_MIDI_OUT 0x12 /* 00xxxxx 5 bit Source for each MIDI out port */ 1075 #define EMU_HANA_MIDI_OUT_0202 0x01 /* 0202 MIDI from Alice 2. 0 = A, 1 = B */ 1076 #define EMU_HANA_MIDI_OUT_DOCK1 0x02 /* Audio Dock MIDI1 front, from Alice 2. 0 = A, 1 = B */ 1077 #define EMU_HANA_MIDI_OUT_DOCK2 0x04 /* Audio Dock MIDI2 rear, from Alice 2. 0 = A, 1 = B */ 1078 #define EMU_HANA_MIDI_OUT_SYNC2 0x08 /* Sync card. Not the actual MIDI out jack. 0 = A, 1 = B */ 1079 #define EMU_HANA_MIDI_OUT_LOOP 0x10 /* 0 = bits (3:0) normal. 1 = MIDI loopback enabled. */ 1080 1081 #define EMU_HANA_DAC_PADS 0x13 /* 00xxxxx 5 bit DAC 14dB attenuation pads */ 1082 #define EMU_HANA_DOCK_DAC_PAD1 0x01 /* 14dB Attenuation on AudioDock DAC 1. Left and Right */ 1083 #define EMU_HANA_DOCK_DAC_PAD2 0x02 /* 14dB Attenuation on AudioDock DAC 2. Left and Right */ 1084 #define EMU_HANA_DOCK_DAC_PAD3 0x04 /* 14dB Attenuation on AudioDock DAC 3. Left and Right */ 1085 #define EMU_HANA_DOCK_DAC_PAD4 0x08 /* 14dB Attenuation on AudioDock DAC 4. Left and Right */ 1086 #define EMU_HANA_0202_DAC_PAD1 0x10 /* 14dB Attenuation on 0202 DAC 1. Left and Right */ 1087 1088 /* 0x14 - 0x1f Unused R/W registers */ 1089 1090 #define EMU_HANA_IRQ_STATUS 0x20 /* 00xxxxx 5 bits IRQ Status */ 1091 /* Same bits as for EMU_HANA_IRQ_ENABLE */ 1092 /* Reading the register resets it. */ 1093 1094 #define EMU_HANA_OPTION_CARDS 0x21 /* 000xxxx 4 bits Presence of option cards */ 1095 #define EMU_HANA_OPTION_HAMOA 0x01 /* Hamoa (analog I/O) card present */ 1096 #define EMU_HANA_OPTION_SYNC 0x02 /* Sync card present */ 1097 #define EMU_HANA_OPTION_DOCK_ONLINE 0x04 /* Audio/Micro dock present and FPGA configured */ 1098 #define EMU_HANA_OPTION_DOCK_OFFLINE 0x08 /* Audio/Micro dock present and FPGA not configured */ 1099 1100 #define EMU_HANA_ID 0x22 /* 1010101 7 bits ID byte & 0x7f = 0x55 with Alice2 */ 1101 /* 0010101 5 bits ID byte & 0x1f = 0x15 with Tina/2 */ 1102 1103 #define EMU_HANA_MAJOR_REV 0x23 /* 0000xxx 3 bit Hana FPGA Major rev */ 1104 #define EMU_HANA_MINOR_REV 0x24 /* 0000xxx 3 bit Hana FPGA Minor rev */ 1105 1106 #define EMU_DOCK_MAJOR_REV 0x25 /* 0000xxx 3 bit Audio Dock FPGA Major rev */ 1107 #define EMU_DOCK_MINOR_REV 0x26 /* 0000xxx 3 bit Audio Dock FPGA Minor rev */ 1108 1109 #define EMU_DOCK_BOARD_ID 0x27 /* 00000xx 2 bits Audio Dock ID pins */ 1110 #define EMU_DOCK_BOARD_ID0 0x00 /* ID bit 0 */ 1111 #define EMU_DOCK_BOARD_ID1 0x03 /* ID bit 1 */ 1112 1113 // The actual code disagrees about the bit width of the registers - 1114 // the formula used is freq = 0x1770000 / (((X_HI << 5) | X_LO) + 1) 1115 1116 #define EMU_HANA_WC_SPDIF_HI 0x28 /* 0xxxxxx 6 bit SPDIF IN Word clock, upper 6 bits */ 1117 #define EMU_HANA_WC_SPDIF_LO 0x29 /* 0xxxxxx 6 bit SPDIF IN Word clock, lower 6 bits */ 1118 1119 #define EMU_HANA_WC_ADAT_HI 0x2a /* 0xxxxxx 6 bit ADAT IN Word clock, upper 6 bits */ 1120 #define EMU_HANA_WC_ADAT_LO 0x2b /* 0xxxxxx 6 bit ADAT IN Word clock, lower 6 bits */ 1121 1122 #define EMU_HANA_WC_BNC_LO 0x2c /* 0xxxxxx 6 bit BNC IN Word clock, lower 6 bits */ 1123 #define EMU_HANA_WC_BNC_HI 0x2d /* 0xxxxxx 6 bit BNC IN Word clock, upper 6 bits */ 1124 1125 #define EMU_HANA2_WC_SPDIF_HI 0x2e /* 0xxxxxx 6 bit HANA2 SPDIF IN Word clock, upper 6 bits */ 1126 #define EMU_HANA2_WC_SPDIF_LO 0x2f /* 0xxxxxx 6 bit HANA2 SPDIF IN Word clock, lower 6 bits */ 1127 1128 /* 0x30 - 0x3f Unused Read only registers */ 1129 1130 // The meaning of this is not clear; kX-project just calls it "lock" in some info-only code. 1131 #define EMU_HANA_LOCK_STS_LO 0x38 /* 0xxxxxx lower 6 bits */ 1132 #define EMU_HANA_LOCK_STS_HI 0x39 /* 0xxxxxx upper 6 bits */ 1133 1134 /************************************************************************************************/ 1135 /* EMU1010 Audio Destinations */ 1136 /************************************************************************************************/ 1137 /* Hana, original 1010,1212m,1820[m] using Alice2 1138 * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2 1139 * 0x01, 0x00-0x1f: 32 EDI channels to Audio Dock 1140 * 0x00: Dock DAC 1 Left 1141 * 0x04: Dock DAC 1 Right 1142 * 0x08: Dock DAC 2 Left 1143 * 0x0c: Dock DAC 2 Right 1144 * 0x10: Dock DAC 3 Left 1145 * 0x12: PHONES Left (n/a in 2x/4x mode; output mirrors DAC4 Left) 1146 * 0x14: Dock DAC 3 Right 1147 * 0x16: PHONES Right (n/a in 2x/4x mode; output mirrors DAC4 Right) 1148 * 0x18: Dock DAC 4 Left 1149 * 0x1a: S/PDIF Left 1150 * 0x1c: Dock DAC 4 Right 1151 * 0x1e: S/PDIF Right 1152 * 0x02, 0x00: Hana S/PDIF Left 1153 * 0x02, 0x01: Hana S/PDIF Right 1154 * 0x03, 0x00: Hamoa DAC Left 1155 * 0x03, 0x01: Hamoa DAC Right 1156 * 0x04, 0x00-0x07: Hana ADAT 1157 * 0x05, 0x00: I2S0 Left to Alice2 1158 * 0x05, 0x01: I2S0 Right to Alice2 1159 * 0x06, 0x00: I2S0 Left to Alice2 1160 * 0x06, 0x01: I2S0 Right to Alice2 1161 * 0x07, 0x00: I2S0 Left to Alice2 1162 * 0x07, 0x01: I2S0 Right to Alice2 1163 * 1164 * Hana2 never released, but used Tina 1165 * Not needed. 1166 * 1167 * Hana3, rev2 1010,1212m,1616[m] using Tina 1168 * 0x00, 0x00-0x0f: 16 EMU32A channels to Tina 1169 * 0x01, 0x00-0x1f: 32 EDI channels to Micro Dock 1170 * 0x00: Dock DAC 1 Left 1171 * 0x04: Dock DAC 1 Right 1172 * 0x08: Dock DAC 2 Left 1173 * 0x0c: Dock DAC 2 Right 1174 * 0x10: Dock DAC 3 Left 1175 * 0x12: Dock S/PDIF Left 1176 * 0x14: Dock DAC 3 Right 1177 * 0x16: Dock S/PDIF Right 1178 * 0x18-0x1f: Dock ADAT 0-7 1179 * 0x02, 0x00: Hana3 S/PDIF Left 1180 * 0x02, 0x01: Hana3 S/PDIF Right 1181 * 0x03, 0x00: Hamoa DAC Left 1182 * 0x03, 0x01: Hamoa DAC Right 1183 * 0x04, 0x00-0x07: Hana3 ADAT 0-7 1184 * 0x05, 0x00-0x0f: 16 EMU32B channels to Tina 1185 * 0x06-0x07: Not used 1186 * 1187 * HanaLite, rev1 0404 using Alice2 1188 * HanaLiteLite, rev2 0404 using Tina 1189 * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2/Tina 1190 * 0x01: Not used 1191 * 0x02, 0x00: S/PDIF Left 1192 * 0x02, 0x01: S/PDIF Right 1193 * 0x03, 0x00: DAC Left 1194 * 0x03, 0x01: DAC Right 1195 * 0x04-0x07: Not used 1196 * 1197 * Mana, Cardbus 1616 using Tina2 1198 * 0x00, 0x00-0x0f: 16 EMU32A channels to Tina2 1199 * 0x01, 0x00-0x1f: 32 EDI channels to Micro Dock 1200 * (same as rev2 1010) 1201 * 0x02: Not used 1202 * 0x03, 0x00: Mana DAC Left 1203 * 0x03, 0x01: Mana DAC Right 1204 * 0x04, 0x00-0x0f: 16 EMU32B channels to Tina2 1205 * 0x05-0x07: Not used 1206 */ 1207 1208 /* 32-bit destinations of signal in the Hana FPGA. Destinations are either 1209 * physical outputs of Hana, or outputs going to Alice2/Tina for capture - 1210 * 16 x EMU_DST_ALICE2_EMU32_X (2x on rev2 boards). Which data is fed into 1211 * a channel depends on the mixer control setting for each destination - see 1212 * the register arrays in emumixer.c. 1213 */ 1214 #define EMU_DST_ALICE2_EMU32_0 0x000f /* 16 EMU32 channels to Alice2 +0 to +0xf */ 1215 /* This channel is delayed by one sample. */ 1216 #define EMU_DST_ALICE2_EMU32_1 0x0000 /* 16 EMU32 channels to Alice2 +0 to +0xf */ 1217 #define EMU_DST_ALICE2_EMU32_2 0x0001 /* 16 EMU32 channels to Alice2 +0 to +0xf */ 1218 #define EMU_DST_ALICE2_EMU32_3 0x0002 /* 16 EMU32 channels to Alice2 +0 to +0xf */ 1219 #define EMU_DST_ALICE2_EMU32_4 0x0003 /* 16 EMU32 channels to Alice2 +0 to +0xf */ 1220 #define EMU_DST_ALICE2_EMU32_5 0x0004 /* 16 EMU32 channels to Alice2 +0 to +0xf */ 1221 #define EMU_DST_ALICE2_EMU32_6 0x0005 /* 16 EMU32 channels to Alice2 +0 to +0xf */ 1222 #define EMU_DST_ALICE2_EMU32_7 0x0006 /* 16 EMU32 channels to Alice2 +0 to +0xf */ 1223 #define EMU_DST_ALICE2_EMU32_8 0x0007 /* 16 EMU32 channels to Alice2 +0 to +0xf */ 1224 #define EMU_DST_ALICE2_EMU32_9 0x0008 /* 16 EMU32 channels to Alice2 +0 to +0xf */ 1225 #define EMU_DST_ALICE2_EMU32_A 0x0009 /* 16 EMU32 channels to Alice2 +0 to +0xf */ 1226 #define EMU_DST_ALICE2_EMU32_B 0x000a /* 16 EMU32 channels to Alice2 +0 to +0xf */ 1227 #define EMU_DST_ALICE2_EMU32_C 0x000b /* 16 EMU32 channels to Alice2 +0 to +0xf */ 1228 #define EMU_DST_ALICE2_EMU32_D 0x000c /* 16 EMU32 channels to Alice2 +0 to +0xf */ 1229 #define EMU_DST_ALICE2_EMU32_E 0x000d /* 16 EMU32 channels to Alice2 +0 to +0xf */ 1230 #define EMU_DST_ALICE2_EMU32_F 0x000e /* 16 EMU32 channels to Alice2 +0 to +0xf */ 1231 #define EMU_DST_DOCK_DAC1_LEFT1 0x0100 /* Audio Dock DAC1 Left, 1st or 48kHz only */ 1232 #define EMU_DST_DOCK_DAC1_LEFT2 0x0101 /* Audio Dock DAC1 Left, 2nd or 96kHz */ 1233 #define EMU_DST_DOCK_DAC1_LEFT3 0x0102 /* Audio Dock DAC1 Left, 3rd or 192kHz */ 1234 #define EMU_DST_DOCK_DAC1_LEFT4 0x0103 /* Audio Dock DAC1 Left, 4th or 192kHz */ 1235 #define EMU_DST_DOCK_DAC1_RIGHT1 0x0104 /* Audio Dock DAC1 Right, 1st or 48kHz only */ 1236 #define EMU_DST_DOCK_DAC1_RIGHT2 0x0105 /* Audio Dock DAC1 Right, 2nd or 96kHz */ 1237 #define EMU_DST_DOCK_DAC1_RIGHT3 0x0106 /* Audio Dock DAC1 Right, 3rd or 192kHz */ 1238 #define EMU_DST_DOCK_DAC1_RIGHT4 0x0107 /* Audio Dock DAC1 Right, 4th or 192kHz */ 1239 #define EMU_DST_DOCK_DAC2_LEFT1 0x0108 /* Audio Dock DAC2 Left, 1st or 48kHz only */ 1240 #define EMU_DST_DOCK_DAC2_LEFT2 0x0109 /* Audio Dock DAC2 Left, 2nd or 96kHz */ 1241 #define EMU_DST_DOCK_DAC2_LEFT3 0x010a /* Audio Dock DAC2 Left, 3rd or 192kHz */ 1242 #define EMU_DST_DOCK_DAC2_LEFT4 0x010b /* Audio Dock DAC2 Left, 4th or 192kHz */ 1243 #define EMU_DST_DOCK_DAC2_RIGHT1 0x010c /* Audio Dock DAC2 Right, 1st or 48kHz only */ 1244 #define EMU_DST_DOCK_DAC2_RIGHT2 0x010d /* Audio Dock DAC2 Right, 2nd or 96kHz */ 1245 #define EMU_DST_DOCK_DAC2_RIGHT3 0x010e /* Audio Dock DAC2 Right, 3rd or 192kHz */ 1246 #define EMU_DST_DOCK_DAC2_RIGHT4 0x010f /* Audio Dock DAC2 Right, 4th or 192kHz */ 1247 #define EMU_DST_DOCK_DAC3_LEFT1 0x0110 /* Audio Dock DAC1 Left, 1st or 48kHz only */ 1248 #define EMU_DST_DOCK_DAC3_LEFT2 0x0111 /* Audio Dock DAC1 Left, 2nd or 96kHz */ 1249 #define EMU_DST_DOCK_DAC3_LEFT3 0x0112 /* Audio Dock DAC1 Left, 3rd or 192kHz */ 1250 #define EMU_DST_DOCK_DAC3_LEFT4 0x0113 /* Audio Dock DAC1 Left, 4th or 192kHz */ 1251 #define EMU_DST_DOCK_PHONES_LEFT1 0x0112 /* Audio Dock PHONES Left, 1st or 48kHz only */ 1252 #define EMU_DST_DOCK_PHONES_LEFT2 0x0113 /* Audio Dock PHONES Left, 2nd or 96kHz */ 1253 #define EMU_DST_DOCK_DAC3_RIGHT1 0x0114 /* Audio Dock DAC1 Right, 1st or 48kHz only */ 1254 #define EMU_DST_DOCK_DAC3_RIGHT2 0x0115 /* Audio Dock DAC1 Right, 2nd or 96kHz */ 1255 #define EMU_DST_DOCK_DAC3_RIGHT3 0x0116 /* Audio Dock DAC1 Right, 3rd or 192kHz */ 1256 #define EMU_DST_DOCK_DAC3_RIGHT4 0x0117 /* Audio Dock DAC1 Right, 4th or 192kHz */ 1257 #define EMU_DST_DOCK_PHONES_RIGHT1 0x0116 /* Audio Dock PHONES Right, 1st or 48kHz only */ 1258 #define EMU_DST_DOCK_PHONES_RIGHT2 0x0117 /* Audio Dock PHONES Right, 2nd or 96kHz */ 1259 #define EMU_DST_DOCK_DAC4_LEFT1 0x0118 /* Audio Dock DAC2 Left, 1st or 48kHz only */ 1260 #define EMU_DST_DOCK_DAC4_LEFT2 0x0119 /* Audio Dock DAC2 Left, 2nd or 96kHz */ 1261 #define EMU_DST_DOCK_DAC4_LEFT3 0x011a /* Audio Dock DAC2 Left, 3rd or 192kHz */ 1262 #define EMU_DST_DOCK_DAC4_LEFT4 0x011b /* Audio Dock DAC2 Left, 4th or 192kHz */ 1263 #define EMU_DST_DOCK_SPDIF_LEFT1 0x011a /* Audio Dock SPDIF Left, 1st or 48kHz only */ 1264 #define EMU_DST_DOCK_SPDIF_LEFT2 0x011b /* Audio Dock SPDIF Left, 2nd or 96kHz */ 1265 #define EMU_DST_DOCK_DAC4_RIGHT1 0x011c /* Audio Dock DAC2 Right, 1st or 48kHz only */ 1266 #define EMU_DST_DOCK_DAC4_RIGHT2 0x011d /* Audio Dock DAC2 Right, 2nd or 96kHz */ 1267 #define EMU_DST_DOCK_DAC4_RIGHT3 0x011e /* Audio Dock DAC2 Right, 3rd or 192kHz */ 1268 #define EMU_DST_DOCK_DAC4_RIGHT4 0x011f /* Audio Dock DAC2 Right, 4th or 192kHz */ 1269 #define EMU_DST_DOCK_SPDIF_RIGHT1 0x011e /* Audio Dock SPDIF Right, 1st or 48kHz only */ 1270 #define EMU_DST_DOCK_SPDIF_RIGHT2 0x011f /* Audio Dock SPDIF Right, 2nd or 96kHz */ 1271 #define EMU_DST_HANA_SPDIF_LEFT1 0x0200 /* Hana SPDIF Left, 1st or 48kHz only */ 1272 #define EMU_DST_HANA_SPDIF_LEFT2 0x0202 /* Hana SPDIF Left, 2nd or 96kHz */ 1273 #define EMU_DST_HANA_SPDIF_LEFT3 0x0204 /* Hana SPDIF Left, 3rd or 192kHz */ 1274 #define EMU_DST_HANA_SPDIF_LEFT4 0x0206 /* Hana SPDIF Left, 4th or 192kHz */ 1275 #define EMU_DST_HANA_SPDIF_RIGHT1 0x0201 /* Hana SPDIF Right, 1st or 48kHz only */ 1276 #define EMU_DST_HANA_SPDIF_RIGHT2 0x0203 /* Hana SPDIF Right, 2nd or 96kHz */ 1277 #define EMU_DST_HANA_SPDIF_RIGHT3 0x0205 /* Hana SPDIF Right, 3rd or 192kHz */ 1278 #define EMU_DST_HANA_SPDIF_RIGHT4 0x0207 /* Hana SPDIF Right, 4th or 192kHz */ 1279 #define EMU_DST_HAMOA_DAC_LEFT1 0x0300 /* Hamoa DAC Left, 1st or 48kHz only */ 1280 #define EMU_DST_HAMOA_DAC_LEFT2 0x0302 /* Hamoa DAC Left, 2nd or 96kHz */ 1281 #define EMU_DST_HAMOA_DAC_LEFT3 0x0304 /* Hamoa DAC Left, 3rd or 192kHz */ 1282 #define EMU_DST_HAMOA_DAC_LEFT4 0x0306 /* Hamoa DAC Left, 4th or 192kHz */ 1283 #define EMU_DST_HAMOA_DAC_RIGHT1 0x0301 /* Hamoa DAC Right, 1st or 48kHz only */ 1284 #define EMU_DST_HAMOA_DAC_RIGHT2 0x0303 /* Hamoa DAC Right, 2nd or 96kHz */ 1285 #define EMU_DST_HAMOA_DAC_RIGHT3 0x0305 /* Hamoa DAC Right, 3rd or 192kHz */ 1286 #define EMU_DST_HAMOA_DAC_RIGHT4 0x0307 /* Hamoa DAC Right, 4th or 192kHz */ 1287 // In S/MUX mode, the samples of one channel are adjacent. 1288 #define EMU_DST_HANA_ADAT 0x0400 /* Hana ADAT 8 channel out +0 to +7 */ 1289 #define EMU_DST_ALICE_I2S0_LEFT 0x0500 /* Alice2 I2S0 Left */ 1290 #define EMU_DST_ALICE_I2S0_RIGHT 0x0501 /* Alice2 I2S0 Right */ 1291 #define EMU_DST_ALICE_I2S1_LEFT 0x0600 /* Alice2 I2S1 Left */ 1292 #define EMU_DST_ALICE_I2S1_RIGHT 0x0601 /* Alice2 I2S1 Right */ 1293 #define EMU_DST_ALICE_I2S2_LEFT 0x0700 /* Alice2 I2S2 Left */ 1294 #define EMU_DST_ALICE_I2S2_RIGHT 0x0701 /* Alice2 I2S2 Right */ 1295 1296 /* Additional destinations for 1616(M)/Microdock */ 1297 1298 #define EMU_DST_MDOCK_SPDIF_LEFT1 0x0112 /* Microdock S/PDIF OUT Left, 1st or 48kHz only */ 1299 #define EMU_DST_MDOCK_SPDIF_LEFT2 0x0113 /* Microdock S/PDIF OUT Left, 2nd or 96kHz */ 1300 #define EMU_DST_MDOCK_SPDIF_RIGHT1 0x0116 /* Microdock S/PDIF OUT Right, 1st or 48kHz only */ 1301 #define EMU_DST_MDOCK_SPDIF_RIGHT2 0x0117 /* Microdock S/PDIF OUT Right, 2nd or 96kHz */ 1302 #define EMU_DST_MDOCK_ADAT 0x0118 /* Microdock S/PDIF ADAT 8 channel out +8 to +f */ 1303 1304 #define EMU_DST_MANA_DAC_LEFT 0x0300 /* Headphone jack on 1010 cardbus? 44.1/48kHz only? */ 1305 #define EMU_DST_MANA_DAC_RIGHT 0x0301 /* Headphone jack on 1010 cardbus? 44.1/48kHz only? */ 1306 1307 /************************************************************************************************/ 1308 /* EMU1010 Audio Sources */ 1309 /************************************************************************************************/ 1310 /* Hana, original 1010,1212m,1820[m] using Alice2 1311 * 0x00, 0x00-0x1f: Silence 1312 * 0x01, 0x00-0x1f: 32 EDI channels from Audio Dock 1313 * 0x00: Dock Mic A 1314 * 0x04: Dock Mic B 1315 * 0x08: Dock ADC 1 Left 1316 * 0x0c: Dock ADC 1 Right 1317 * 0x10: Dock ADC 2 Left 1318 * 0x14: Dock ADC 2 Right 1319 * 0x18: Dock ADC 3 Left 1320 * 0x1c: Dock ADC 3 Right 1321 * 0x02, 0x00: Hamoa ADC Left 1322 * 0x02, 0x01: Hamoa ADC Right 1323 * 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu32A output 1324 * 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu32B output 1325 * 0x04, 0x00-0x07: Hana ADAT 1326 * 0x05, 0x00: Hana S/PDIF Left 1327 * 0x05, 0x01: Hana S/PDIF Right 1328 * 0x06-0x07: Not used 1329 * 1330 * Hana2 never released, but used Tina 1331 * Not needed. 1332 * 1333 * Hana3, rev2 1010,1212m,1616[m] using Tina 1334 * 0x00, 0x00-0x1f: Silence 1335 * 0x01, 0x00-0x1f: 32 EDI channels from Micro Dock 1336 * 0x00: Dock Mic A 1337 * 0x04: Dock Mic B 1338 * 0x08: Dock ADC 1 Left 1339 * 0x0c: Dock ADC 1 Right 1340 * 0x10: Dock ADC 2 Left 1341 * 0x12: Dock S/PDIF Left 1342 * 0x14: Dock ADC 2 Right 1343 * 0x16: Dock S/PDIF Right 1344 * 0x18-0x1f: Dock ADAT 0-7 1345 * 0x02, 0x00: Hamoa ADC Left 1346 * 0x02, 0x01: Hamoa ADC Right 1347 * 0x03, 0x00-0x0f: 16 inputs from Tina Emu32A output 1348 * 0x03, 0x10-0x1f: 16 inputs from Tina Emu32B output 1349 * 0x04, 0x00-0x07: Hana3 ADAT 1350 * 0x05, 0x00: Hana3 S/PDIF Left 1351 * 0x05, 0x01: Hana3 S/PDIF Right 1352 * 0x06-0x07: Not used 1353 * 1354 * HanaLite, rev1 0404 using Alice2 1355 * HanaLiteLite, rev2 0404 using Tina 1356 * 0x00, 0x00-0x1f: Silence 1357 * 0x01: Not used 1358 * 0x02, 0x00: ADC Left 1359 * 0x02, 0x01: ADC Right 1360 * 0x03, 0x00-0x0f: 16 inputs from Alice2/Tina Emu32A output 1361 * 0x03, 0x10-0x1f: 16 inputs from Alice2/Tina Emu32B output 1362 * 0x04: Not used 1363 * 0x05, 0x00: S/PDIF Left 1364 * 0x05, 0x01: S/PDIF Right 1365 * 0x06-0x07: Not used 1366 * 1367 * Mana, Cardbus 1616 using Tina2 1368 * 0x00, 0x00-0x1f: Silence 1369 * 0x01, 0x00-0x1f: 32 EDI channels from Micro Dock 1370 * (same as rev2 1010) 1371 * 0x02: Not used 1372 * 0x03, 0x00-0x0f: 16 inputs from Tina2 Emu32A output 1373 * 0x03, 0x10-0x1f: 16 inputs from Tina2 Emu32B output 1374 * 0x04-0x07: Not used 1375 */ 1376 1377 /* 32-bit sources of signal in the Hana FPGA. The sources are routed to 1378 * destinations using a mixer control for each destination - see emumixer.c. 1379 * Sources are either physical inputs of Hana, or inputs from Alice2/Tina - 1380 * 16 x EMU_SRC_ALICE_EMU32A + 16 x EMU_SRC_ALICE_EMU32B. 1381 */ 1382 #define EMU_SRC_SILENCE 0x0000 /* Silence */ 1383 #define EMU_SRC_DOCK_MIC_A1 0x0100 /* Audio Dock Mic A, 1st or 48kHz only */ 1384 #define EMU_SRC_DOCK_MIC_A2 0x0101 /* Audio Dock Mic A, 2nd or 96kHz */ 1385 #define EMU_SRC_DOCK_MIC_A3 0x0102 /* Audio Dock Mic A, 3rd or 192kHz */ 1386 #define EMU_SRC_DOCK_MIC_A4 0x0103 /* Audio Dock Mic A, 4th or 192kHz */ 1387 #define EMU_SRC_DOCK_MIC_B1 0x0104 /* Audio Dock Mic B, 1st or 48kHz only */ 1388 #define EMU_SRC_DOCK_MIC_B2 0x0105 /* Audio Dock Mic B, 2nd or 96kHz */ 1389 #define EMU_SRC_DOCK_MIC_B3 0x0106 /* Audio Dock Mic B, 3rd or 192kHz */ 1390 #define EMU_SRC_DOCK_MIC_B4 0x0107 /* Audio Dock Mic B, 4th or 192kHz */ 1391 #define EMU_SRC_DOCK_ADC1_LEFT1 0x0108 /* Audio Dock ADC1 Left, 1st or 48kHz only */ 1392 #define EMU_SRC_DOCK_ADC1_LEFT2 0x0109 /* Audio Dock ADC1 Left, 2nd or 96kHz */ 1393 #define EMU_SRC_DOCK_ADC1_LEFT3 0x010a /* Audio Dock ADC1 Left, 3rd or 192kHz */ 1394 #define EMU_SRC_DOCK_ADC1_LEFT4 0x010b /* Audio Dock ADC1 Left, 4th or 192kHz */ 1395 #define EMU_SRC_DOCK_ADC1_RIGHT1 0x010c /* Audio Dock ADC1 Right, 1st or 48kHz only */ 1396 #define EMU_SRC_DOCK_ADC1_RIGHT2 0x010d /* Audio Dock ADC1 Right, 2nd or 96kHz */ 1397 #define EMU_SRC_DOCK_ADC1_RIGHT3 0x010e /* Audio Dock ADC1 Right, 3rd or 192kHz */ 1398 #define EMU_SRC_DOCK_ADC1_RIGHT4 0x010f /* Audio Dock ADC1 Right, 4th or 192kHz */ 1399 #define EMU_SRC_DOCK_ADC2_LEFT1 0x0110 /* Audio Dock ADC2 Left, 1st or 48kHz only */ 1400 #define EMU_SRC_DOCK_ADC2_LEFT2 0x0111 /* Audio Dock ADC2 Left, 2nd or 96kHz */ 1401 #define EMU_SRC_DOCK_ADC2_LEFT3 0x0112 /* Audio Dock ADC2 Left, 3rd or 192kHz */ 1402 #define EMU_SRC_DOCK_ADC2_LEFT4 0x0113 /* Audio Dock ADC2 Left, 4th or 192kHz */ 1403 #define EMU_SRC_DOCK_ADC2_RIGHT1 0x0114 /* Audio Dock ADC2 Right, 1st or 48kHz only */ 1404 #define EMU_SRC_DOCK_ADC2_RIGHT2 0x0115 /* Audio Dock ADC2 Right, 2nd or 96kHz */ 1405 #define EMU_SRC_DOCK_ADC2_RIGHT3 0x0116 /* Audio Dock ADC2 Right, 3rd or 192kHz */ 1406 #define EMU_SRC_DOCK_ADC2_RIGHT4 0x0117 /* Audio Dock ADC2 Right, 4th or 192kHz */ 1407 #define EMU_SRC_DOCK_ADC3_LEFT1 0x0118 /* Audio Dock ADC3 Left, 1st or 48kHz only */ 1408 #define EMU_SRC_DOCK_ADC3_LEFT2 0x0119 /* Audio Dock ADC3 Left, 2nd or 96kHz */ 1409 #define EMU_SRC_DOCK_ADC3_LEFT3 0x011a /* Audio Dock ADC3 Left, 3rd or 192kHz */ 1410 #define EMU_SRC_DOCK_ADC3_LEFT4 0x011b /* Audio Dock ADC3 Left, 4th or 192kHz */ 1411 #define EMU_SRC_DOCK_ADC3_RIGHT1 0x011c /* Audio Dock ADC3 Right, 1st or 48kHz only */ 1412 #define EMU_SRC_DOCK_ADC3_RIGHT2 0x011d /* Audio Dock ADC3 Right, 2nd or 96kHz */ 1413 #define EMU_SRC_DOCK_ADC3_RIGHT3 0x011e /* Audio Dock ADC3 Right, 3rd or 192kHz */ 1414 #define EMU_SRC_DOCK_ADC3_RIGHT4 0x011f /* Audio Dock ADC3 Right, 4th or 192kHz */ 1415 #define EMU_SRC_HAMOA_ADC_LEFT1 0x0200 /* Hamoa ADC Left, 1st or 48kHz only */ 1416 #define EMU_SRC_HAMOA_ADC_LEFT2 0x0202 /* Hamoa ADC Left, 2nd or 96kHz */ 1417 #define EMU_SRC_HAMOA_ADC_LEFT3 0x0204 /* Hamoa ADC Left, 3rd or 192kHz */ 1418 #define EMU_SRC_HAMOA_ADC_LEFT4 0x0206 /* Hamoa ADC Left, 4th or 192kHz */ 1419 #define EMU_SRC_HAMOA_ADC_RIGHT1 0x0201 /* Hamoa ADC Right, 1st or 48kHz only */ 1420 #define EMU_SRC_HAMOA_ADC_RIGHT2 0x0203 /* Hamoa ADC Right, 2nd or 96kHz */ 1421 #define EMU_SRC_HAMOA_ADC_RIGHT3 0x0205 /* Hamoa ADC Right, 3rd or 192kHz */ 1422 #define EMU_SRC_HAMOA_ADC_RIGHT4 0x0207 /* Hamoa ADC Right, 4th or 192kHz */ 1423 #define EMU_SRC_ALICE_EMU32A 0x0300 /* Alice2 EMU32a 16 outputs. +0 to +0xf */ 1424 #define EMU_SRC_ALICE_EMU32B 0x0310 /* Alice2 EMU32b 16 outputs. +0 to +0xf */ 1425 // In S/MUX mode, the samples of one channel are adjacent. 1426 #define EMU_SRC_HANA_ADAT 0x0400 /* Hana ADAT 8 channel in +0 to +7 */ 1427 #define EMU_SRC_HANA_SPDIF_LEFT1 0x0500 /* Hana SPDIF Left, 1st or 48kHz only */ 1428 #define EMU_SRC_HANA_SPDIF_LEFT2 0x0502 /* Hana SPDIF Left, 2nd or 96kHz */ 1429 #define EMU_SRC_HANA_SPDIF_LEFT3 0x0504 /* Hana SPDIF Left, 3rd or 192kHz */ 1430 #define EMU_SRC_HANA_SPDIF_LEFT4 0x0506 /* Hana SPDIF Left, 4th or 192kHz */ 1431 #define EMU_SRC_HANA_SPDIF_RIGHT1 0x0501 /* Hana SPDIF Right, 1st or 48kHz only */ 1432 #define EMU_SRC_HANA_SPDIF_RIGHT2 0x0503 /* Hana SPDIF Right, 2nd or 96kHz */ 1433 #define EMU_SRC_HANA_SPDIF_RIGHT3 0x0505 /* Hana SPDIF Right, 3rd or 192kHz */ 1434 #define EMU_SRC_HANA_SPDIF_RIGHT4 0x0507 /* Hana SPDIF Right, 4th or 192kHz */ 1435 1436 /* Additional inputs for 1616(M)/Microdock */ 1437 1438 #define EMU_SRC_MDOCK_SPDIF_LEFT1 0x0112 /* Microdock S/PDIF Left, 1st or 48kHz only */ 1439 #define EMU_SRC_MDOCK_SPDIF_LEFT2 0x0113 /* Microdock S/PDIF Left, 2nd or 96kHz */ 1440 #define EMU_SRC_MDOCK_SPDIF_RIGHT1 0x0116 /* Microdock S/PDIF Right, 1st or 48kHz only */ 1441 #define EMU_SRC_MDOCK_SPDIF_RIGHT2 0x0117 /* Microdock S/PDIF Right, 2nd or 96kHz */ 1442 #define EMU_SRC_MDOCK_ADAT 0x0118 /* Microdock ADAT 8 channel in +8 to +f */ 1443 1444 /* 0x600 and 0x700 no used */ 1445 1446 1447 /* ------------------- CONSTANTS -------------------- */ 1448 1449 extern const char * const snd_emu10k1_fxbus[32]; 1450 extern const char * const snd_emu10k1_sblive_ins[16]; 1451 extern const char * const snd_emu10k1_audigy_ins[16]; 1452 extern const char * const snd_emu10k1_sblive_outs[32]; 1453 extern const char * const snd_emu10k1_audigy_outs[32]; 1454 extern const s8 snd_emu10k1_sblive51_fxbus2_map[16]; 1455 1456 /* ------------------- STRUCTURES -------------------- */ 1457 1458 enum { 1459 EMU10K1_UNUSED, // This must be zero 1460 EMU10K1_EFX, 1461 EMU10K1_EFX_IRQ, 1462 EMU10K1_PCM, 1463 EMU10K1_PCM_IRQ, 1464 EMU10K1_SYNTH, 1465 EMU10K1_NUM_TYPES 1466 }; 1467 1468 struct snd_emu10k1; 1469 1470 struct snd_emu10k1_voice { 1471 unsigned char number; 1472 unsigned char use; 1473 unsigned char dirty; 1474 unsigned char last; 1475 void (*interrupt)(struct snd_emu10k1 *emu, struct snd_emu10k1_voice *pvoice); 1476 1477 struct snd_emu10k1_pcm *epcm; 1478 }; 1479 1480 enum { 1481 PLAYBACK_EMUVOICE, 1482 PLAYBACK_EFX, 1483 CAPTURE_AC97ADC, 1484 CAPTURE_AC97MIC, 1485 CAPTURE_EFX 1486 }; 1487 1488 struct snd_emu10k1_pcm { 1489 struct snd_emu10k1 *emu; 1490 int type; 1491 struct snd_pcm_substream *substream; 1492 struct snd_emu10k1_voice *voices[NUM_EFX_PLAYBACK]; 1493 struct snd_emu10k1_voice *extra; 1494 unsigned short running; 1495 unsigned short first_ptr; 1496 snd_pcm_uframes_t resume_pos; 1497 struct snd_util_memblk *memblk; 1498 unsigned int pitch_target; 1499 unsigned int start_addr; 1500 unsigned int ccca_start_addr; 1501 unsigned int capture_ipr; /* interrupt acknowledge mask */ 1502 unsigned int capture_inte; /* interrupt enable mask */ 1503 unsigned int capture_ba_reg; /* buffer address register */ 1504 unsigned int capture_bs_reg; /* buffer size register */ 1505 unsigned int capture_idx_reg; /* buffer index register */ 1506 unsigned int capture_cr_val; /* control value */ 1507 unsigned int capture_cr_val2; /* control value2 (for audigy) */ 1508 unsigned int capture_bs_val; /* buffer size value */ 1509 unsigned int capture_bufsize; /* buffer size in bytes */ 1510 }; 1511 1512 struct snd_emu10k1_pcm_mixer { 1513 /* mono, left, right x 8 sends (4 on emu10k1) */ 1514 unsigned char send_routing[3][8]; 1515 unsigned char send_volume[3][8]; 1516 // 0x8000 is neutral. The mixer code rescales it to 0xffff to maintain 1517 // backwards compatibility with user space. 1518 unsigned short attn[3]; 1519 struct snd_emu10k1_pcm *epcm; 1520 }; 1521 1522 #define snd_emu10k1_compose_send_routing(route) \ 1523 ((route[0] | (route[1] << 4) | (route[2] << 8) | (route[3] << 12)) << 16) 1524 1525 #define snd_emu10k1_compose_audigy_fxrt1(route) \ 1526 ((unsigned int)route[0] | ((unsigned int)route[1] << 8) | ((unsigned int)route[2] << 16) | ((unsigned int)route[3] << 24)) 1527 1528 #define snd_emu10k1_compose_audigy_fxrt2(route) \ 1529 ((unsigned int)route[4] | ((unsigned int)route[5] << 8) | ((unsigned int)route[6] << 16) | ((unsigned int)route[7] << 24)) 1530 1531 #define snd_emu10k1_compose_audigy_sendamounts(vol) \ 1532 (((unsigned int)vol[4] << 24) | ((unsigned int)vol[5] << 16) | ((unsigned int)vol[6] << 8) | (unsigned int)vol[7]) 1533 1534 struct snd_emu10k1_memblk { 1535 struct snd_util_memblk mem; 1536 /* private part */ 1537 int first_page, last_page, pages, mapped_page; 1538 unsigned int map_locked; 1539 struct list_head mapped_link; 1540 struct list_head mapped_order_link; 1541 }; 1542 1543 #define snd_emu10k1_memblk_offset(blk) (((blk)->mapped_page << PAGE_SHIFT) | ((blk)->mem.offset & (PAGE_SIZE - 1))) 1544 1545 #define EMU10K1_MAX_TRAM_BLOCKS_PER_CODE 16 1546 1547 struct snd_emu10k1_fx8010_ctl { 1548 struct list_head list; /* list link container */ 1549 unsigned int vcount; 1550 unsigned int count; /* count of GPR (1..16) */ 1551 unsigned short gpr[32]; /* GPR number(s) */ 1552 int value[32]; 1553 int min; /* minimum range */ 1554 int max; /* maximum range */ 1555 unsigned int translation; /* translation type (EMU10K1_GPR_TRANSLATION*) */ 1556 struct snd_kcontrol *kcontrol; 1557 }; 1558 1559 typedef void (snd_fx8010_irq_handler_t)(struct snd_emu10k1 *emu, void *private_data); 1560 1561 struct snd_emu10k1_fx8010_irq { 1562 struct snd_emu10k1_fx8010_irq *next; 1563 snd_fx8010_irq_handler_t *handler; 1564 unsigned short gpr_running; 1565 void *private_data; 1566 }; 1567 1568 struct snd_emu10k1_fx8010_pcm { 1569 unsigned int valid: 1, 1570 opened: 1, 1571 active: 1; 1572 unsigned int channels; /* 16-bit channels count */ 1573 unsigned int tram_start; /* initial ring buffer position in TRAM (in samples) */ 1574 unsigned int buffer_size; /* count of buffered samples */ 1575 unsigned short gpr_size; /* GPR containing size of ring buffer in samples (host) */ 1576 unsigned short gpr_ptr; /* GPR containing current pointer in the ring buffer (host = reset, FX8010) */ 1577 unsigned short gpr_count; /* GPR containing count of samples between two interrupts (host) */ 1578 unsigned short gpr_tmpcount; /* GPR containing current count of samples to interrupt (host = set, FX8010) */ 1579 unsigned short gpr_trigger; /* GPR containing trigger (activate) information (host) */ 1580 unsigned short gpr_running; /* GPR containing info if PCM is running (FX8010) */ 1581 unsigned char etram[32]; /* external TRAM address & data */ 1582 struct snd_pcm_indirect pcm_rec; 1583 unsigned int tram_pos; 1584 unsigned int tram_shift; 1585 struct snd_emu10k1_fx8010_irq irq; 1586 }; 1587 1588 struct snd_emu10k1_fx8010 { 1589 unsigned short extin_mask; /* used external inputs (bitmask); not used for Audigy */ 1590 unsigned short extout_mask; /* used external outputs (bitmask); not used for Audigy */ 1591 unsigned int itram_size; /* internal TRAM size in samples */ 1592 struct snd_dma_buffer etram_pages; /* external TRAM pages and size */ 1593 unsigned int dbg; /* FX debugger register */ 1594 unsigned char name[128]; 1595 int gpr_size; /* size of allocated GPR controls */ 1596 int gpr_count; /* count of used kcontrols */ 1597 struct list_head gpr_ctl; /* GPR controls */ 1598 struct mutex lock; 1599 struct snd_emu10k1_fx8010_pcm pcm[8]; 1600 spinlock_t irq_lock; 1601 struct snd_emu10k1_fx8010_irq *irq_handlers; 1602 }; 1603 1604 struct snd_emu10k1_midi { 1605 struct snd_emu10k1 *emu; 1606 struct snd_rawmidi *rmidi; 1607 struct snd_rawmidi_substream *substream_input; 1608 struct snd_rawmidi_substream *substream_output; 1609 unsigned int midi_mode; 1610 spinlock_t input_lock; 1611 spinlock_t output_lock; 1612 spinlock_t open_lock; 1613 int tx_enable, rx_enable; 1614 int port; 1615 int ipr_tx, ipr_rx; 1616 void (*interrupt)(struct snd_emu10k1 *emu, unsigned int status); 1617 }; 1618 1619 enum { 1620 EMU_MODEL_SB, 1621 EMU_MODEL_EMU1010, 1622 EMU_MODEL_EMU1010B, 1623 EMU_MODEL_EMU1616, 1624 EMU_MODEL_EMU0404, 1625 }; 1626 1627 // Chip-o-logy: 1628 // - All SB Live! cards use EMU10K1 chips 1629 // - All SB Audigy cards use CA* chips, termed "emu10k2" by the driver 1630 // - Original Audigy uses CA0100 "Alice" 1631 // - Audigy 2 uses CA0102/CA10200 "Alice2" 1632 // - Has an interface for CA0151 (P16V) "Alice3" 1633 // - Audigy 2 Value uses CA0108/CA10300 "Tina" 1634 // - Approximately a CA0102 with an on-chip CA0151 (P17V) 1635 // - Audigy 2 ZS NB uses CA0109 "Tina2" 1636 // - Cardbus version of CA0108 1637 struct snd_emu_chip_details { 1638 u32 vendor; 1639 u32 device; 1640 u32 subsystem; 1641 unsigned char revision; 1642 unsigned char emu_model; /* EMU model type */ 1643 unsigned int emu10k1_chip:1; /* Original SB Live. Not SB Live 24bit. */ 1644 /* Redundant with emu10k2_chip being unset. */ 1645 unsigned int emu10k2_chip:1; /* Audigy 1 or Audigy 2. */ 1646 unsigned int ca0102_chip:1; /* Audigy 1 or Audigy 2. Not SB Audigy 2 Value. */ 1647 /* Redundant with ca0108_chip being unset. */ 1648 unsigned int ca0108_chip:1; /* Audigy 2 Value */ 1649 unsigned int ca_cardbus_chip:1; /* Audigy 2 ZS Notebook */ 1650 unsigned int ca0151_chip:1; /* P16V */ 1651 unsigned int spk20:1; /* Stereo only */ 1652 unsigned int spk71:1; /* Has 7.1 speakers */ 1653 unsigned int no_adat:1; /* Has no ADAT, only SPDIF */ 1654 unsigned int sblive51:1; /* SBLive! 5.1 - extout 0x11 -> center, 0x12 -> lfe */ 1655 unsigned int spdif_bug:1; /* Has Spdif phasing bug */ 1656 unsigned int ac97_chip:2; /* Has an AC97 chip: 1 = mandatory, 2 = optional */ 1657 unsigned int ecard:1; /* APS EEPROM */ 1658 unsigned int spi_dac:1; /* SPI interface for DAC; requires ca0108_chip */ 1659 unsigned int i2c_adc:1; /* I2C interface for ADC; requires ca0108_chip */ 1660 unsigned int adc_1361t:1; /* Use Philips 1361T ADC */ 1661 unsigned int invert_shared_spdif:1; /* analog/digital switch inverted */ 1662 const char *driver; 1663 const char *name; 1664 const char *id; /* for backward compatibility - can be NULL if not needed */ 1665 }; 1666 1667 #define NUM_OUTPUT_DESTS 28 1668 #define NUM_INPUT_DESTS 22 1669 1670 struct snd_emu1010 { 1671 unsigned char output_source[NUM_OUTPUT_DESTS]; 1672 unsigned char input_source[NUM_INPUT_DESTS]; 1673 unsigned int adc_pads; /* bit mask */ 1674 unsigned int dac_pads; /* bit mask */ 1675 unsigned int wclock; /* Cached register value */ 1676 unsigned int word_clock; /* Cached effective value */ 1677 unsigned int clock_source; 1678 unsigned int clock_fallback; 1679 unsigned int optical_in; /* 0:SPDIF, 1:ADAT */ 1680 unsigned int optical_out; /* 0:SPDIF, 1:ADAT */ 1681 struct delayed_work firmware_work; 1682 u32 last_reg; 1683 }; 1684 1685 struct snd_emu10k1 { 1686 int irq; 1687 1688 unsigned long port; /* I/O port number */ 1689 unsigned int tos_link: 1, /* tos link detected */ 1690 rear_ac97: 1, /* rear channels are on AC'97 */ 1691 enable_ir: 1; 1692 unsigned int support_tlv :1; 1693 /* Contains profile of card capabilities */ 1694 const struct snd_emu_chip_details *card_capabilities; 1695 unsigned int audigy; /* is Audigy? */ 1696 unsigned int revision; /* chip revision */ 1697 unsigned int serial; /* serial number */ 1698 unsigned short model; /* subsystem id */ 1699 unsigned int ecard_ctrl; /* ecard control bits */ 1700 unsigned int address_mode; /* address mode */ 1701 unsigned long dma_mask; /* PCI DMA mask */ 1702 bool iommu_workaround; /* IOMMU workaround needed */ 1703 int max_cache_pages; /* max memory size / PAGE_SIZE */ 1704 struct snd_dma_buffer silent_page; /* silent page */ 1705 struct snd_dma_buffer ptb_pages; /* page table pages */ 1706 struct snd_dma_device p16v_dma_dev; 1707 struct snd_dma_buffer *p16v_buffer; 1708 1709 struct snd_util_memhdr *memhdr; /* page allocation list */ 1710 1711 struct list_head mapped_link_head; 1712 struct list_head mapped_order_link_head; 1713 void **page_ptr_table; 1714 unsigned long *page_addr_table; 1715 spinlock_t memblk_lock; 1716 1717 unsigned int spdif_bits[3]; /* s/pdif out setup */ 1718 unsigned int i2c_capture_source; 1719 u8 i2c_capture_volume[4][2]; 1720 1721 struct snd_emu10k1_fx8010 fx8010; /* FX8010 info */ 1722 int gpr_base; 1723 1724 struct snd_ac97 *ac97; 1725 1726 struct pci_dev *pci; 1727 struct snd_card *card; 1728 struct snd_pcm *pcm; 1729 struct snd_pcm *pcm_mic; 1730 struct snd_pcm *pcm_efx; 1731 struct snd_pcm *pcm_multi; 1732 struct snd_pcm *pcm_p16v; 1733 1734 spinlock_t synth_lock; 1735 void *synth; 1736 int (*get_synth_voice)(struct snd_emu10k1 *emu); 1737 1738 spinlock_t reg_lock; // high-level driver lock 1739 spinlock_t emu_lock; // low-level i/o lock 1740 spinlock_t voice_lock; // voice allocator lock 1741 spinlock_t spi_lock; /* serialises access to spi port */ 1742 spinlock_t i2c_lock; /* serialises access to i2c port */ 1743 1744 struct snd_emu10k1_voice voices[NUM_G]; 1745 int p16v_device_offset; 1746 u32 p16v_capture_source; 1747 u32 p16v_capture_channel; 1748 struct snd_emu1010 emu1010; 1749 struct snd_emu10k1_pcm_mixer pcm_mixer[32]; 1750 struct snd_emu10k1_pcm_mixer efx_pcm_mixer[NUM_EFX_PLAYBACK]; 1751 struct snd_kcontrol *ctl_send_routing; 1752 struct snd_kcontrol *ctl_send_volume; 1753 struct snd_kcontrol *ctl_attn; 1754 struct snd_kcontrol *ctl_efx_send_routing; 1755 struct snd_kcontrol *ctl_efx_send_volume; 1756 struct snd_kcontrol *ctl_efx_attn; 1757 1758 void (*hwvol_interrupt)(struct snd_emu10k1 *emu, unsigned int status); 1759 void (*capture_interrupt)(struct snd_emu10k1 *emu, unsigned int status); 1760 void (*capture_mic_interrupt)(struct snd_emu10k1 *emu, unsigned int status); 1761 void (*capture_efx_interrupt)(struct snd_emu10k1 *emu, unsigned int status); 1762 void (*spdif_interrupt)(struct snd_emu10k1 *emu, unsigned int status); 1763 void (*dsp_interrupt)(struct snd_emu10k1 *emu); 1764 void (*p16v_interrupt)(struct snd_emu10k1 *emu); 1765 1766 struct snd_pcm_substream *pcm_capture_substream; 1767 struct snd_pcm_substream *pcm_capture_mic_substream; 1768 struct snd_pcm_substream *pcm_capture_efx_substream; 1769 1770 struct snd_timer *timer; 1771 1772 struct snd_emu10k1_midi midi; 1773 struct snd_emu10k1_midi midi2; /* for audigy */ 1774 1775 unsigned int efx_voices_mask[2]; 1776 unsigned int next_free_voice; 1777 1778 const struct firmware *firmware; 1779 const struct firmware *dock_fw; 1780 1781 #ifdef CONFIG_PM_SLEEP 1782 unsigned int *saved_ptr; 1783 unsigned int *saved_gpr; 1784 unsigned int *tram_val_saved; 1785 unsigned int *tram_addr_saved; 1786 unsigned int *saved_icode; 1787 unsigned int *p16v_saved; 1788 unsigned int saved_a_iocfg, saved_hcfg; 1789 bool suspend; 1790 #endif 1791 1792 }; 1793 1794 int snd_emu10k1_create(struct snd_card *card, 1795 struct pci_dev *pci, 1796 unsigned short extin_mask, 1797 unsigned short extout_mask, 1798 long max_cache_bytes, 1799 int enable_ir, 1800 uint subsystem); 1801 1802 int snd_emu10k1_pcm(struct snd_emu10k1 *emu, int device); 1803 int snd_emu10k1_pcm_mic(struct snd_emu10k1 *emu, int device); 1804 int snd_emu10k1_pcm_efx(struct snd_emu10k1 *emu, int device); 1805 int snd_p16v_pcm(struct snd_emu10k1 *emu, int device); 1806 int snd_p16v_mixer(struct snd_emu10k1 * emu); 1807 int snd_emu10k1_pcm_multi(struct snd_emu10k1 *emu, int device); 1808 int snd_emu10k1_fx8010_pcm(struct snd_emu10k1 *emu, int device); 1809 int snd_emu10k1_mixer(struct snd_emu10k1 * emu, int pcm_device, int multi_device); 1810 int snd_emu10k1_timer(struct snd_emu10k1 * emu, int device); 1811 int snd_emu10k1_fx8010_new(struct snd_emu10k1 *emu, int device); 1812 1813 irqreturn_t snd_emu10k1_interrupt(int irq, void *dev_id); 1814 1815 void snd_emu10k1_voice_init(struct snd_emu10k1 * emu, int voice); 1816 int snd_emu10k1_init_efx(struct snd_emu10k1 *emu); 1817 void snd_emu10k1_free_efx(struct snd_emu10k1 *emu); 1818 int snd_emu10k1_fx8010_tram_setup(struct snd_emu10k1 *emu, u32 size); 1819 int snd_emu10k1_done(struct snd_emu10k1 * emu); 1820 1821 /* I/O functions */ 1822 unsigned int snd_emu10k1_ptr_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn); 1823 void snd_emu10k1_ptr_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data); 1824 void snd_emu10k1_ptr_write_multiple(struct snd_emu10k1 *emu, unsigned int chn, ...); 1825 unsigned int snd_emu10k1_ptr20_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn); 1826 void snd_emu10k1_ptr20_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data); 1827 int snd_emu10k1_spi_write(struct snd_emu10k1 * emu, unsigned int data); 1828 int snd_emu10k1_i2c_write(struct snd_emu10k1 *emu, u32 reg, u32 value); 1829 void snd_emu1010_fpga_write(struct snd_emu10k1 *emu, u32 reg, u32 value); 1830 void snd_emu1010_fpga_read(struct snd_emu10k1 *emu, u32 reg, u32 *value); 1831 void snd_emu1010_fpga_link_dst_src_write(struct snd_emu10k1 *emu, u32 dst, u32 src); 1832 u32 snd_emu1010_fpga_link_dst_src_read(struct snd_emu10k1 *emu, u32 dst); 1833 int snd_emu1010_get_raw_rate(struct snd_emu10k1 *emu, u8 src); 1834 void snd_emu1010_update_clock(struct snd_emu10k1 *emu); 1835 unsigned int snd_emu10k1_efx_read(struct snd_emu10k1 *emu, unsigned int pc); 1836 void snd_emu10k1_intr_enable(struct snd_emu10k1 *emu, unsigned int intrenb); 1837 void snd_emu10k1_intr_disable(struct snd_emu10k1 *emu, unsigned int intrenb); 1838 void snd_emu10k1_voice_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum); 1839 void snd_emu10k1_voice_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum); 1840 void snd_emu10k1_voice_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum); 1841 void snd_emu10k1_voice_half_loop_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum); 1842 void snd_emu10k1_voice_half_loop_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum); 1843 void snd_emu10k1_voice_half_loop_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum); 1844 #if 0 1845 void snd_emu10k1_voice_set_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum); 1846 void snd_emu10k1_voice_clear_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum); 1847 #endif 1848 void snd_emu10k1_voice_set_loop_stop_multiple(struct snd_emu10k1 *emu, u64 voices); 1849 void snd_emu10k1_voice_clear_loop_stop_multiple(struct snd_emu10k1 *emu, u64 voices); 1850 int snd_emu10k1_voice_clear_loop_stop_multiple_atomic(struct snd_emu10k1 *emu, u64 voices); 1851 void snd_emu10k1_wait(struct snd_emu10k1 *emu, unsigned int wait); 1852 static inline unsigned int snd_emu10k1_wc(struct snd_emu10k1 *emu) { return (inl(emu->port + WC) >> 6) & 0xfffff; } 1853 unsigned short snd_emu10k1_ac97_read(struct snd_ac97 *ac97, unsigned short reg); 1854 void snd_emu10k1_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short data); 1855 1856 #ifdef CONFIG_PM_SLEEP 1857 void snd_emu10k1_suspend_regs(struct snd_emu10k1 *emu); 1858 void snd_emu10k1_resume_init(struct snd_emu10k1 *emu); 1859 void snd_emu10k1_resume_regs(struct snd_emu10k1 *emu); 1860 int snd_emu10k1_efx_alloc_pm_buffer(struct snd_emu10k1 *emu); 1861 void snd_emu10k1_efx_free_pm_buffer(struct snd_emu10k1 *emu); 1862 void snd_emu10k1_efx_suspend(struct snd_emu10k1 *emu); 1863 void snd_emu10k1_efx_resume(struct snd_emu10k1 *emu); 1864 int snd_p16v_alloc_pm_buffer(struct snd_emu10k1 *emu); 1865 void snd_p16v_free_pm_buffer(struct snd_emu10k1 *emu); 1866 void snd_p16v_suspend(struct snd_emu10k1 *emu); 1867 void snd_p16v_resume(struct snd_emu10k1 *emu); 1868 #endif 1869 1870 /* memory allocation */ 1871 struct snd_util_memblk *snd_emu10k1_alloc_pages(struct snd_emu10k1 *emu, struct snd_pcm_substream *substream); 1872 int snd_emu10k1_free_pages(struct snd_emu10k1 *emu, struct snd_util_memblk *blk); 1873 int snd_emu10k1_alloc_pages_maybe_wider(struct snd_emu10k1 *emu, size_t size, 1874 struct snd_dma_buffer *dmab); 1875 struct snd_util_memblk *snd_emu10k1_synth_alloc(struct snd_emu10k1 *emu, unsigned int size); 1876 int snd_emu10k1_synth_free(struct snd_emu10k1 *emu, struct snd_util_memblk *blk); 1877 int snd_emu10k1_synth_bzero(struct snd_emu10k1 *emu, struct snd_util_memblk *blk, int offset, int size); 1878 int snd_emu10k1_synth_copy_from_user(struct snd_emu10k1 *emu, struct snd_util_memblk *blk, int offset, const char __user *data, int size); 1879 int snd_emu10k1_memblk_map(struct snd_emu10k1 *emu, struct snd_emu10k1_memblk *blk); 1880 1881 /* voice allocation */ 1882 int snd_emu10k1_voice_alloc(struct snd_emu10k1 *emu, int type, int count, int channels, 1883 struct snd_emu10k1_pcm *epcm, struct snd_emu10k1_voice **rvoice); 1884 int snd_emu10k1_voice_free(struct snd_emu10k1 *emu, struct snd_emu10k1_voice *pvoice); 1885 1886 /* MIDI uart */ 1887 int snd_emu10k1_midi(struct snd_emu10k1 * emu); 1888 int snd_emu10k1_audigy_midi(struct snd_emu10k1 * emu); 1889 1890 /* proc interface */ 1891 int snd_emu10k1_proc_init(struct snd_emu10k1 * emu); 1892 1893 /* fx8010 irq handler */ 1894 int snd_emu10k1_fx8010_register_irq_handler(struct snd_emu10k1 *emu, 1895 snd_fx8010_irq_handler_t *handler, 1896 unsigned char gpr_running, 1897 void *private_data, 1898 struct snd_emu10k1_fx8010_irq *irq); 1899 int snd_emu10k1_fx8010_unregister_irq_handler(struct snd_emu10k1 *emu, 1900 struct snd_emu10k1_fx8010_irq *irq); 1901 1902 #endif /* __SOUND_EMU10K1_H */ 1903