1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Definitions for CS4271 ASoC codec driver 4 * 5 * Copyright (c) 2010 Alexander Sverdlin <subaparts@yandex.ru> 6 */ 7 8 #ifndef __CS4271_H 9 #define __CS4271_H 10 11 struct cs4271_platform_data { 12 int gpio_nreset; /* GPIO driving Reset pin, if any */ 13 bool amutec_eq_bmutec; /* flag to enable AMUTEC=BMUTEC */ 14 15 /* 16 * The CS4271 requires its LRCLK and MCLK to be stable before its RESET 17 * line is de-asserted. That also means that clocks cannot be changed 18 * without putting the chip back into hardware reset, which also requires 19 * a complete re-initialization of all registers. 20 * 21 * One (undocumented) workaround is to assert and de-assert the PDN bit 22 * in the MODE2 register. This workaround can be enabled with the 23 * following flag. 24 * 25 * Note that this is not needed in case the clocks are stable 26 * throughout the entire runtime of the codec. 27 */ 28 bool enable_soft_reset; 29 }; 30 31 #endif /* __CS4271_H */ 32