1f545714eSKrzysztof Helt #ifndef __SOUND_CS4231_REGS_H 2f545714eSKrzysztof Helt #define __SOUND_CS4231_REGS_H 3f545714eSKrzysztof Helt 4f545714eSKrzysztof Helt /* 5f545714eSKrzysztof Helt * Copyright (c) by Jaroslav Kysela <perex@suse.cz> 6f545714eSKrzysztof Helt * Definitions for CS4231 & InterWave chips & compatible chips registers 7f545714eSKrzysztof Helt * 8f545714eSKrzysztof Helt * 9f545714eSKrzysztof Helt * This program is free software; you can redistribute it and/or modify 10f545714eSKrzysztof Helt * it under the terms of the GNU General Public License as published by 11f545714eSKrzysztof Helt * the Free Software Foundation; either version 2 of the License, or 12f545714eSKrzysztof Helt * (at your option) any later version. 13f545714eSKrzysztof Helt * 14f545714eSKrzysztof Helt * This program is distributed in the hope that it will be useful, 15f545714eSKrzysztof Helt * but WITHOUT ANY WARRANTY; without even the implied warranty of 16f545714eSKrzysztof Helt * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17f545714eSKrzysztof Helt * GNU General Public License for more details. 18f545714eSKrzysztof Helt * 19f545714eSKrzysztof Helt * You should have received a copy of the GNU General Public License 20f545714eSKrzysztof Helt * along with this program; if not, write to the Free Software 21f545714eSKrzysztof Helt * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 22f545714eSKrzysztof Helt * 23f545714eSKrzysztof Helt */ 24f545714eSKrzysztof Helt 25f545714eSKrzysztof Helt /* IO ports */ 26f545714eSKrzysztof Helt 27f545714eSKrzysztof Helt #define CS4231P(x) (c_d_c_CS4231##x) 28f545714eSKrzysztof Helt 29f545714eSKrzysztof Helt #define c_d_c_CS4231REGSEL 0 30f545714eSKrzysztof Helt #define c_d_c_CS4231REG 1 31f545714eSKrzysztof Helt #define c_d_c_CS4231STATUS 2 32f545714eSKrzysztof Helt #define c_d_c_CS4231PIO 3 33f545714eSKrzysztof Helt 34f545714eSKrzysztof Helt /* codec registers */ 35f545714eSKrzysztof Helt 36f545714eSKrzysztof Helt #define CS4231_LEFT_INPUT 0x00 /* left input control */ 37f545714eSKrzysztof Helt #define CS4231_RIGHT_INPUT 0x01 /* right input control */ 38f545714eSKrzysztof Helt #define CS4231_AUX1_LEFT_INPUT 0x02 /* left AUX1 input control */ 39f545714eSKrzysztof Helt #define CS4231_AUX1_RIGHT_INPUT 0x03 /* right AUX1 input control */ 40f545714eSKrzysztof Helt #define CS4231_AUX2_LEFT_INPUT 0x04 /* left AUX2 input control */ 41f545714eSKrzysztof Helt #define CS4231_AUX2_RIGHT_INPUT 0x05 /* right AUX2 input control */ 42f545714eSKrzysztof Helt #define CS4231_LEFT_OUTPUT 0x06 /* left output control register */ 43f545714eSKrzysztof Helt #define CS4231_RIGHT_OUTPUT 0x07 /* right output control register */ 44f545714eSKrzysztof Helt #define CS4231_PLAYBK_FORMAT 0x08 /* clock and data format - playback - bits 7-0 MCE */ 45f545714eSKrzysztof Helt #define CS4231_IFACE_CTRL 0x09 /* interface control - bits 7-2 MCE */ 46f545714eSKrzysztof Helt #define CS4231_PIN_CTRL 0x0a /* pin control */ 47f545714eSKrzysztof Helt #define CS4231_TEST_INIT 0x0b /* test and initialization */ 48f545714eSKrzysztof Helt #define CS4231_MISC_INFO 0x0c /* miscellaneaous information */ 49f545714eSKrzysztof Helt #define CS4231_LOOPBACK 0x0d /* loopback control */ 50f545714eSKrzysztof Helt #define CS4231_PLY_UPR_CNT 0x0e /* playback upper base count */ 51f545714eSKrzysztof Helt #define CS4231_PLY_LWR_CNT 0x0f /* playback lower base count */ 52f545714eSKrzysztof Helt #define CS4231_ALT_FEATURE_1 0x10 /* alternate #1 feature enable */ 53f545714eSKrzysztof Helt #define AD1845_AF1_MIC_LEFT 0x10 /* alternate #1 feature + MIC left */ 54f545714eSKrzysztof Helt #define CS4231_ALT_FEATURE_2 0x11 /* alternate #2 feature enable */ 55f545714eSKrzysztof Helt #define AD1845_AF2_MIC_RIGHT 0x11 /* alternate #2 feature + MIC right */ 56f545714eSKrzysztof Helt #define CS4231_LEFT_LINE_IN 0x12 /* left line input control */ 57f545714eSKrzysztof Helt #define CS4231_RIGHT_LINE_IN 0x13 /* right line input control */ 58f545714eSKrzysztof Helt #define CS4231_TIMER_LOW 0x14 /* timer low byte */ 59f545714eSKrzysztof Helt #define CS4231_TIMER_HIGH 0x15 /* timer high byte */ 60f545714eSKrzysztof Helt #define CS4231_LEFT_MIC_INPUT 0x16 /* left MIC input control register (InterWave only) */ 61f545714eSKrzysztof Helt #define AD1845_UPR_FREQ_SEL 0x16 /* upper byte of frequency select */ 62f545714eSKrzysztof Helt #define CS4231_RIGHT_MIC_INPUT 0x17 /* right MIC input control register (InterWave only) */ 63f545714eSKrzysztof Helt #define AD1845_LWR_FREQ_SEL 0x17 /* lower byte of frequency select */ 64f545714eSKrzysztof Helt #define CS4236_EXT_REG 0x17 /* extended register access */ 65f545714eSKrzysztof Helt #define CS4231_IRQ_STATUS 0x18 /* irq status register */ 66f545714eSKrzysztof Helt #define CS4231_LINE_LEFT_OUTPUT 0x19 /* left line output control register (InterWave only) */ 67f545714eSKrzysztof Helt #define CS4231_VERSION 0x19 /* CS4231(A) - version values */ 68f545714eSKrzysztof Helt #define CS4231_MONO_CTRL 0x1a /* mono input/output control */ 69f545714eSKrzysztof Helt #define CS4231_LINE_RIGHT_OUTPUT 0x1b /* right line output control register (InterWave only) */ 70f545714eSKrzysztof Helt #define AD1845_PWR_DOWN 0x1b /* power down control */ 71f545714eSKrzysztof Helt #define CS4235_LEFT_MASTER 0x1b /* left master output control */ 72f545714eSKrzysztof Helt #define CS4231_REC_FORMAT 0x1c /* clock and data format - record - bits 7-0 MCE */ 73f545714eSKrzysztof Helt #define CS4231_PLY_VAR_FREQ 0x1d /* playback variable frequency */ 74f545714eSKrzysztof Helt #define AD1845_CLOCK 0x1d /* crystal clock select and total power down */ 75f545714eSKrzysztof Helt #define CS4235_RIGHT_MASTER 0x1d /* right master output control */ 76f545714eSKrzysztof Helt #define CS4231_REC_UPR_CNT 0x1e /* record upper count */ 77f545714eSKrzysztof Helt #define CS4231_REC_LWR_CNT 0x1f /* record lower count */ 78f545714eSKrzysztof Helt 79f545714eSKrzysztof Helt /* definitions for codec register select port - CODECP( REGSEL ) */ 80f545714eSKrzysztof Helt 81f545714eSKrzysztof Helt #define CS4231_INIT 0x80 /* CODEC is initializing */ 82f545714eSKrzysztof Helt #define CS4231_MCE 0x40 /* mode change enable */ 83f545714eSKrzysztof Helt #define CS4231_TRD 0x20 /* transfer request disable */ 84f545714eSKrzysztof Helt 85f545714eSKrzysztof Helt /* definitions for codec status register - CODECP( STATUS ) */ 86f545714eSKrzysztof Helt 87f545714eSKrzysztof Helt #define CS4231_GLOBALIRQ 0x01 /* IRQ is active */ 88f545714eSKrzysztof Helt 89f545714eSKrzysztof Helt /* definitions for codec irq status */ 90f545714eSKrzysztof Helt 91f545714eSKrzysztof Helt #define CS4231_PLAYBACK_IRQ 0x10 92f545714eSKrzysztof Helt #define CS4231_RECORD_IRQ 0x20 93f545714eSKrzysztof Helt #define CS4231_TIMER_IRQ 0x40 94f545714eSKrzysztof Helt #define CS4231_ALL_IRQS 0x70 95f545714eSKrzysztof Helt #define CS4231_REC_UNDERRUN 0x08 96f545714eSKrzysztof Helt #define CS4231_REC_OVERRUN 0x04 97f545714eSKrzysztof Helt #define CS4231_PLY_OVERRUN 0x02 98f545714eSKrzysztof Helt #define CS4231_PLY_UNDERRUN 0x01 99f545714eSKrzysztof Helt 100f545714eSKrzysztof Helt /* definitions for CS4231_LEFT_INPUT and CS4231_RIGHT_INPUT registers */ 101f545714eSKrzysztof Helt 102f545714eSKrzysztof Helt #define CS4231_ENABLE_MIC_GAIN 0x20 103f545714eSKrzysztof Helt 104f545714eSKrzysztof Helt #define CS4231_MIXS_LINE 0x00 105f545714eSKrzysztof Helt #define CS4231_MIXS_AUX1 0x40 106f545714eSKrzysztof Helt #define CS4231_MIXS_MIC 0x80 107f545714eSKrzysztof Helt #define CS4231_MIXS_ALL 0xc0 108f545714eSKrzysztof Helt 109f545714eSKrzysztof Helt /* definitions for clock and data format register - CS4231_PLAYBK_FORMAT */ 110f545714eSKrzysztof Helt 111f545714eSKrzysztof Helt #define CS4231_LINEAR_8 0x00 /* 8-bit unsigned data */ 112f545714eSKrzysztof Helt #define CS4231_ALAW_8 0x60 /* 8-bit A-law companded */ 113f545714eSKrzysztof Helt #define CS4231_ULAW_8 0x20 /* 8-bit U-law companded */ 114f545714eSKrzysztof Helt #define CS4231_LINEAR_16 0x40 /* 16-bit twos complement data - little endian */ 115f545714eSKrzysztof Helt #define CS4231_LINEAR_16_BIG 0xc0 /* 16-bit twos complement data - big endian */ 116f545714eSKrzysztof Helt #define CS4231_ADPCM_16 0xa0 /* 16-bit ADPCM */ 117f545714eSKrzysztof Helt #define CS4231_STEREO 0x10 /* stereo mode */ 118f545714eSKrzysztof Helt /* bits 3-1 define frequency divisor */ 119f545714eSKrzysztof Helt #define CS4231_XTAL1 0x00 /* 24.576 crystal */ 120f545714eSKrzysztof Helt #define CS4231_XTAL2 0x01 /* 16.9344 crystal */ 121f545714eSKrzysztof Helt 122f545714eSKrzysztof Helt /* definitions for interface control register - CS4231_IFACE_CTRL */ 123f545714eSKrzysztof Helt 124f545714eSKrzysztof Helt #define CS4231_RECORD_PIO 0x80 /* record PIO enable */ 125f545714eSKrzysztof Helt #define CS4231_PLAYBACK_PIO 0x40 /* playback PIO enable */ 126f545714eSKrzysztof Helt #define CS4231_CALIB_MODE 0x18 /* calibration mode bits */ 127f545714eSKrzysztof Helt #define CS4231_AUTOCALIB 0x08 /* auto calibrate */ 128f545714eSKrzysztof Helt #define CS4231_SINGLE_DMA 0x04 /* use single DMA channel */ 129f545714eSKrzysztof Helt #define CS4231_RECORD_ENABLE 0x02 /* record enable */ 130f545714eSKrzysztof Helt #define CS4231_PLAYBACK_ENABLE 0x01 /* playback enable */ 131f545714eSKrzysztof Helt 132f545714eSKrzysztof Helt /* definitions for pin control register - CS4231_PIN_CTRL */ 133f545714eSKrzysztof Helt 134f545714eSKrzysztof Helt #define CS4231_IRQ_ENABLE 0x02 /* enable IRQ */ 135f545714eSKrzysztof Helt #define CS4231_XCTL1 0x40 /* external control #1 */ 136f545714eSKrzysztof Helt #define CS4231_XCTL0 0x80 /* external control #0 */ 137f545714eSKrzysztof Helt 138f545714eSKrzysztof Helt /* definitions for test and init register - CS4231_TEST_INIT */ 139f545714eSKrzysztof Helt 140f545714eSKrzysztof Helt #define CS4231_CALIB_IN_PROGRESS 0x20 /* auto calibrate in progress */ 141f545714eSKrzysztof Helt #define CS4231_DMA_REQUEST 0x10 /* DMA request in progress */ 142f545714eSKrzysztof Helt 143f545714eSKrzysztof Helt /* definitions for misc control register - CS4231_MISC_INFO */ 144f545714eSKrzysztof Helt 145f545714eSKrzysztof Helt #define CS4231_MODE2 0x40 /* MODE 2 */ 146f545714eSKrzysztof Helt #define CS4231_IW_MODE3 0x6c /* MODE 3 - InterWave enhanced mode */ 147f545714eSKrzysztof Helt #define CS4231_4236_MODE3 0xe0 /* MODE 3 - CS4236+ enhanced mode */ 148f545714eSKrzysztof Helt 149f545714eSKrzysztof Helt /* definitions for alternate feature 1 register - CS4231_ALT_FEATURE_1 */ 150f545714eSKrzysztof Helt 151f545714eSKrzysztof Helt #define CS4231_DACZ 0x01 /* zero DAC when underrun */ 152f545714eSKrzysztof Helt #define CS4231_TIMER_ENABLE 0x40 /* codec timer enable */ 153f545714eSKrzysztof Helt #define CS4231_OLB 0x80 /* output level bit */ 154f545714eSKrzysztof Helt 155f545714eSKrzysztof Helt /* definitions for Extended Registers - CS4236+ */ 156f545714eSKrzysztof Helt 157f545714eSKrzysztof Helt #define CS4236_REG(i23val) (((i23val << 2) & 0x10) | ((i23val >> 4) & 0x0f)) 158f545714eSKrzysztof Helt #define CS4236_I23VAL(reg) ((((reg)&0xf) << 4) | (((reg)&0x10) >> 2) | 0x8) 159f545714eSKrzysztof Helt 160f545714eSKrzysztof Helt #define CS4236_LEFT_LINE 0x08 /* left LINE alternate volume */ 161f545714eSKrzysztof Helt #define CS4236_RIGHT_LINE 0x18 /* right LINE alternate volume */ 162f545714eSKrzysztof Helt #define CS4236_LEFT_MIC 0x28 /* left MIC volume */ 163f545714eSKrzysztof Helt #define CS4236_RIGHT_MIC 0x38 /* right MIC volume */ 164f545714eSKrzysztof Helt #define CS4236_LEFT_MIX_CTRL 0x48 /* synthesis and left input mixer control */ 165f545714eSKrzysztof Helt #define CS4236_RIGHT_MIX_CTRL 0x58 /* right input mixer control */ 166f545714eSKrzysztof Helt #define CS4236_LEFT_FM 0x68 /* left FM volume */ 167f545714eSKrzysztof Helt #define CS4236_RIGHT_FM 0x78 /* right FM volume */ 168f545714eSKrzysztof Helt #define CS4236_LEFT_DSP 0x88 /* left DSP serial port volume */ 169f545714eSKrzysztof Helt #define CS4236_RIGHT_DSP 0x98 /* right DSP serial port volume */ 170f545714eSKrzysztof Helt #define CS4236_RIGHT_LOOPBACK 0xa8 /* right loopback monitor volume */ 171f545714eSKrzysztof Helt #define CS4236_DAC_MUTE 0xb8 /* DAC mute and IFSE enable */ 172f545714eSKrzysztof Helt #define CS4236_ADC_RATE 0xc8 /* indenpendent ADC sample frequency */ 173f545714eSKrzysztof Helt #define CS4236_DAC_RATE 0xd8 /* indenpendent DAC sample frequency */ 174f545714eSKrzysztof Helt #define CS4236_LEFT_MASTER 0xe8 /* left master digital audio volume */ 175f545714eSKrzysztof Helt #define CS4236_RIGHT_MASTER 0xf8 /* right master digital audio volume */ 176f545714eSKrzysztof Helt #define CS4236_LEFT_WAVE 0x0c /* left wavetable serial port volume */ 177f545714eSKrzysztof Helt #define CS4236_RIGHT_WAVE 0x1c /* right wavetable serial port volume */ 178f545714eSKrzysztof Helt #define CS4236_VERSION 0x9c /* chip version and ID */ 179f545714eSKrzysztof Helt 180f545714eSKrzysztof Helt #endif /* __SOUND_CS4231_REGS_H */ 181