142cfa276SPavel Hofman #ifndef __SOUND_AK4113_H 242cfa276SPavel Hofman #define __SOUND_AK4113_H 342cfa276SPavel Hofman 442cfa276SPavel Hofman /* 542cfa276SPavel Hofman * Routines for Asahi Kasei AK4113 642cfa276SPavel Hofman * Copyright (c) by Jaroslav Kysela <perex@perex.cz>, 742cfa276SPavel Hofman * Copyright (c) by Pavel Hofman <pavel.hofman@ivitera.com>, 842cfa276SPavel Hofman * 942cfa276SPavel Hofman * 1042cfa276SPavel Hofman * This program is free software; you can redistribute it and/or modify 1142cfa276SPavel Hofman * it under the terms of the GNU General Public License as published by 1242cfa276SPavel Hofman * the Free Software Foundation; either version 2 of the License, or 1342cfa276SPavel Hofman * (at your option) any later version. 1442cfa276SPavel Hofman * 1542cfa276SPavel Hofman * This program is distributed in the hope that it will be useful, 1642cfa276SPavel Hofman * but WITHOUT ANY WARRANTY; without even the implied warranty of 1742cfa276SPavel Hofman * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1842cfa276SPavel Hofman * GNU General Public License for more details. 1942cfa276SPavel Hofman * 2042cfa276SPavel Hofman * You should have received a copy of the GNU General Public License 2142cfa276SPavel Hofman * along with this program; if not, write to the Free Software 2242cfa276SPavel Hofman * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 2342cfa276SPavel Hofman * 2442cfa276SPavel Hofman */ 2542cfa276SPavel Hofman 2642cfa276SPavel Hofman /* AK4113 registers */ 2742cfa276SPavel Hofman /* power down */ 2842cfa276SPavel Hofman #define AK4113_REG_PWRDN 0x00 2942cfa276SPavel Hofman /* format control */ 3042cfa276SPavel Hofman #define AK4113_REG_FORMAT 0x01 3142cfa276SPavel Hofman /* input/output control */ 3242cfa276SPavel Hofman #define AK4113_REG_IO0 0x02 3342cfa276SPavel Hofman /* input/output control */ 3442cfa276SPavel Hofman #define AK4113_REG_IO1 0x03 3542cfa276SPavel Hofman /* interrupt0 mask */ 3642cfa276SPavel Hofman #define AK4113_REG_INT0_MASK 0x04 3742cfa276SPavel Hofman /* interrupt1 mask */ 3842cfa276SPavel Hofman #define AK4113_REG_INT1_MASK 0x05 3942cfa276SPavel Hofman /* DAT mask & DTS select */ 4042cfa276SPavel Hofman #define AK4113_REG_DATDTS 0x06 4142cfa276SPavel Hofman /* receiver status 0 */ 4242cfa276SPavel Hofman #define AK4113_REG_RCS0 0x07 4342cfa276SPavel Hofman /* receiver status 1 */ 4442cfa276SPavel Hofman #define AK4113_REG_RCS1 0x08 4542cfa276SPavel Hofman /* receiver status 2 */ 4642cfa276SPavel Hofman #define AK4113_REG_RCS2 0x09 4742cfa276SPavel Hofman /* RX channel status byte 0 */ 4842cfa276SPavel Hofman #define AK4113_REG_RXCSB0 0x0a 4942cfa276SPavel Hofman /* RX channel status byte 1 */ 5042cfa276SPavel Hofman #define AK4113_REG_RXCSB1 0x0b 5142cfa276SPavel Hofman /* RX channel status byte 2 */ 5242cfa276SPavel Hofman #define AK4113_REG_RXCSB2 0x0c 5342cfa276SPavel Hofman /* RX channel status byte 3 */ 5442cfa276SPavel Hofman #define AK4113_REG_RXCSB3 0x0d 5542cfa276SPavel Hofman /* RX channel status byte 4 */ 5642cfa276SPavel Hofman #define AK4113_REG_RXCSB4 0x0e 5742cfa276SPavel Hofman /* burst preamble Pc byte 0 */ 5842cfa276SPavel Hofman #define AK4113_REG_Pc0 0x0f 5942cfa276SPavel Hofman /* burst preamble Pc byte 1 */ 6042cfa276SPavel Hofman #define AK4113_REG_Pc1 0x10 6142cfa276SPavel Hofman /* burst preamble Pd byte 0 */ 6242cfa276SPavel Hofman #define AK4113_REG_Pd0 0x11 6342cfa276SPavel Hofman /* burst preamble Pd byte 1 */ 6442cfa276SPavel Hofman #define AK4113_REG_Pd1 0x12 6542cfa276SPavel Hofman /* Q-subcode address + control */ 6642cfa276SPavel Hofman #define AK4113_REG_QSUB_ADDR 0x13 6742cfa276SPavel Hofman /* Q-subcode track */ 6842cfa276SPavel Hofman #define AK4113_REG_QSUB_TRACK 0x14 6942cfa276SPavel Hofman /* Q-subcode index */ 7042cfa276SPavel Hofman #define AK4113_REG_QSUB_INDEX 0x15 7142cfa276SPavel Hofman /* Q-subcode minute */ 7242cfa276SPavel Hofman #define AK4113_REG_QSUB_MINUTE 0x16 7342cfa276SPavel Hofman /* Q-subcode second */ 7442cfa276SPavel Hofman #define AK4113_REG_QSUB_SECOND 0x17 7542cfa276SPavel Hofman /* Q-subcode frame */ 7642cfa276SPavel Hofman #define AK4113_REG_QSUB_FRAME 0x18 7742cfa276SPavel Hofman /* Q-subcode zero */ 7842cfa276SPavel Hofman #define AK4113_REG_QSUB_ZERO 0x19 7942cfa276SPavel Hofman /* Q-subcode absolute minute */ 8042cfa276SPavel Hofman #define AK4113_REG_QSUB_ABSMIN 0x1a 8142cfa276SPavel Hofman /* Q-subcode absolute second */ 8242cfa276SPavel Hofman #define AK4113_REG_QSUB_ABSSEC 0x1b 8342cfa276SPavel Hofman /* Q-subcode absolute frame */ 8442cfa276SPavel Hofman #define AK4113_REG_QSUB_ABSFRM 0x1c 8542cfa276SPavel Hofman 8642cfa276SPavel Hofman /* sizes */ 8742cfa276SPavel Hofman #define AK4113_REG_RXCSB_SIZE ((AK4113_REG_RXCSB4-AK4113_REG_RXCSB0)+1) 8842cfa276SPavel Hofman #define AK4113_REG_QSUB_SIZE ((AK4113_REG_QSUB_ABSFRM-AK4113_REG_QSUB_ADDR)\ 8942cfa276SPavel Hofman +1) 9042cfa276SPavel Hofman 9142cfa276SPavel Hofman #define AK4113_WRITABLE_REGS (AK4113_REG_DATDTS + 1) 9242cfa276SPavel Hofman 9342cfa276SPavel Hofman /* AK4113_REG_PWRDN bits */ 9442cfa276SPavel Hofman /* Channel Status Select */ 9542cfa276SPavel Hofman #define AK4113_CS12 (1<<7) 9642cfa276SPavel Hofman /* Block Start & C/U Output Mode */ 9742cfa276SPavel Hofman #define AK4113_BCU (1<<6) 9842cfa276SPavel Hofman /* Master Clock Operation Select */ 9942cfa276SPavel Hofman #define AK4113_CM1 (1<<5) 10042cfa276SPavel Hofman /* Master Clock Operation Select */ 10142cfa276SPavel Hofman #define AK4113_CM0 (1<<4) 10242cfa276SPavel Hofman /* Master Clock Frequency Select */ 10342cfa276SPavel Hofman #define AK4113_OCKS1 (1<<3) 10442cfa276SPavel Hofman /* Master Clock Frequency Select */ 10542cfa276SPavel Hofman #define AK4113_OCKS0 (1<<2) 10642cfa276SPavel Hofman /* 0 = power down, 1 = normal operation */ 10742cfa276SPavel Hofman #define AK4113_PWN (1<<1) 10842cfa276SPavel Hofman /* 0 = reset & initialize (except thisregister), 1 = normal operation */ 10942cfa276SPavel Hofman #define AK4113_RST (1<<0) 11042cfa276SPavel Hofman 11142cfa276SPavel Hofman /* AK4113_REQ_FORMAT bits */ 11242cfa276SPavel Hofman /* V/TX Output select: 0 = Validity Flag Output, 1 = TX */ 11342cfa276SPavel Hofman #define AK4113_VTX (1<<7) 11442cfa276SPavel Hofman /* Audio Data Control */ 11542cfa276SPavel Hofman #define AK4113_DIF2 (1<<6) 11642cfa276SPavel Hofman /* Audio Data Control */ 11742cfa276SPavel Hofman #define AK4113_DIF1 (1<<5) 11842cfa276SPavel Hofman /* Audio Data Control */ 11942cfa276SPavel Hofman #define AK4113_DIF0 (1<<4) 12042cfa276SPavel Hofman /* Deemphasis Autodetect Enable (1 = enable) */ 12142cfa276SPavel Hofman #define AK4113_DEAU (1<<3) 12242cfa276SPavel Hofman /* 32kHz-48kHz Deemphasis Control */ 12342cfa276SPavel Hofman #define AK4113_DEM1 (1<<2) 12442cfa276SPavel Hofman /* 32kHz-48kHz Deemphasis Control */ 12542cfa276SPavel Hofman #define AK4113_DEM0 (1<<1) 12642cfa276SPavel Hofman #define AK4113_DEM_OFF (AK4113_DEM0) 12742cfa276SPavel Hofman #define AK4113_DEM_44KHZ (0) 12842cfa276SPavel Hofman #define AK4113_DEM_48KHZ (AK4113_DEM1) 12942cfa276SPavel Hofman #define AK4113_DEM_32KHZ (AK4113_DEM0|AK4113_DEM1) 13042cfa276SPavel Hofman /* STDO: 16-bit, right justified */ 13142cfa276SPavel Hofman #define AK4113_DIF_16R (0) 13242cfa276SPavel Hofman /* STDO: 18-bit, right justified */ 13342cfa276SPavel Hofman #define AK4113_DIF_18R (AK4113_DIF0) 13442cfa276SPavel Hofman /* STDO: 20-bit, right justified */ 13542cfa276SPavel Hofman #define AK4113_DIF_20R (AK4113_DIF1) 13642cfa276SPavel Hofman /* STDO: 24-bit, right justified */ 13742cfa276SPavel Hofman #define AK4113_DIF_24R (AK4113_DIF1|AK4113_DIF0) 13842cfa276SPavel Hofman /* STDO: 24-bit, left justified */ 13942cfa276SPavel Hofman #define AK4113_DIF_24L (AK4113_DIF2) 14042cfa276SPavel Hofman /* STDO: I2S */ 14142cfa276SPavel Hofman #define AK4113_DIF_24I2S (AK4113_DIF2|AK4113_DIF0) 14242cfa276SPavel Hofman /* STDO: 24-bit, left justified; LRCLK, BICK = Input */ 14342cfa276SPavel Hofman #define AK4113_DIF_I24L (AK4113_DIF2|AK4113_DIF1) 14442cfa276SPavel Hofman /* STDO: I2S; LRCLK, BICK = Input */ 14542cfa276SPavel Hofman #define AK4113_DIF_I24I2S (AK4113_DIF2|AK4113_DIF1|AK4113_DIF0) 14642cfa276SPavel Hofman 14742cfa276SPavel Hofman /* AK4113_REG_IO0 */ 14842cfa276SPavel Hofman /* XTL1=0,XTL0=0 -> 11.2896Mhz; XTL1=0,XTL0=1 -> 12.288Mhz */ 14942cfa276SPavel Hofman #define AK4113_XTL1 (1<<6) 15042cfa276SPavel Hofman /* XTL1=1,XTL0=0 -> 24.576Mhz; XTL1=1,XTL0=1 -> use channel status */ 15142cfa276SPavel Hofman #define AK4113_XTL0 (1<<5) 15242cfa276SPavel Hofman /* Block Start Signal Output: 0 = U-bit, 1 = C-bit (req. BCU = 1) */ 15342cfa276SPavel Hofman #define AK4113_UCE (1<<4) 15442cfa276SPavel Hofman /* TX Output Enable (1 = enable) */ 15542cfa276SPavel Hofman #define AK4113_TXE (1<<3) 15642cfa276SPavel Hofman /* Output Through Data Selector for TX pin */ 15742cfa276SPavel Hofman #define AK4113_OPS2 (1<<2) 15842cfa276SPavel Hofman /* Output Through Data Selector for TX pin */ 15942cfa276SPavel Hofman #define AK4113_OPS1 (1<<1) 16042cfa276SPavel Hofman /* Output Through Data Selector for TX pin */ 16142cfa276SPavel Hofman #define AK4113_OPS0 (1<<0) 16242cfa276SPavel Hofman /* 11.2896 MHz ref. Xtal freq. */ 16342cfa276SPavel Hofman #define AK4113_XTL_11_2896M (0) 16442cfa276SPavel Hofman /* 12.288 MHz ref. Xtal freq. */ 16542cfa276SPavel Hofman #define AK4113_XTL_12_288M (AK4113_XTL0) 16642cfa276SPavel Hofman /* 24.576 MHz ref. Xtal freq. */ 16742cfa276SPavel Hofman #define AK4113_XTL_24_576M (AK4113_XTL1) 16842cfa276SPavel Hofman 16942cfa276SPavel Hofman /* AK4113_REG_IO1 */ 17042cfa276SPavel Hofman /* Interrupt 0 pin Hold */ 17142cfa276SPavel Hofman #define AK4113_EFH1 (1<<7) 17242cfa276SPavel Hofman /* Interrupt 0 pin Hold */ 17342cfa276SPavel Hofman #define AK4113_EFH0 (1<<6) 17442cfa276SPavel Hofman #define AK4113_EFH_512LRCLK (0) 17542cfa276SPavel Hofman #define AK4113_EFH_1024LRCLK (AK4113_EFH0) 17642cfa276SPavel Hofman #define AK4113_EFH_2048LRCLK (AK4113_EFH1) 17742cfa276SPavel Hofman #define AK4113_EFH_4096LRCLK (AK4113_EFH1|AK4113_EFH0) 17842cfa276SPavel Hofman /* PLL Lock Time: 0 = 384/fs, 1 = 1/fs */ 17942cfa276SPavel Hofman #define AK4113_FAST (1<<5) 18042cfa276SPavel Hofman /* MCKO2 Output Select: 0 = CMx/OCKSx, 1 = Xtal */ 18142cfa276SPavel Hofman #define AK4113_XMCK (1<<4) 18242cfa276SPavel Hofman /* MCKO2 Output Freq. Select: 0 = x1, 1 = x0.5 (req. XMCK = 1) */ 18342cfa276SPavel Hofman #define AK4113_DIV (1<<3) 18442cfa276SPavel Hofman /* Input Recovery Data Select */ 18542cfa276SPavel Hofman #define AK4113_IPS2 (1<<2) 18642cfa276SPavel Hofman /* Input Recovery Data Select */ 18742cfa276SPavel Hofman #define AK4113_IPS1 (1<<1) 18842cfa276SPavel Hofman /* Input Recovery Data Select */ 18942cfa276SPavel Hofman #define AK4113_IPS0 (1<<0) 19042cfa276SPavel Hofman #define AK4113_IPS(x) ((x)&7) 19142cfa276SPavel Hofman 19242cfa276SPavel Hofman /* AK4113_REG_INT0_MASK && AK4113_REG_INT1_MASK*/ 19342cfa276SPavel Hofman /* mask enable for QINT bit */ 19442cfa276SPavel Hofman #define AK4113_MQI (1<<7) 19542cfa276SPavel Hofman /* mask enable for AUTO bit */ 19642cfa276SPavel Hofman #define AK4113_MAUT (1<<6) 19742cfa276SPavel Hofman /* mask enable for CINT bit */ 19842cfa276SPavel Hofman #define AK4113_MCIT (1<<5) 19942cfa276SPavel Hofman /* mask enable for UNLOCK bit */ 20042cfa276SPavel Hofman #define AK4113_MULK (1<<4) 20142cfa276SPavel Hofman /* mask enable for V bit */ 20242cfa276SPavel Hofman #define AK4113_V (1<<3) 20342cfa276SPavel Hofman /* mask enable for STC bit */ 20442cfa276SPavel Hofman #define AK4113_STC (1<<2) 20542cfa276SPavel Hofman /* mask enable for AUDN bit */ 20642cfa276SPavel Hofman #define AK4113_MAN (1<<1) 20742cfa276SPavel Hofman /* mask enable for PAR bit */ 20842cfa276SPavel Hofman #define AK4113_MPR (1<<0) 20942cfa276SPavel Hofman 21042cfa276SPavel Hofman /* AK4113_REG_DATDTS */ 21142cfa276SPavel Hofman /* DAT Start ID Counter */ 21242cfa276SPavel Hofman #define AK4113_DCNT (1<<4) 21342cfa276SPavel Hofman /* DTS-CD 16-bit Sync Word Detect */ 21442cfa276SPavel Hofman #define AK4113_DTS16 (1<<3) 21542cfa276SPavel Hofman /* DTS-CD 14-bit Sync Word Detect */ 21642cfa276SPavel Hofman #define AK4113_DTS14 (1<<2) 21742cfa276SPavel Hofman /* mask enable for DAT bit (if 1, no INT1 effect */ 21842cfa276SPavel Hofman #define AK4113_MDAT1 (1<<1) 21942cfa276SPavel Hofman /* mask enable for DAT bit (if 1, no INT0 effect */ 22042cfa276SPavel Hofman #define AK4113_MDAT0 (1<<0) 22142cfa276SPavel Hofman 22242cfa276SPavel Hofman /* AK4113_REG_RCS0 */ 22342cfa276SPavel Hofman /* Q-subcode buffer interrupt, 0 = no change, 1 = changed */ 22442cfa276SPavel Hofman #define AK4113_QINT (1<<7) 22542cfa276SPavel Hofman /* Non-PCM or DTS stream auto detection, 0 = no detect, 1 = detect */ 22642cfa276SPavel Hofman #define AK4113_AUTO (1<<6) 22742cfa276SPavel Hofman /* channel status buffer interrupt, 0 = no change, 1 = change */ 22842cfa276SPavel Hofman #define AK4113_CINT (1<<5) 22942cfa276SPavel Hofman /* PLL lock status, 0 = lock, 1 = unlock */ 23042cfa276SPavel Hofman #define AK4113_UNLCK (1<<4) 23142cfa276SPavel Hofman /* Validity bit, 0 = valid, 1 = invalid */ 23242cfa276SPavel Hofman #define AK4113_V (1<<3) 23342cfa276SPavel Hofman /* sampling frequency or Pre-emphasis change, 0 = no detect, 1 = detect */ 23442cfa276SPavel Hofman #define AK4113_STC (1<<2) 23542cfa276SPavel Hofman /* audio bit output, 0 = audio, 1 = non-audio */ 23642cfa276SPavel Hofman #define AK4113_AUDION (1<<1) 23742cfa276SPavel Hofman /* parity error or biphase error status, 0 = no error, 1 = error */ 23842cfa276SPavel Hofman #define AK4113_PAR (1<<0) 23942cfa276SPavel Hofman 24042cfa276SPavel Hofman /* AK4113_REG_RCS1 */ 24142cfa276SPavel Hofman /* sampling frequency detection */ 24242cfa276SPavel Hofman #define AK4113_FS3 (1<<7) 24342cfa276SPavel Hofman #define AK4113_FS2 (1<<6) 24442cfa276SPavel Hofman #define AK4113_FS1 (1<<5) 24542cfa276SPavel Hofman #define AK4113_FS0 (1<<4) 24642cfa276SPavel Hofman /* Pre-emphasis detect, 0 = OFF, 1 = ON */ 24742cfa276SPavel Hofman #define AK4113_PEM (1<<3) 24842cfa276SPavel Hofman /* DAT Start ID Detect, 0 = no detect, 1 = detect */ 24942cfa276SPavel Hofman #define AK4113_DAT (1<<2) 25042cfa276SPavel Hofman /* DTS-CD bit audio stream detect, 0 = no detect, 1 = detect */ 25142cfa276SPavel Hofman #define AK4113_DTSCD (1<<1) 25242cfa276SPavel Hofman /* Non-PCM bit stream detection, 0 = no detect, 1 = detect */ 25342cfa276SPavel Hofman #define AK4113_NPCM (1<<0) 25442cfa276SPavel Hofman #define AK4113_FS_8000HZ (AK4113_FS3|AK4113_FS0) 25542cfa276SPavel Hofman #define AK4113_FS_11025HZ (AK4113_FS2|AK4113_FS0) 25642cfa276SPavel Hofman #define AK4113_FS_16000HZ (AK4113_FS2|AK4113_FS1|AK4113_FS0) 25742cfa276SPavel Hofman #define AK4113_FS_22050HZ (AK4113_FS2) 25842cfa276SPavel Hofman #define AK4113_FS_24000HZ (AK4113_FS2|AK4113_FS1) 25942cfa276SPavel Hofman #define AK4113_FS_32000HZ (AK4113_FS1|AK4113_FS0) 26042cfa276SPavel Hofman #define AK4113_FS_44100HZ (0) 26142cfa276SPavel Hofman #define AK4113_FS_48000HZ (AK4113_FS1) 26242cfa276SPavel Hofman #define AK4113_FS_64000HZ (AK4113_FS3|AK4113_FS1|AK4113_FS0) 26342cfa276SPavel Hofman #define AK4113_FS_88200HZ (AK4113_FS3) 26442cfa276SPavel Hofman #define AK4113_FS_96000HZ (AK4113_FS3|AK4113_FS1) 26542cfa276SPavel Hofman #define AK4113_FS_176400HZ (AK4113_FS3|AK4113_FS2) 26642cfa276SPavel Hofman #define AK4113_FS_192000HZ (AK4113_FS3|AK4113_FS2|AK4113_FS1) 26742cfa276SPavel Hofman 26842cfa276SPavel Hofman /* AK4113_REG_RCS2 */ 26942cfa276SPavel Hofman /* CRC for Q-subcode, 0 = no error, 1 = error */ 27042cfa276SPavel Hofman #define AK4113_QCRC (1<<1) 27142cfa276SPavel Hofman /* CRC for channel status, 0 = no error, 1 = error */ 27242cfa276SPavel Hofman #define AK4113_CCRC (1<<0) 27342cfa276SPavel Hofman 27442cfa276SPavel Hofman /* flags for snd_ak4113_check_rate_and_errors() */ 27542cfa276SPavel Hofman #define AK4113_CHECK_NO_STAT (1<<0) /* no statistics */ 27642cfa276SPavel Hofman #define AK4113_CHECK_NO_RATE (1<<1) /* no rate check */ 27742cfa276SPavel Hofman 27842cfa276SPavel Hofman #define AK4113_CONTROLS 13 27942cfa276SPavel Hofman 28042cfa276SPavel Hofman typedef void (ak4113_write_t)(void *private_data, unsigned char addr, 28142cfa276SPavel Hofman unsigned char data); 28242cfa276SPavel Hofman typedef unsigned char (ak4113_read_t)(void *private_data, unsigned char addr); 28342cfa276SPavel Hofman 284239480abSTakashi Iwai enum { 285239480abSTakashi Iwai AK4113_PARITY_ERRORS, 286239480abSTakashi Iwai AK4113_V_BIT_ERRORS, 287239480abSTakashi Iwai AK4113_QCRC_ERRORS, 288239480abSTakashi Iwai AK4113_CCRC_ERRORS, 289239480abSTakashi Iwai AK4113_NUM_ERRORS 290239480abSTakashi Iwai }; 291239480abSTakashi Iwai 29242cfa276SPavel Hofman struct ak4113 { 29342cfa276SPavel Hofman struct snd_card *card; 29442cfa276SPavel Hofman ak4113_write_t *write; 29542cfa276SPavel Hofman ak4113_read_t *read; 29642cfa276SPavel Hofman void *private_data; 2974161b450STakashi Iwai atomic_t wq_processing; 2981781e78cSTakashi Iwai struct mutex reinit_mutex; 29942cfa276SPavel Hofman spinlock_t lock; 30042cfa276SPavel Hofman unsigned char regmap[AK4113_WRITABLE_REGS]; 30142cfa276SPavel Hofman struct snd_kcontrol *kctls[AK4113_CONTROLS]; 30242cfa276SPavel Hofman struct snd_pcm_substream *substream; 303239480abSTakashi Iwai unsigned long errors[AK4113_NUM_ERRORS]; 30442cfa276SPavel Hofman unsigned char rcs0; 30542cfa276SPavel Hofman unsigned char rcs1; 30642cfa276SPavel Hofman unsigned char rcs2; 30742cfa276SPavel Hofman struct delayed_work work; 30842cfa276SPavel Hofman unsigned int check_flags; 30942cfa276SPavel Hofman void *change_callback_private; 31042cfa276SPavel Hofman void (*change_callback)(struct ak4113 *ak4113, unsigned char c0, 31142cfa276SPavel Hofman unsigned char c1); 31242cfa276SPavel Hofman }; 31342cfa276SPavel Hofman 31442cfa276SPavel Hofman int snd_ak4113_create(struct snd_card *card, ak4113_read_t *read, 31542cfa276SPavel Hofman ak4113_write_t *write, 316f11947c7SDan Carpenter const unsigned char *pgm, 31742cfa276SPavel Hofman void *private_data, struct ak4113 **r_ak4113); 31842cfa276SPavel Hofman void snd_ak4113_reg_write(struct ak4113 *ak4113, unsigned char reg, 31942cfa276SPavel Hofman unsigned char mask, unsigned char val); 32042cfa276SPavel Hofman void snd_ak4113_reinit(struct ak4113 *ak4113); 32142cfa276SPavel Hofman int snd_ak4113_build(struct ak4113 *ak4113, 32242cfa276SPavel Hofman struct snd_pcm_substream *capture_substream); 32342cfa276SPavel Hofman int snd_ak4113_external_rate(struct ak4113 *ak4113); 32442cfa276SPavel Hofman int snd_ak4113_check_rate_and_errors(struct ak4113 *ak4113, unsigned int flags); 32542cfa276SPavel Hofman 3261293617cSTakashi Iwai #ifdef CONFIG_PM 3271293617cSTakashi Iwai void snd_ak4113_suspend(struct ak4113 *chip); 3281293617cSTakashi Iwai void snd_ak4113_resume(struct ak4113 *chip); 3291293617cSTakashi Iwai #else 3301293617cSTakashi Iwai static inline void snd_ak4113_suspend(struct ak4113 *chip) {} 3311293617cSTakashi Iwai static inline void snd_ak4113_resume(struct ak4113 *chip) {} 3321293617cSTakashi Iwai #endif 3331293617cSTakashi Iwai 33442cfa276SPavel Hofman #endif /* __SOUND_AK4113_H */ 33542cfa276SPavel Hofman 336