1 #ifndef __SOUND_AC97_CODEC_H 2 #define __SOUND_AC97_CODEC_H 3 4 /* 5 * Copyright (c) by Jaroslav Kysela <perex@suse.cz> 6 * Universal interface for Audio Codec '97 7 * 8 * For more details look to AC '97 component specification revision 2.1 9 * by Intel Corporation (http://developer.intel.com). 10 * 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2 of the License, or 15 * (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 25 * 26 */ 27 28 #include <linux/bitops.h> 29 #include "pcm.h" 30 #include "control.h" 31 #include "info.h" 32 33 /* 34 * AC'97 codec registers 35 */ 36 37 #define AC97_RESET 0x00 /* Reset */ 38 #define AC97_MASTER 0x02 /* Master Volume */ 39 #define AC97_HEADPHONE 0x04 /* Headphone Volume (optional) */ 40 #define AC97_MASTER_MONO 0x06 /* Master Volume Mono (optional) */ 41 #define AC97_MASTER_TONE 0x08 /* Master Tone (Bass & Treble) (optional) */ 42 #define AC97_PC_BEEP 0x0a /* PC Beep Volume (optinal) */ 43 #define AC97_PHONE 0x0c /* Phone Volume (optional) */ 44 #define AC97_MIC 0x0e /* MIC Volume */ 45 #define AC97_LINE 0x10 /* Line In Volume */ 46 #define AC97_CD 0x12 /* CD Volume */ 47 #define AC97_VIDEO 0x14 /* Video Volume (optional) */ 48 #define AC97_AUX 0x16 /* AUX Volume (optional) */ 49 #define AC97_PCM 0x18 /* PCM Volume */ 50 #define AC97_REC_SEL 0x1a /* Record Select */ 51 #define AC97_REC_GAIN 0x1c /* Record Gain */ 52 #define AC97_REC_GAIN_MIC 0x1e /* Record Gain MIC (optional) */ 53 #define AC97_GENERAL_PURPOSE 0x20 /* General Purpose (optional) */ 54 #define AC97_3D_CONTROL 0x22 /* 3D Control (optional) */ 55 #define AC97_INT_PAGING 0x24 /* Audio Interrupt & Paging (AC'97 2.3) */ 56 #define AC97_POWERDOWN 0x26 /* Powerdown control / status */ 57 /* range 0x28-0x3a - AUDIO AC'97 2.0 extensions */ 58 #define AC97_EXTENDED_ID 0x28 /* Extended Audio ID */ 59 #define AC97_EXTENDED_STATUS 0x2a /* Extended Audio Status and Control */ 60 #define AC97_PCM_FRONT_DAC_RATE 0x2c /* PCM Front DAC Rate */ 61 #define AC97_PCM_SURR_DAC_RATE 0x2e /* PCM Surround DAC Rate */ 62 #define AC97_PCM_LFE_DAC_RATE 0x30 /* PCM LFE DAC Rate */ 63 #define AC97_PCM_LR_ADC_RATE 0x32 /* PCM LR ADC Rate */ 64 #define AC97_PCM_MIC_ADC_RATE 0x34 /* PCM MIC ADC Rate */ 65 #define AC97_CENTER_LFE_MASTER 0x36 /* Center + LFE Master Volume */ 66 #define AC97_SURROUND_MASTER 0x38 /* Surround (Rear) Master Volume */ 67 #define AC97_SPDIF 0x3a /* S/PDIF control */ 68 /* range 0x3c-0x58 - MODEM */ 69 #define AC97_EXTENDED_MID 0x3c /* Extended Modem ID */ 70 #define AC97_EXTENDED_MSTATUS 0x3e /* Extended Modem Status and Control */ 71 #define AC97_LINE1_RATE 0x40 /* Line1 DAC/ADC Rate */ 72 #define AC97_LINE2_RATE 0x42 /* Line2 DAC/ADC Rate */ 73 #define AC97_HANDSET_RATE 0x44 /* Handset DAC/ADC Rate */ 74 #define AC97_LINE1_LEVEL 0x46 /* Line1 DAC/ADC Level */ 75 #define AC97_LINE2_LEVEL 0x48 /* Line2 DAC/ADC Level */ 76 #define AC97_HANDSET_LEVEL 0x4a /* Handset DAC/ADC Level */ 77 #define AC97_GPIO_CFG 0x4c /* GPIO Configuration */ 78 #define AC97_GPIO_POLARITY 0x4e /* GPIO Pin Polarity/Type, 0=low, 1=high active */ 79 #define AC97_GPIO_STICKY 0x50 /* GPIO Pin Sticky, 0=not, 1=sticky */ 80 #define AC97_GPIO_WAKEUP 0x52 /* GPIO Pin Wakeup, 0=no int, 1=yes int */ 81 #define AC97_GPIO_STATUS 0x54 /* GPIO Pin Status, slot 12 */ 82 #define AC97_MISC_AFE 0x56 /* Miscellaneous Modem AFE Status and Control */ 83 /* range 0x5a-0x7b - Vendor Specific */ 84 #define AC97_VENDOR_ID1 0x7c /* Vendor ID1 */ 85 #define AC97_VENDOR_ID2 0x7e /* Vendor ID2 / revision */ 86 /* range 0x60-0x6f (page 1) - extended codec registers */ 87 #define AC97_CODEC_CLASS_REV 0x60 /* Codec Class/Revision */ 88 #define AC97_PCI_SVID 0x62 /* PCI Subsystem Vendor ID */ 89 #define AC97_PCI_SID 0x64 /* PCI Subsystem ID */ 90 #define AC97_FUNC_SELECT 0x66 /* Function Select */ 91 #define AC97_FUNC_INFO 0x68 /* Function Information */ 92 #define AC97_SENSE_INFO 0x6a /* Sense Details */ 93 94 /* slot allocation */ 95 #define AC97_SLOT_TAG 0 96 #define AC97_SLOT_CMD_ADDR 1 97 #define AC97_SLOT_CMD_DATA 2 98 #define AC97_SLOT_PCM_LEFT 3 99 #define AC97_SLOT_PCM_RIGHT 4 100 #define AC97_SLOT_MODEM_LINE1 5 101 #define AC97_SLOT_PCM_CENTER 6 102 #define AC97_SLOT_MIC 6 /* input */ 103 #define AC97_SLOT_SPDIF_LEFT1 6 104 #define AC97_SLOT_PCM_SLEFT 7 /* surround left */ 105 #define AC97_SLOT_PCM_LEFT_0 7 /* double rate operation */ 106 #define AC97_SLOT_SPDIF_LEFT 7 107 #define AC97_SLOT_PCM_SRIGHT 8 /* surround right */ 108 #define AC97_SLOT_PCM_RIGHT_0 8 /* double rate operation */ 109 #define AC97_SLOT_SPDIF_RIGHT 8 110 #define AC97_SLOT_LFE 9 111 #define AC97_SLOT_SPDIF_RIGHT1 9 112 #define AC97_SLOT_MODEM_LINE2 10 113 #define AC97_SLOT_PCM_LEFT_1 10 /* double rate operation */ 114 #define AC97_SLOT_SPDIF_LEFT2 10 115 #define AC97_SLOT_HANDSET 11 /* output */ 116 #define AC97_SLOT_PCM_RIGHT_1 11 /* double rate operation */ 117 #define AC97_SLOT_SPDIF_RIGHT2 11 118 #define AC97_SLOT_MODEM_GPIO 12 /* modem GPIO */ 119 #define AC97_SLOT_PCM_CENTER_1 12 /* double rate operation */ 120 121 /* basic capabilities (reset register) */ 122 #define AC97_BC_DEDICATED_MIC 0x0001 /* Dedicated Mic PCM In Channel */ 123 #define AC97_BC_RESERVED1 0x0002 /* Reserved (was Modem Line Codec support) */ 124 #define AC97_BC_BASS_TREBLE 0x0004 /* Bass & Treble Control */ 125 #define AC97_BC_SIM_STEREO 0x0008 /* Simulated stereo */ 126 #define AC97_BC_HEADPHONE 0x0010 /* Headphone Out Support */ 127 #define AC97_BC_LOUDNESS 0x0020 /* Loudness (bass boost) Support */ 128 #define AC97_BC_16BIT_DAC 0x0000 /* 16-bit DAC resolution */ 129 #define AC97_BC_18BIT_DAC 0x0040 /* 18-bit DAC resolution */ 130 #define AC97_BC_20BIT_DAC 0x0080 /* 20-bit DAC resolution */ 131 #define AC97_BC_DAC_MASK 0x00c0 132 #define AC97_BC_16BIT_ADC 0x0000 /* 16-bit ADC resolution */ 133 #define AC97_BC_18BIT_ADC 0x0100 /* 18-bit ADC resolution */ 134 #define AC97_BC_20BIT_ADC 0x0200 /* 20-bit ADC resolution */ 135 #define AC97_BC_ADC_MASK 0x0300 136 137 /* general purpose */ 138 #define AC97_GP_DRSS_MASK 0x0c00 /* double rate slot select */ 139 #define AC97_GP_DRSS_1011 0x0000 /* LR(C) 10+11(+12) */ 140 #define AC97_GP_DRSS_78 0x0400 /* LR 7+8 */ 141 142 /* extended audio ID bit defines */ 143 #define AC97_EI_VRA 0x0001 /* Variable bit rate supported */ 144 #define AC97_EI_DRA 0x0002 /* Double rate supported */ 145 #define AC97_EI_SPDIF 0x0004 /* S/PDIF out supported */ 146 #define AC97_EI_VRM 0x0008 /* Variable bit rate supported for MIC */ 147 #define AC97_EI_DACS_SLOT_MASK 0x0030 /* DACs slot assignment */ 148 #define AC97_EI_DACS_SLOT_SHIFT 4 149 #define AC97_EI_CDAC 0x0040 /* PCM Center DAC available */ 150 #define AC97_EI_SDAC 0x0080 /* PCM Surround DACs available */ 151 #define AC97_EI_LDAC 0x0100 /* PCM LFE DAC available */ 152 #define AC97_EI_AMAP 0x0200 /* indicates optional slot/DAC mapping based on codec ID */ 153 #define AC97_EI_REV_MASK 0x0c00 /* AC'97 revision mask */ 154 #define AC97_EI_REV_22 0x0400 /* AC'97 revision 2.2 */ 155 #define AC97_EI_REV_23 0x0800 /* AC'97 revision 2.3 */ 156 #define AC97_EI_REV_SHIFT 10 157 #define AC97_EI_ADDR_MASK 0xc000 /* physical codec ID (address) */ 158 #define AC97_EI_ADDR_SHIFT 14 159 160 /* extended audio status and control bit defines */ 161 #define AC97_EA_VRA 0x0001 /* Variable bit rate enable bit */ 162 #define AC97_EA_DRA 0x0002 /* Double-rate audio enable bit */ 163 #define AC97_EA_SPDIF 0x0004 /* S/PDIF out enable bit */ 164 #define AC97_EA_VRM 0x0008 /* Variable bit rate for MIC enable bit */ 165 #define AC97_EA_SPSA_SLOT_MASK 0x0030 /* Mask for slot assignment bits */ 166 #define AC97_EA_SPSA_SLOT_SHIFT 4 167 #define AC97_EA_SPSA_3_4 0x0000 /* Slot assigned to 3 & 4 */ 168 #define AC97_EA_SPSA_7_8 0x0010 /* Slot assigned to 7 & 8 */ 169 #define AC97_EA_SPSA_6_9 0x0020 /* Slot assigned to 6 & 9 */ 170 #define AC97_EA_SPSA_10_11 0x0030 /* Slot assigned to 10 & 11 */ 171 #define AC97_EA_CDAC 0x0040 /* PCM Center DAC is ready (Read only) */ 172 #define AC97_EA_SDAC 0x0080 /* PCM Surround DACs are ready (Read only) */ 173 #define AC97_EA_LDAC 0x0100 /* PCM LFE DAC is ready (Read only) */ 174 #define AC97_EA_MDAC 0x0200 /* MIC ADC is ready (Read only) */ 175 #define AC97_EA_SPCV 0x0400 /* S/PDIF configuration valid (Read only) */ 176 #define AC97_EA_PRI 0x0800 /* Turns the PCM Center DAC off */ 177 #define AC97_EA_PRJ 0x1000 /* Turns the PCM Surround DACs off */ 178 #define AC97_EA_PRK 0x2000 /* Turns the PCM LFE DAC off */ 179 #define AC97_EA_PRL 0x4000 /* Turns the MIC ADC off */ 180 181 /* S/PDIF control bit defines */ 182 #define AC97_SC_PRO 0x0001 /* Professional status */ 183 #define AC97_SC_NAUDIO 0x0002 /* Non audio stream */ 184 #define AC97_SC_COPY 0x0004 /* Copyright status */ 185 #define AC97_SC_PRE 0x0008 /* Preemphasis status */ 186 #define AC97_SC_CC_MASK 0x07f0 /* Category Code mask */ 187 #define AC97_SC_CC_SHIFT 4 188 #define AC97_SC_L 0x0800 /* Generation Level status */ 189 #define AC97_SC_SPSR_MASK 0x3000 /* S/PDIF Sample Rate bits */ 190 #define AC97_SC_SPSR_SHIFT 12 191 #define AC97_SC_SPSR_44K 0x0000 /* Use 44.1kHz Sample rate */ 192 #define AC97_SC_SPSR_48K 0x2000 /* Use 48kHz Sample rate */ 193 #define AC97_SC_SPSR_32K 0x3000 /* Use 32kHz Sample rate */ 194 #define AC97_SC_DRS 0x4000 /* Double Rate S/PDIF */ 195 #define AC97_SC_V 0x8000 /* Validity status */ 196 197 /* Interrupt and Paging bit defines (AC'97 2.3) */ 198 #define AC97_PAGE_MASK 0x000f /* Page Selector */ 199 #define AC97_PAGE_VENDOR 0 /* Vendor-specific registers */ 200 #define AC97_PAGE_1 1 /* Extended Codec Registers page 1 */ 201 #define AC97_INT_ENABLE 0x0800 /* Interrupt Enable */ 202 #define AC97_INT_SENSE 0x1000 /* Sense Cycle */ 203 #define AC97_INT_CAUSE_SENSE 0x2000 /* Sense Cycle Completed (RO) */ 204 #define AC97_INT_CAUSE_GPIO 0x4000 /* GPIO bits changed (RO) */ 205 #define AC97_INT_STATUS 0x8000 /* Interrupt Status */ 206 207 /* extended modem ID bit defines */ 208 #define AC97_MEI_LINE1 0x0001 /* Line1 present */ 209 #define AC97_MEI_LINE2 0x0002 /* Line2 present */ 210 #define AC97_MEI_HANDSET 0x0004 /* Handset present */ 211 #define AC97_MEI_CID1 0x0008 /* caller ID decode for Line1 is supported */ 212 #define AC97_MEI_CID2 0x0010 /* caller ID decode for Line2 is supported */ 213 #define AC97_MEI_ADDR_MASK 0xc000 /* physical codec ID (address) */ 214 #define AC97_MEI_ADDR_SHIFT 14 215 216 /* extended modem status and control bit defines */ 217 #define AC97_MEA_GPIO 0x0001 /* GPIO is ready (ro) */ 218 #define AC97_MEA_MREF 0x0002 /* Vref is up to nominal level (ro) */ 219 #define AC97_MEA_ADC1 0x0004 /* ADC1 operational (ro) */ 220 #define AC97_MEA_DAC1 0x0008 /* DAC1 operational (ro) */ 221 #define AC97_MEA_ADC2 0x0010 /* ADC2 operational (ro) */ 222 #define AC97_MEA_DAC2 0x0020 /* DAC2 operational (ro) */ 223 #define AC97_MEA_HADC 0x0040 /* HADC operational (ro) */ 224 #define AC97_MEA_HDAC 0x0080 /* HDAC operational (ro) */ 225 #define AC97_MEA_PRA 0x0100 /* GPIO power down (high) */ 226 #define AC97_MEA_PRB 0x0200 /* reserved */ 227 #define AC97_MEA_PRC 0x0400 /* ADC1 power down (high) */ 228 #define AC97_MEA_PRD 0x0800 /* DAC1 power down (high) */ 229 #define AC97_MEA_PRE 0x1000 /* ADC2 power down (high) */ 230 #define AC97_MEA_PRF 0x2000 /* DAC2 power down (high) */ 231 #define AC97_MEA_PRG 0x4000 /* HADC power down (high) */ 232 #define AC97_MEA_PRH 0x8000 /* HDAC power down (high) */ 233 234 /* modem gpio status defines */ 235 #define AC97_GPIO_LINE1_OH 0x0001 /* Off Hook Line1 */ 236 #define AC97_GPIO_LINE1_RI 0x0002 /* Ring Detect Line1 */ 237 #define AC97_GPIO_LINE1_CID 0x0004 /* Caller ID path enable Line1 */ 238 #define AC97_GPIO_LINE1_LCS 0x0008 /* Loop Current Sense Line1 */ 239 #define AC97_GPIO_LINE1_PULSE 0x0010 /* Opt./ Pulse Dial Line1 (out) */ 240 #define AC97_GPIO_LINE1_HL1R 0x0020 /* Opt./ Handset to Line1 relay control (out) */ 241 #define AC97_GPIO_LINE1_HOHD 0x0040 /* Opt./ Handset off hook detect Line1 (in) */ 242 #define AC97_GPIO_LINE12_AC 0x0080 /* Opt./ Int.bit 1 / Line1/2 AC (out) */ 243 #define AC97_GPIO_LINE12_DC 0x0100 /* Opt./ Int.bit 2 / Line1/2 DC (out) */ 244 #define AC97_GPIO_LINE12_RS 0x0200 /* Opt./ Int.bit 3 / Line1/2 RS (out) */ 245 #define AC97_GPIO_LINE2_OH 0x0400 /* Off Hook Line2 */ 246 #define AC97_GPIO_LINE2_RI 0x0800 /* Ring Detect Line2 */ 247 #define AC97_GPIO_LINE2_CID 0x1000 /* Caller ID path enable Line2 */ 248 #define AC97_GPIO_LINE2_LCS 0x2000 /* Loop Current Sense Line2 */ 249 #define AC97_GPIO_LINE2_PULSE 0x4000 /* Opt./ Pulse Dial Line2 (out) */ 250 #define AC97_GPIO_LINE2_HL1R 0x8000 /* Opt./ Handset to Line2 relay control (out) */ 251 252 /* specific - SigmaTel */ 253 #define AC97_SIGMATEL_OUTSEL 0x64 /* Output Select, STAC9758 */ 254 #define AC97_SIGMATEL_INSEL 0x66 /* Input Select, STAC9758 */ 255 #define AC97_SIGMATEL_IOMISC 0x68 /* STAC9758 */ 256 #define AC97_SIGMATEL_ANALOG 0x6c /* Analog Special */ 257 #define AC97_SIGMATEL_DAC2INVERT 0x6e 258 #define AC97_SIGMATEL_BIAS1 0x70 259 #define AC97_SIGMATEL_BIAS2 0x72 260 #define AC97_SIGMATEL_VARIOUS 0x72 /* STAC9758 */ 261 #define AC97_SIGMATEL_MULTICHN 0x74 /* Multi-Channel programming */ 262 #define AC97_SIGMATEL_CIC1 0x76 263 #define AC97_SIGMATEL_CIC2 0x78 264 265 /* specific - Analog Devices */ 266 #define AC97_AD_TEST 0x5a /* test register */ 267 #define AC97_AD_CODEC_CFG 0x70 /* codec configuration */ 268 #define AC97_AD_JACK_SPDIF 0x72 /* Jack Sense & S/PDIF */ 269 #define AC97_AD_SERIAL_CFG 0x74 /* Serial Configuration */ 270 #define AC97_AD_MISC 0x76 /* Misc Control Bits */ 271 272 /* specific - Cirrus Logic */ 273 #define AC97_CSR_ACMODE 0x5e /* AC Mode Register */ 274 #define AC97_CSR_MISC_CRYSTAL 0x60 /* Misc Crystal Control */ 275 #define AC97_CSR_SPDIF 0x68 /* S/PDIF Register */ 276 #define AC97_CSR_SERIAL 0x6a /* Serial Port Control */ 277 #define AC97_CSR_SPECF_ADDR 0x6c /* Special Feature Address */ 278 #define AC97_CSR_SPECF_DATA 0x6e /* Special Feature Data */ 279 #define AC97_CSR_BDI_STATUS 0x7a /* BDI Status */ 280 281 /* specific - Conexant */ 282 #define AC97_CXR_AUDIO_MISC 0x5c 283 #define AC97_CXR_SPDIFEN (1<<3) 284 #define AC97_CXR_COPYRGT (1<<2) 285 #define AC97_CXR_SPDIF_MASK (3<<0) 286 #define AC97_CXR_SPDIF_PCM 0x0 287 #define AC97_CXR_SPDIF_AC3 0x2 288 289 /* specific - ALC */ 290 #define AC97_ALC650_SPDIF_INPUT_STATUS1 0x60 291 /* S/PDIF input status 1 bit defines */ 292 #define AC97_ALC650_PRO 0x0001 /* Professional status */ 293 #define AC97_ALC650_NAUDIO 0x0002 /* Non audio stream */ 294 #define AC97_ALC650_COPY 0x0004 /* Copyright status */ 295 #define AC97_ALC650_PRE 0x0038 /* Preemphasis status */ 296 #define AC97_ALC650_PRE_SHIFT 3 297 #define AC97_ALC650_MODE 0x00C0 /* Preemphasis status */ 298 #define AC97_ALC650_MODE_SHIFT 6 299 #define AC97_ALC650_CC_MASK 0x7f00 /* Category Code mask */ 300 #define AC97_ALC650_CC_SHIFT 8 301 #define AC97_ALC650_L 0x8000 /* Generation Level status */ 302 303 #define AC97_ALC650_SPDIF_INPUT_STATUS2 0x62 304 /* S/PDIF input status 2 bit defines */ 305 #define AC97_ALC650_SOUCE_MASK 0x000f /* Source number */ 306 #define AC97_ALC650_CHANNEL_MASK 0x00f0 /* Channel number */ 307 #define AC97_ALC650_CHANNEL_SHIFT 4 308 #define AC97_ALC650_SPSR_MASK 0x0f00 /* S/PDIF Sample Rate bits */ 309 #define AC97_ALC650_SPSR_SHIFT 8 310 #define AC97_ALC650_SPSR_44K 0x0000 /* Use 44.1kHz Sample rate */ 311 #define AC97_ALC650_SPSR_48K 0x0200 /* Use 48kHz Sample rate */ 312 #define AC97_ALC650_SPSR_32K 0x0300 /* Use 32kHz Sample rate */ 313 #define AC97_ALC650_CLOCK_ACCURACY 0x3000 /* Clock accuracy */ 314 #define AC97_ALC650_CLOCK_SHIFT 12 315 #define AC97_ALC650_CLOCK_LOCK 0x4000 /* Clock locked status */ 316 #define AC97_ALC650_V 0x8000 /* Validity status */ 317 318 #define AC97_ALC650_SURR_DAC_VOL 0x64 319 #define AC97_ALC650_LFE_DAC_VOL 0x66 320 #define AC97_ALC650_UNKNOWN1 0x68 321 #define AC97_ALC650_MULTICH 0x6a 322 #define AC97_ALC650_UNKNOWN2 0x6c 323 #define AC97_ALC650_REVISION 0x6e 324 #define AC97_ALC650_UNKNOWN3 0x70 325 #define AC97_ALC650_UNKNOWN4 0x72 326 #define AC97_ALC650_MISC 0x74 327 #define AC97_ALC650_GPIO_SETUP 0x76 328 #define AC97_ALC650_GPIO_STATUS 0x78 329 #define AC97_ALC650_CLOCK 0x7a 330 331 /* specific - Yamaha YMF753 */ 332 #define AC97_YMF753_DIT_CTRL2 0x66 /* DIT Control 2 */ 333 #define AC97_YMF753_3D_MODE_SEL 0x68 /* 3D Mode Select */ 334 335 /* specific - C-Media */ 336 #define AC97_CM9738_VENDOR_CTRL 0x5a 337 #define AC97_CM9739_MULTI_CHAN 0x64 338 #define AC97_CM9739_SPDIF_IN_STATUS 0x68 /* 32bit */ 339 #define AC97_CM9739_SPDIF_CTRL 0x6c 340 341 /* specific - wolfson */ 342 #define AC97_WM97XX_FMIXER_VOL 0x72 343 #define AC97_WM9704_RMIXER_VOL 0x74 344 #define AC97_WM9704_TEST 0x5a 345 #define AC97_WM9704_RPCM_VOL 0x70 346 #define AC97_WM9711_OUT3VOL 0x16 347 348 349 /* ac97->scaps */ 350 #define AC97_SCAP_AUDIO (1<<0) /* audio codec 97 */ 351 #define AC97_SCAP_MODEM (1<<1) /* modem codec 97 */ 352 #define AC97_SCAP_SURROUND_DAC (1<<2) /* surround L&R DACs are present */ 353 #define AC97_SCAP_CENTER_LFE_DAC (1<<3) /* center and LFE DACs are present */ 354 #define AC97_SCAP_SKIP_AUDIO (1<<4) /* skip audio part of codec */ 355 #define AC97_SCAP_SKIP_MODEM (1<<5) /* skip modem part of codec */ 356 #define AC97_SCAP_INDEP_SDIN (1<<6) /* independent SDIN */ 357 #define AC97_SCAP_INV_EAPD (1<<7) /* inverted EAPD */ 358 #define AC97_SCAP_DETECT_BY_VENDOR (1<<8) /* use vendor registers for read tests */ 359 #define AC97_SCAP_NO_SPDIF (1<<9) /* don't build SPDIF controls */ 360 361 /* ac97->flags */ 362 #define AC97_HAS_PC_BEEP (1<<0) /* force PC Speaker usage */ 363 #define AC97_AD_MULTI (1<<1) /* Analog Devices - multi codecs */ 364 #define AC97_CS_SPDIF (1<<2) /* Cirrus Logic uses funky SPDIF */ 365 #define AC97_CX_SPDIF (1<<3) /* Conexant's spdif interface */ 366 #define AC97_STEREO_MUTES (1<<4) /* has stereo mute bits */ 367 #define AC97_DOUBLE_RATE (1<<5) /* supports double rate playback */ 368 #define AC97_HAS_NO_MASTER_VOL (1<<6) /* no Master volume */ 369 #define AC97_HAS_NO_PCM_VOL (1<<7) /* no PCM volume */ 370 #define AC97_DEFAULT_POWER_OFF (1<<8) /* no RESET write */ 371 #define AC97_MODEM_PATCH (1<<9) /* modem patch */ 372 #define AC97_HAS_NO_REC_GAIN (1<<10) /* no Record gain */ 373 #define AC97_HAS_NO_PHONE (1<<11) /* no PHONE volume */ 374 #define AC97_HAS_NO_PC_BEEP (1<<12) /* no PC Beep volume */ 375 #define AC97_HAS_NO_VIDEO (1<<13) /* no Video volume */ 376 #define AC97_HAS_NO_CD (1<<14) /* no CD volume */ 377 378 /* rates indexes */ 379 #define AC97_RATES_FRONT_DAC 0 380 #define AC97_RATES_SURR_DAC 1 381 #define AC97_RATES_LFE_DAC 2 382 #define AC97_RATES_ADC 3 383 #define AC97_RATES_MIC_ADC 4 384 #define AC97_RATES_SPDIF 5 385 386 /* shared controllers */ 387 enum { 388 AC97_SHARED_TYPE_NONE, 389 AC97_SHARED_TYPE_ICH, 390 AC97_SHARED_TYPE_ATIIXP, 391 AC97_SHARED_TYPE_VIA, 392 AC97_SHARED_TYPES 393 }; 394 395 /* 396 * 397 */ 398 399 typedef struct _snd_ac97_bus ac97_bus_t; 400 typedef struct _snd_ac97_bus_ops ac97_bus_ops_t; 401 typedef struct _snd_ac97_template ac97_template_t; 402 typedef struct _snd_ac97 ac97_t; 403 404 enum ac97_pcm_cfg { 405 AC97_PCM_CFG_FRONT = 2, 406 AC97_PCM_CFG_REAR = 10, /* alias surround */ 407 AC97_PCM_CFG_LFE = 11, /* center + lfe */ 408 AC97_PCM_CFG_40 = 4, /* front + rear */ 409 AC97_PCM_CFG_51 = 6, /* front + rear + center/lfe */ 410 AC97_PCM_CFG_SPDIF = 20 411 }; 412 413 /* PCM allocation */ 414 struct ac97_pcm { 415 ac97_bus_t *bus; 416 unsigned int stream: 1, /* stream type: 1 = capture */ 417 exclusive: 1, /* exclusive mode, don't override with other pcms */ 418 copy_flag: 1, /* lowlevel driver must fill all entries */ 419 spdif: 1; /* spdif pcm */ 420 unsigned short aslots; /* active slots */ 421 unsigned int rates; /* available rates */ 422 struct { 423 unsigned short slots; /* driver input: requested AC97 slot numbers */ 424 unsigned short rslots[4]; /* allocated slots per codecs */ 425 unsigned char rate_table[4]; 426 ac97_t *codec[4]; /* allocated codecs */ 427 } r[2]; /* 0 = standard rates, 1 = double rates */ 428 unsigned long private_value; /* used by the hardware driver */ 429 }; 430 431 struct snd_ac97_build_ops { 432 int (*build_3d) (ac97_t *ac97); 433 int (*build_specific) (ac97_t *ac97); 434 int (*build_spdif) (ac97_t *ac97); 435 int (*build_post_spdif) (ac97_t *ac97); 436 #ifdef CONFIG_PM 437 void (*suspend) (ac97_t *ac97); 438 void (*resume) (ac97_t *ac97); 439 #endif 440 void (*update_jacks) (ac97_t *ac97); /* for jack-sharing */ 441 }; 442 443 struct _snd_ac97_bus_ops { 444 void (*reset) (ac97_t *ac97); 445 void (*write) (ac97_t *ac97, unsigned short reg, unsigned short val); 446 unsigned short (*read) (ac97_t *ac97, unsigned short reg); 447 void (*wait) (ac97_t *ac97); 448 void (*init) (ac97_t *ac97); 449 }; 450 451 struct _snd_ac97_bus { 452 /* -- lowlevel (hardware) driver specific -- */ 453 ac97_bus_ops_t *ops; 454 void *private_data; 455 void (*private_free) (ac97_bus_t *bus); 456 /* --- */ 457 snd_card_t *card; 458 unsigned short num; /* bus number */ 459 unsigned short no_vra: 1, /* bridge doesn't support VRA */ 460 dra: 1, /* bridge supports double rate */ 461 isdin: 1;/* independent SDIN */ 462 unsigned int clock; /* AC'97 base clock (usually 48000Hz) */ 463 spinlock_t bus_lock; /* used mainly for slot allocation */ 464 unsigned short used_slots[2][4]; /* actually used PCM slots */ 465 unsigned short pcms_count; /* count of PCMs */ 466 struct ac97_pcm *pcms; 467 unsigned int shared_type; /* type of shared controller betwen audio and modem */ 468 ac97_t *codec[4]; 469 snd_info_entry_t *proc; 470 }; 471 472 struct _snd_ac97_template { 473 void *private_data; 474 void (*private_free) (ac97_t *ac97); 475 struct pci_dev *pci; /* assigned PCI device - used for quirks */ 476 unsigned short num; /* number of codec: 0 = primary, 1 = secondary */ 477 unsigned short addr; /* physical address of codec [0-3] */ 478 unsigned int scaps; /* driver capabilities */ 479 unsigned int limited_regs; /* allow limited registers only */ 480 DECLARE_BITMAP(reg_accessed, 0x80); /* bit flags */ 481 }; 482 483 struct _snd_ac97 { 484 /* -- lowlevel (hardware) driver specific -- */ 485 struct snd_ac97_build_ops * build_ops; 486 void *private_data; 487 void (*private_free) (ac97_t *ac97); 488 /* --- */ 489 ac97_bus_t *bus; 490 struct pci_dev *pci; /* assigned PCI device - used for quirks */ 491 snd_info_entry_t *proc; 492 snd_info_entry_t *proc_regs; 493 unsigned short subsystem_vendor; 494 unsigned short subsystem_device; 495 struct semaphore reg_mutex; 496 struct semaphore page_mutex; /* mutex for AD18xx multi-codecs and paging (2.3) */ 497 unsigned short num; /* number of codec: 0 = primary, 1 = secondary */ 498 unsigned short addr; /* physical address of codec [0-3] */ 499 unsigned int id; /* identification of codec */ 500 unsigned short caps; /* capabilities (register 0) */ 501 unsigned short ext_id; /* extended feature identification (register 28) */ 502 unsigned short ext_mid; /* extended modem ID (register 3C) */ 503 unsigned int scaps; /* driver capabilities */ 504 unsigned int flags; /* specific code */ 505 unsigned int rates[6]; /* see AC97_RATES_* defines */ 506 unsigned int spdif_status; 507 unsigned short regs[0x80]; /* register cache */ 508 unsigned int limited_regs; /* allow limited registers only */ 509 DECLARE_BITMAP(reg_accessed, 0x80); /* bit flags */ 510 union { /* vendor specific code */ 511 struct { 512 unsigned short unchained[3]; // 0 = C34, 1 = C79, 2 = C69 513 unsigned short chained[3]; // 0 = C34, 1 = C79, 2 = C69 514 unsigned short id[3]; // codec IDs (lower 16-bit word) 515 unsigned short pcmreg[3]; // PCM registers 516 unsigned short codec_cfg[3]; // CODEC_CFG bits 517 } ad18xx; 518 unsigned int dev_flags; /* device specific */ 519 } spec; 520 /* jack-sharing info */ 521 unsigned char indep_surround; 522 unsigned char channel_mode; 523 }; 524 525 /* conditions */ 526 static inline int ac97_is_audio(ac97_t * ac97) 527 { 528 return (ac97->scaps & AC97_SCAP_AUDIO); 529 } 530 static inline int ac97_is_modem(ac97_t * ac97) 531 { 532 return (ac97->scaps & AC97_SCAP_MODEM); 533 } 534 static inline int ac97_is_rev22(ac97_t * ac97) 535 { 536 return (ac97->ext_id & AC97_EI_REV_MASK) >= AC97_EI_REV_22; 537 } 538 static inline int ac97_can_amap(ac97_t * ac97) 539 { 540 return (ac97->ext_id & AC97_EI_AMAP) != 0; 541 } 542 static inline int ac97_can_spdif(ac97_t * ac97) 543 { 544 return (ac97->ext_id & AC97_EI_SPDIF) != 0; 545 } 546 547 /* functions */ 548 int snd_ac97_bus(snd_card_t *card, int num, ac97_bus_ops_t *ops, void *private_data, ac97_bus_t **rbus); /* create new AC97 bus */ 549 int snd_ac97_mixer(ac97_bus_t *bus, ac97_template_t *template, ac97_t **rac97); /* create mixer controls */ 550 const char *snd_ac97_get_short_name(ac97_t *ac97); 551 552 void snd_ac97_write(ac97_t *ac97, unsigned short reg, unsigned short value); 553 unsigned short snd_ac97_read(ac97_t *ac97, unsigned short reg); 554 void snd_ac97_write_cache(ac97_t *ac97, unsigned short reg, unsigned short value); 555 int snd_ac97_update(ac97_t *ac97, unsigned short reg, unsigned short value); 556 int snd_ac97_update_bits(ac97_t *ac97, unsigned short reg, unsigned short mask, unsigned short value); 557 #ifdef CONFIG_PM 558 void snd_ac97_suspend(ac97_t *ac97); 559 void snd_ac97_resume(ac97_t *ac97); 560 #endif 561 562 /* quirk types */ 563 enum { 564 AC97_TUNE_DEFAULT = -1, /* use default from quirk list (not valid in list) */ 565 AC97_TUNE_NONE = 0, /* nothing extra to do */ 566 AC97_TUNE_HP_ONLY, /* headphone (true line-out) control as master only */ 567 AC97_TUNE_SWAP_HP, /* swap headphone and master controls */ 568 AC97_TUNE_SWAP_SURROUND, /* swap master and surround controls */ 569 AC97_TUNE_AD_SHARING, /* for AD1985, turn on OMS bit and use headphone */ 570 AC97_TUNE_ALC_JACK, /* for Realtek, enable JACK detection */ 571 AC97_TUNE_INV_EAPD, /* inverted EAPD implementation */ 572 AC97_TUNE_MUTE_LED, /* EAPD bit works as mute LED */ 573 }; 574 575 struct ac97_quirk { 576 unsigned short vendor; /* PCI vendor id */ 577 unsigned short device; /* PCI device id */ 578 unsigned short mask; /* device id bit mask, 0 = accept all */ 579 unsigned int codec_id; /* codec id (if any), 0 = accept all */ 580 const char *name; /* name shown as info */ 581 int type; /* quirk type above */ 582 }; 583 584 int snd_ac97_tune_hardware(ac97_t *ac97, struct ac97_quirk *quirk, const char *override); 585 int snd_ac97_set_rate(ac97_t *ac97, int reg, unsigned int rate); 586 587 int snd_ac97_pcm_assign(ac97_bus_t *ac97, 588 unsigned short pcms_count, 589 const struct ac97_pcm *pcms); 590 int snd_ac97_pcm_open(struct ac97_pcm *pcm, unsigned int rate, 591 enum ac97_pcm_cfg cfg, unsigned short slots); 592 int snd_ac97_pcm_close(struct ac97_pcm *pcm); 593 int snd_ac97_pcm_double_rate_rules(snd_pcm_runtime_t *runtime); 594 595 struct ac97_enum { 596 unsigned char reg; 597 unsigned char shift_l; 598 unsigned char shift_r; 599 unsigned short mask; 600 const char **texts; 601 }; 602 #endif /* __SOUND_AC97_CODEC_H */ 603