1 /* 2 * Copyright (c) 2010 Google, Inc 3 * Copyright (c) 2014 NVIDIA Corporation 4 * 5 * Author: 6 * Colin Cross <ccross@google.com> 7 * 8 * This software is licensed under the terms of the GNU General Public 9 * License version 2, as published by the Free Software Foundation, and 10 * may be copied, distributed, and modified under those terms. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 */ 18 19 #ifndef __SOC_TEGRA_PMC_H__ 20 #define __SOC_TEGRA_PMC_H__ 21 22 #include <linux/reboot.h> 23 24 #include <soc/tegra/pm.h> 25 26 struct clk; 27 struct reset_control; 28 29 void tegra_pmc_restart(enum reboot_mode mode, const char *cmd); 30 31 #ifdef CONFIG_PM_SLEEP 32 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void); 33 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode); 34 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode); 35 #endif /* CONFIG_PM_SLEEP */ 36 37 #ifdef CONFIG_SMP 38 bool tegra_pmc_cpu_is_powered(int cpuid); 39 int tegra_pmc_cpu_power_on(int cpuid); 40 int tegra_pmc_cpu_remove_clamping(int cpuid); 41 #endif /* CONFIG_SMP */ 42 43 /* 44 * powergate and I/O rail APIs 45 */ 46 47 #define TEGRA_POWERGATE_CPU 0 48 #define TEGRA_POWERGATE_3D 1 49 #define TEGRA_POWERGATE_VENC 2 50 #define TEGRA_POWERGATE_PCIE 3 51 #define TEGRA_POWERGATE_VDEC 4 52 #define TEGRA_POWERGATE_L2 5 53 #define TEGRA_POWERGATE_MPE 6 54 #define TEGRA_POWERGATE_HEG 7 55 #define TEGRA_POWERGATE_SATA 8 56 #define TEGRA_POWERGATE_CPU1 9 57 #define TEGRA_POWERGATE_CPU2 10 58 #define TEGRA_POWERGATE_CPU3 11 59 #define TEGRA_POWERGATE_CELP 12 60 #define TEGRA_POWERGATE_3D1 13 61 #define TEGRA_POWERGATE_CPU0 14 62 #define TEGRA_POWERGATE_C0NC 15 63 #define TEGRA_POWERGATE_C1NC 16 64 #define TEGRA_POWERGATE_SOR 17 65 #define TEGRA_POWERGATE_DIS 18 66 #define TEGRA_POWERGATE_DISB 19 67 #define TEGRA_POWERGATE_XUSBA 20 68 #define TEGRA_POWERGATE_XUSBB 21 69 #define TEGRA_POWERGATE_XUSBC 22 70 #define TEGRA_POWERGATE_VIC 23 71 #define TEGRA_POWERGATE_IRAM 24 72 73 #define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D 74 75 #define TEGRA_IO_RAIL_CSIA 0 76 #define TEGRA_IO_RAIL_CSIB 1 77 #define TEGRA_IO_RAIL_DSI 2 78 #define TEGRA_IO_RAIL_MIPI_BIAS 3 79 #define TEGRA_IO_RAIL_PEX_BIAS 4 80 #define TEGRA_IO_RAIL_PEX_CLK1 5 81 #define TEGRA_IO_RAIL_PEX_CLK2 6 82 #define TEGRA_IO_RAIL_USB0 9 83 #define TEGRA_IO_RAIL_USB1 10 84 #define TEGRA_IO_RAIL_USB2 11 85 #define TEGRA_IO_RAIL_USB_BIAS 12 86 #define TEGRA_IO_RAIL_NAND 13 87 #define TEGRA_IO_RAIL_UART 14 88 #define TEGRA_IO_RAIL_BB 15 89 #define TEGRA_IO_RAIL_AUDIO 17 90 #define TEGRA_IO_RAIL_HSIC 19 91 #define TEGRA_IO_RAIL_COMP 22 92 #define TEGRA_IO_RAIL_HDMI 28 93 #define TEGRA_IO_RAIL_PEX_CNTRL 32 94 #define TEGRA_IO_RAIL_SDMMC1 33 95 #define TEGRA_IO_RAIL_SDMMC3 34 96 #define TEGRA_IO_RAIL_SDMMC4 35 97 #define TEGRA_IO_RAIL_CAM 36 98 #define TEGRA_IO_RAIL_RES 37 99 #define TEGRA_IO_RAIL_HV 38 100 #define TEGRA_IO_RAIL_DSIB 39 101 #define TEGRA_IO_RAIL_DSIC 40 102 #define TEGRA_IO_RAIL_DSID 41 103 #define TEGRA_IO_RAIL_CSIE 44 104 #define TEGRA_IO_RAIL_LVDS 57 105 #define TEGRA_IO_RAIL_SYS_DDC 58 106 107 #ifdef CONFIG_ARCH_TEGRA 108 int tegra_powergate_is_powered(int id); 109 int tegra_powergate_power_on(int id); 110 int tegra_powergate_power_off(int id); 111 int tegra_powergate_remove_clamping(int id); 112 113 /* Must be called with clk disabled, and returns with clk enabled */ 114 int tegra_powergate_sequence_power_up(int id, struct clk *clk, 115 struct reset_control *rst); 116 117 int tegra_io_rail_power_on(int id); 118 int tegra_io_rail_power_off(int id); 119 #else 120 static inline int tegra_powergate_is_powered(int id) 121 { 122 return -ENOSYS; 123 } 124 125 static inline int tegra_powergate_power_on(int id) 126 { 127 return -ENOSYS; 128 } 129 130 static inline int tegra_powergate_power_off(int id) 131 { 132 return -ENOSYS; 133 } 134 135 static inline int tegra_powergate_remove_clamping(int id) 136 { 137 return -ENOSYS; 138 } 139 140 static inline int tegra_powergate_sequence_power_up(int id, struct clk *clk, 141 struct reset_control *rst) 142 { 143 return -ENOSYS; 144 } 145 146 static inline int tegra_io_rail_power_on(int id) 147 { 148 return -ENOSYS; 149 } 150 151 static inline int tegra_io_rail_power_off(int id) 152 { 153 return -ENOSYS; 154 } 155 #endif /* CONFIG_ARCH_TEGRA */ 156 157 #endif /* __SOC_TEGRA_PMC_H__ */ 158