1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2014 NVIDIA Corporation 4 */ 5 6 #ifndef __SOC_TEGRA_MC_H__ 7 #define __SOC_TEGRA_MC_H__ 8 9 #include <linux/bits.h> 10 #include <linux/err.h> 11 #include <linux/interconnect-provider.h> 12 #include <linux/reset-controller.h> 13 #include <linux/types.h> 14 15 struct clk; 16 struct device; 17 struct page; 18 19 struct tegra_smmu_enable { 20 unsigned int reg; 21 unsigned int bit; 22 }; 23 24 struct tegra_mc_timing { 25 unsigned long rate; 26 27 u32 *emem_data; 28 }; 29 30 /* latency allowance */ 31 struct tegra_mc_la { 32 unsigned int reg; 33 unsigned int shift; 34 unsigned int mask; 35 unsigned int def; 36 }; 37 38 struct tegra_mc_client { 39 unsigned int id; 40 const char *name; 41 unsigned int swgroup; 42 43 unsigned int fifo_size; 44 45 struct tegra_smmu_enable smmu; 46 struct tegra_mc_la la; 47 }; 48 49 struct tegra_smmu_swgroup { 50 const char *name; 51 unsigned int swgroup; 52 unsigned int reg; 53 }; 54 55 struct tegra_smmu_group_soc { 56 const char *name; 57 const unsigned int *swgroups; 58 unsigned int num_swgroups; 59 }; 60 61 struct tegra_smmu_soc { 62 const struct tegra_mc_client *clients; 63 unsigned int num_clients; 64 65 const struct tegra_smmu_swgroup *swgroups; 66 unsigned int num_swgroups; 67 68 const struct tegra_smmu_group_soc *groups; 69 unsigned int num_groups; 70 71 bool supports_round_robin_arbitration; 72 bool supports_request_limit; 73 74 unsigned int num_tlb_lines; 75 unsigned int num_asids; 76 }; 77 78 struct tegra_mc; 79 struct tegra_smmu; 80 struct gart_device; 81 82 #ifdef CONFIG_TEGRA_IOMMU_SMMU 83 struct tegra_smmu *tegra_smmu_probe(struct device *dev, 84 const struct tegra_smmu_soc *soc, 85 struct tegra_mc *mc); 86 void tegra_smmu_remove(struct tegra_smmu *smmu); 87 #else 88 static inline struct tegra_smmu * 89 tegra_smmu_probe(struct device *dev, const struct tegra_smmu_soc *soc, 90 struct tegra_mc *mc) 91 { 92 return NULL; 93 } 94 95 static inline void tegra_smmu_remove(struct tegra_smmu *smmu) 96 { 97 } 98 #endif 99 100 #ifdef CONFIG_TEGRA_IOMMU_GART 101 struct gart_device *tegra_gart_probe(struct device *dev, struct tegra_mc *mc); 102 int tegra_gart_suspend(struct gart_device *gart); 103 int tegra_gart_resume(struct gart_device *gart); 104 #else 105 static inline struct gart_device * 106 tegra_gart_probe(struct device *dev, struct tegra_mc *mc) 107 { 108 return ERR_PTR(-ENODEV); 109 } 110 111 static inline int tegra_gart_suspend(struct gart_device *gart) 112 { 113 return -ENODEV; 114 } 115 116 static inline int tegra_gart_resume(struct gart_device *gart) 117 { 118 return -ENODEV; 119 } 120 #endif 121 122 struct tegra_mc_reset { 123 const char *name; 124 unsigned long id; 125 unsigned int control; 126 unsigned int status; 127 unsigned int reset; 128 unsigned int bit; 129 }; 130 131 struct tegra_mc_reset_ops { 132 int (*hotreset_assert)(struct tegra_mc *mc, 133 const struct tegra_mc_reset *rst); 134 int (*hotreset_deassert)(struct tegra_mc *mc, 135 const struct tegra_mc_reset *rst); 136 int (*block_dma)(struct tegra_mc *mc, 137 const struct tegra_mc_reset *rst); 138 bool (*dma_idling)(struct tegra_mc *mc, 139 const struct tegra_mc_reset *rst); 140 int (*unblock_dma)(struct tegra_mc *mc, 141 const struct tegra_mc_reset *rst); 142 int (*reset_status)(struct tegra_mc *mc, 143 const struct tegra_mc_reset *rst); 144 }; 145 146 #define TEGRA_MC_ICC_TAG_DEFAULT 0 147 #define TEGRA_MC_ICC_TAG_ISO BIT(0) 148 149 struct tegra_mc_icc_ops { 150 int (*set)(struct icc_node *src, struct icc_node *dst); 151 int (*aggregate)(struct icc_node *node, u32 tag, u32 avg_bw, 152 u32 peak_bw, u32 *agg_avg, u32 *agg_peak); 153 struct icc_node_data *(*xlate_extended)(struct of_phandle_args *spec, 154 void *data); 155 }; 156 157 struct tegra_mc_soc { 158 const struct tegra_mc_client *clients; 159 unsigned int num_clients; 160 161 const unsigned long *emem_regs; 162 unsigned int num_emem_regs; 163 164 unsigned int num_address_bits; 165 unsigned int atom_size; 166 167 u8 client_id_mask; 168 169 const struct tegra_smmu_soc *smmu; 170 171 u32 intmask; 172 173 const struct tegra_mc_reset_ops *reset_ops; 174 const struct tegra_mc_reset *resets; 175 unsigned int num_resets; 176 177 const struct tegra_mc_icc_ops *icc_ops; 178 }; 179 180 struct tegra_mc { 181 struct device *dev; 182 struct tegra_smmu *smmu; 183 struct gart_device *gart; 184 void __iomem *regs; 185 struct clk *clk; 186 int irq; 187 188 const struct tegra_mc_soc *soc; 189 unsigned long tick; 190 191 struct tegra_mc_timing *timings; 192 unsigned int num_timings; 193 194 struct reset_controller_dev reset; 195 196 struct icc_provider provider; 197 198 spinlock_t lock; 199 }; 200 201 int tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate); 202 unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc); 203 204 #ifdef CONFIG_TEGRA_MC 205 struct tegra_mc *devm_tegra_memory_controller_get(struct device *dev); 206 #else 207 static inline struct tegra_mc * 208 devm_tegra_memory_controller_get(struct device *dev) 209 { 210 return ERR_PTR(-ENODEV); 211 } 212 #endif 213 214 #endif /* __SOC_TEGRA_MC_H__ */ 215