1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2014 NVIDIA Corporation
4 */
5
6 #ifndef __SOC_TEGRA_MC_H__
7 #define __SOC_TEGRA_MC_H__
8
9 #include <linux/bits.h>
10 #include <linux/debugfs.h>
11 #include <linux/err.h>
12 #include <linux/interconnect-provider.h>
13 #include <linux/irq.h>
14 #include <linux/reset-controller.h>
15 #include <linux/types.h>
16 #include <linux/tegra-icc.h>
17
18 struct clk;
19 struct device;
20 struct page;
21
22 struct tegra_mc_timing {
23 unsigned long rate;
24
25 u32 *emem_data;
26 };
27
28 struct tegra_mc_client {
29 unsigned int id;
30 unsigned int bpmp_id;
31 enum tegra_icc_client_type type;
32 const char *name;
33 /*
34 * For Tegra210 and earlier, this is the SWGROUP ID used for IOVA translations in the
35 * Tegra SMMU, whereas on Tegra186 and later this is the ID used to override the ARM SMMU
36 * stream ID used for IOVA translations for the given memory client.
37 */
38 union {
39 unsigned int swgroup;
40 unsigned int sid;
41 };
42
43 unsigned int fifo_size;
44
45 struct {
46 /* Tegra SMMU enable (Tegra210 and earlier) */
47 struct {
48 unsigned int reg;
49 unsigned int bit;
50 } smmu;
51
52 /* latency allowance */
53 struct {
54 unsigned int reg;
55 unsigned int shift;
56 unsigned int mask;
57 unsigned int def;
58 } la;
59
60 /* stream ID overrides (Tegra186 and later) */
61 struct {
62 unsigned int override;
63 unsigned int security;
64 } sid;
65 } regs;
66 };
67
68 struct tegra_smmu_swgroup {
69 const char *name;
70 unsigned int swgroup;
71 unsigned int reg;
72 };
73
74 struct tegra_smmu_group_soc {
75 const char *name;
76 const unsigned int *swgroups;
77 unsigned int num_swgroups;
78 };
79
80 struct tegra_smmu_soc {
81 const struct tegra_mc_client *clients;
82 unsigned int num_clients;
83
84 const struct tegra_smmu_swgroup *swgroups;
85 unsigned int num_swgroups;
86
87 const struct tegra_smmu_group_soc *groups;
88 unsigned int num_groups;
89
90 bool supports_round_robin_arbitration;
91 bool supports_request_limit;
92
93 unsigned int num_tlb_lines;
94 unsigned int num_asids;
95 };
96
97 struct tegra_mc;
98 struct tegra_smmu;
99 struct gart_device;
100
101 #ifdef CONFIG_TEGRA_IOMMU_SMMU
102 struct tegra_smmu *tegra_smmu_probe(struct device *dev,
103 const struct tegra_smmu_soc *soc,
104 struct tegra_mc *mc);
105 void tegra_smmu_remove(struct tegra_smmu *smmu);
106 #else
107 static inline struct tegra_smmu *
tegra_smmu_probe(struct device * dev,const struct tegra_smmu_soc * soc,struct tegra_mc * mc)108 tegra_smmu_probe(struct device *dev, const struct tegra_smmu_soc *soc,
109 struct tegra_mc *mc)
110 {
111 return NULL;
112 }
113
tegra_smmu_remove(struct tegra_smmu * smmu)114 static inline void tegra_smmu_remove(struct tegra_smmu *smmu)
115 {
116 }
117 #endif
118
119 #ifdef CONFIG_TEGRA_IOMMU_GART
120 struct gart_device *tegra_gart_probe(struct device *dev, struct tegra_mc *mc);
121 int tegra_gart_suspend(struct gart_device *gart);
122 int tegra_gart_resume(struct gart_device *gart);
123 #else
124 static inline struct gart_device *
tegra_gart_probe(struct device * dev,struct tegra_mc * mc)125 tegra_gart_probe(struct device *dev, struct tegra_mc *mc)
126 {
127 return ERR_PTR(-ENODEV);
128 }
129
tegra_gart_suspend(struct gart_device * gart)130 static inline int tegra_gart_suspend(struct gart_device *gart)
131 {
132 return -ENODEV;
133 }
134
tegra_gart_resume(struct gart_device * gart)135 static inline int tegra_gart_resume(struct gart_device *gart)
136 {
137 return -ENODEV;
138 }
139 #endif
140
141 struct tegra_mc_reset {
142 const char *name;
143 unsigned long id;
144 unsigned int control;
145 unsigned int status;
146 unsigned int reset;
147 unsigned int bit;
148 };
149
150 struct tegra_mc_reset_ops {
151 int (*hotreset_assert)(struct tegra_mc *mc,
152 const struct tegra_mc_reset *rst);
153 int (*hotreset_deassert)(struct tegra_mc *mc,
154 const struct tegra_mc_reset *rst);
155 int (*block_dma)(struct tegra_mc *mc,
156 const struct tegra_mc_reset *rst);
157 bool (*dma_idling)(struct tegra_mc *mc,
158 const struct tegra_mc_reset *rst);
159 int (*unblock_dma)(struct tegra_mc *mc,
160 const struct tegra_mc_reset *rst);
161 int (*reset_status)(struct tegra_mc *mc,
162 const struct tegra_mc_reset *rst);
163 };
164
165 #define TEGRA_MC_ICC_TAG_DEFAULT 0
166 #define TEGRA_MC_ICC_TAG_ISO BIT(0)
167
168 struct tegra_mc_icc_ops {
169 int (*set)(struct icc_node *src, struct icc_node *dst);
170 int (*aggregate)(struct icc_node *node, u32 tag, u32 avg_bw,
171 u32 peak_bw, u32 *agg_avg, u32 *agg_peak);
172 struct icc_node* (*xlate)(struct of_phandle_args *spec, void *data);
173 struct icc_node_data *(*xlate_extended)(struct of_phandle_args *spec,
174 void *data);
175 int (*get_bw)(struct icc_node *node, u32 *avg, u32 *peak);
176 };
177
178 struct icc_node *tegra_mc_icc_xlate(struct of_phandle_args *spec, void *data);
179 extern const struct tegra_mc_icc_ops tegra_mc_icc_ops;
180
181 struct tegra_mc_ops {
182 /*
183 * @probe: Callback to set up SoC-specific bits of the memory controller. This is called
184 * after basic, common set up that is done by the SoC-agnostic bits.
185 */
186 int (*probe)(struct tegra_mc *mc);
187 void (*remove)(struct tegra_mc *mc);
188 int (*suspend)(struct tegra_mc *mc);
189 int (*resume)(struct tegra_mc *mc);
190 irqreturn_t (*handle_irq)(int irq, void *data);
191 int (*probe_device)(struct tegra_mc *mc, struct device *dev);
192 };
193
194 struct tegra_mc_soc {
195 const struct tegra_mc_client *clients;
196 unsigned int num_clients;
197
198 const unsigned long *emem_regs;
199 unsigned int num_emem_regs;
200
201 unsigned int num_address_bits;
202 unsigned int atom_size;
203
204 unsigned int num_carveouts;
205
206 u16 client_id_mask;
207 u8 num_channels;
208
209 const struct tegra_smmu_soc *smmu;
210
211 u32 intmask;
212 u32 ch_intmask;
213 u32 global_intstatus_channel_shift;
214 bool has_addr_hi_reg;
215
216 const struct tegra_mc_reset_ops *reset_ops;
217 const struct tegra_mc_reset *resets;
218 unsigned int num_resets;
219
220 const struct tegra_mc_icc_ops *icc_ops;
221 const struct tegra_mc_ops *ops;
222 };
223
224 struct tegra_mc {
225 struct tegra_bpmp *bpmp;
226 struct device *dev;
227 struct tegra_smmu *smmu;
228 struct gart_device *gart;
229 void __iomem *regs;
230 void __iomem *bcast_ch_regs;
231 void __iomem **ch_regs;
232 struct clk *clk;
233 int irq;
234
235 const struct tegra_mc_soc *soc;
236 unsigned long tick;
237
238 struct tegra_mc_timing *timings;
239 unsigned int num_timings;
240 unsigned int num_channels;
241
242 bool bwmgr_mrq_supported;
243 struct reset_controller_dev reset;
244
245 struct icc_provider provider;
246
247 spinlock_t lock;
248
249 struct {
250 struct dentry *root;
251 } debugfs;
252 };
253
254 int tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate);
255 unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc);
256
257 #ifdef CONFIG_TEGRA_MC
258 struct tegra_mc *devm_tegra_memory_controller_get(struct device *dev);
259 int tegra_mc_probe_device(struct tegra_mc *mc, struct device *dev);
260 int tegra_mc_get_carveout_info(struct tegra_mc *mc, unsigned int id,
261 phys_addr_t *base, u64 *size);
262 #else
263 static inline struct tegra_mc *
devm_tegra_memory_controller_get(struct device * dev)264 devm_tegra_memory_controller_get(struct device *dev)
265 {
266 return ERR_PTR(-ENODEV);
267 }
268
269 static inline int
tegra_mc_probe_device(struct tegra_mc * mc,struct device * dev)270 tegra_mc_probe_device(struct tegra_mc *mc, struct device *dev)
271 {
272 return -ENODEV;
273 }
274
275 static inline int
tegra_mc_get_carveout_info(struct tegra_mc * mc,unsigned int id,phys_addr_t * base,u64 * size)276 tegra_mc_get_carveout_info(struct tegra_mc *mc, unsigned int id,
277 phys_addr_t *base, u64 *size)
278 {
279 return -ENODEV;
280 }
281 #endif
282
283 #endif /* __SOC_TEGRA_MC_H__ */
284