1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2014 NVIDIA Corporation 4 */ 5 6 #ifndef __SOC_TEGRA_MC_H__ 7 #define __SOC_TEGRA_MC_H__ 8 9 #include <linux/bits.h> 10 #include <linux/debugfs.h> 11 #include <linux/err.h> 12 #include <linux/interconnect-provider.h> 13 #include <linux/irq.h> 14 #include <linux/reset-controller.h> 15 #include <linux/types.h> 16 17 struct clk; 18 struct device; 19 struct page; 20 21 struct tegra_mc_timing { 22 unsigned long rate; 23 24 u32 *emem_data; 25 }; 26 27 struct tegra_mc_client { 28 unsigned int id; 29 const char *name; 30 /* 31 * For Tegra210 and earlier, this is the SWGROUP ID used for IOVA translations in the 32 * Tegra SMMU, whereas on Tegra186 and later this is the ID used to override the ARM SMMU 33 * stream ID used for IOVA translations for the given memory client. 34 */ 35 union { 36 unsigned int swgroup; 37 unsigned int sid; 38 }; 39 40 unsigned int fifo_size; 41 42 struct { 43 /* Tegra SMMU enable (Tegra210 and earlier) */ 44 struct { 45 unsigned int reg; 46 unsigned int bit; 47 } smmu; 48 49 /* latency allowance */ 50 struct { 51 unsigned int reg; 52 unsigned int shift; 53 unsigned int mask; 54 unsigned int def; 55 } la; 56 57 /* stream ID overrides (Tegra186 and later) */ 58 struct { 59 unsigned int override; 60 unsigned int security; 61 } sid; 62 } regs; 63 }; 64 65 struct tegra_smmu_swgroup { 66 const char *name; 67 unsigned int swgroup; 68 unsigned int reg; 69 }; 70 71 struct tegra_smmu_group_soc { 72 const char *name; 73 const unsigned int *swgroups; 74 unsigned int num_swgroups; 75 }; 76 77 struct tegra_smmu_soc { 78 const struct tegra_mc_client *clients; 79 unsigned int num_clients; 80 81 const struct tegra_smmu_swgroup *swgroups; 82 unsigned int num_swgroups; 83 84 const struct tegra_smmu_group_soc *groups; 85 unsigned int num_groups; 86 87 bool supports_round_robin_arbitration; 88 bool supports_request_limit; 89 90 unsigned int num_tlb_lines; 91 unsigned int num_asids; 92 }; 93 94 struct tegra_mc; 95 struct tegra_smmu; 96 struct gart_device; 97 98 #ifdef CONFIG_TEGRA_IOMMU_SMMU 99 struct tegra_smmu *tegra_smmu_probe(struct device *dev, 100 const struct tegra_smmu_soc *soc, 101 struct tegra_mc *mc); 102 void tegra_smmu_remove(struct tegra_smmu *smmu); 103 #else 104 static inline struct tegra_smmu * 105 tegra_smmu_probe(struct device *dev, const struct tegra_smmu_soc *soc, 106 struct tegra_mc *mc) 107 { 108 return NULL; 109 } 110 111 static inline void tegra_smmu_remove(struct tegra_smmu *smmu) 112 { 113 } 114 #endif 115 116 #ifdef CONFIG_TEGRA_IOMMU_GART 117 struct gart_device *tegra_gart_probe(struct device *dev, struct tegra_mc *mc); 118 int tegra_gart_suspend(struct gart_device *gart); 119 int tegra_gart_resume(struct gart_device *gart); 120 #else 121 static inline struct gart_device * 122 tegra_gart_probe(struct device *dev, struct tegra_mc *mc) 123 { 124 return ERR_PTR(-ENODEV); 125 } 126 127 static inline int tegra_gart_suspend(struct gart_device *gart) 128 { 129 return -ENODEV; 130 } 131 132 static inline int tegra_gart_resume(struct gart_device *gart) 133 { 134 return -ENODEV; 135 } 136 #endif 137 138 struct tegra_mc_reset { 139 const char *name; 140 unsigned long id; 141 unsigned int control; 142 unsigned int status; 143 unsigned int reset; 144 unsigned int bit; 145 }; 146 147 struct tegra_mc_reset_ops { 148 int (*hotreset_assert)(struct tegra_mc *mc, 149 const struct tegra_mc_reset *rst); 150 int (*hotreset_deassert)(struct tegra_mc *mc, 151 const struct tegra_mc_reset *rst); 152 int (*block_dma)(struct tegra_mc *mc, 153 const struct tegra_mc_reset *rst); 154 bool (*dma_idling)(struct tegra_mc *mc, 155 const struct tegra_mc_reset *rst); 156 int (*unblock_dma)(struct tegra_mc *mc, 157 const struct tegra_mc_reset *rst); 158 int (*reset_status)(struct tegra_mc *mc, 159 const struct tegra_mc_reset *rst); 160 }; 161 162 #define TEGRA_MC_ICC_TAG_DEFAULT 0 163 #define TEGRA_MC_ICC_TAG_ISO BIT(0) 164 165 struct tegra_mc_icc_ops { 166 int (*set)(struct icc_node *src, struct icc_node *dst); 167 int (*aggregate)(struct icc_node *node, u32 tag, u32 avg_bw, 168 u32 peak_bw, u32 *agg_avg, u32 *agg_peak); 169 struct icc_node_data *(*xlate_extended)(struct of_phandle_args *spec, 170 void *data); 171 }; 172 173 struct tegra_mc_ops { 174 /* 175 * @probe: Callback to set up SoC-specific bits of the memory controller. This is called 176 * after basic, common set up that is done by the SoC-agnostic bits. 177 */ 178 int (*probe)(struct tegra_mc *mc); 179 void (*remove)(struct tegra_mc *mc); 180 int (*suspend)(struct tegra_mc *mc); 181 int (*resume)(struct tegra_mc *mc); 182 irqreturn_t (*handle_irq)(int irq, void *data); 183 int (*probe_device)(struct tegra_mc *mc, struct device *dev); 184 }; 185 186 struct tegra_mc_soc { 187 const struct tegra_mc_client *clients; 188 unsigned int num_clients; 189 190 const unsigned long *emem_regs; 191 unsigned int num_emem_regs; 192 193 unsigned int num_address_bits; 194 unsigned int atom_size; 195 196 unsigned int num_carveouts; 197 198 u16 client_id_mask; 199 u8 num_channels; 200 201 const struct tegra_smmu_soc *smmu; 202 203 u32 intmask; 204 u32 ch_intmask; 205 u32 global_intstatus_channel_shift; 206 bool has_addr_hi_reg; 207 208 const struct tegra_mc_reset_ops *reset_ops; 209 const struct tegra_mc_reset *resets; 210 unsigned int num_resets; 211 212 const struct tegra_mc_icc_ops *icc_ops; 213 const struct tegra_mc_ops *ops; 214 }; 215 216 struct tegra_mc { 217 struct device *dev; 218 struct tegra_smmu *smmu; 219 struct gart_device *gart; 220 void __iomem *regs; 221 void __iomem *bcast_ch_regs; 222 void __iomem **ch_regs; 223 struct clk *clk; 224 int irq; 225 226 const struct tegra_mc_soc *soc; 227 unsigned long tick; 228 229 struct tegra_mc_timing *timings; 230 unsigned int num_timings; 231 232 struct reset_controller_dev reset; 233 234 struct icc_provider provider; 235 236 spinlock_t lock; 237 238 struct { 239 struct dentry *root; 240 } debugfs; 241 }; 242 243 int tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate); 244 unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc); 245 246 #ifdef CONFIG_TEGRA_MC 247 struct tegra_mc *devm_tegra_memory_controller_get(struct device *dev); 248 int tegra_mc_probe_device(struct tegra_mc *mc, struct device *dev); 249 int tegra_mc_get_carveout_info(struct tegra_mc *mc, unsigned int id, 250 phys_addr_t *base, u64 *size); 251 #else 252 static inline struct tegra_mc * 253 devm_tegra_memory_controller_get(struct device *dev) 254 { 255 return ERR_PTR(-ENODEV); 256 } 257 258 static inline int 259 tegra_mc_probe_device(struct tegra_mc *mc, struct device *dev) 260 { 261 return -ENODEV; 262 } 263 264 static inline int 265 tegra_mc_get_carveout_info(struct tegra_mc *mc, unsigned int id, 266 phys_addr_t *base, u64 *size) 267 { 268 return -ENODEV; 269 } 270 #endif 271 272 #endif /* __SOC_TEGRA_MC_H__ */ 273