1 /* 2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #ifndef __SOC_TEGRA_FUSE_H__ 18 #define __SOC_TEGRA_FUSE_H__ 19 20 #define TEGRA20 0x20 21 #define TEGRA30 0x30 22 #define TEGRA114 0x35 23 #define TEGRA124 0x40 24 25 #define TEGRA_FUSE_SKU_CALIB_0 0xf0 26 #define TEGRA30_FUSE_SATA_CALIB 0x124 27 28 #ifndef __ASSEMBLY__ 29 30 u32 tegra_read_chipid(void); 31 u8 tegra_get_chip_id(void); 32 33 enum tegra_revision { 34 TEGRA_REVISION_UNKNOWN = 0, 35 TEGRA_REVISION_A01, 36 TEGRA_REVISION_A02, 37 TEGRA_REVISION_A03, 38 TEGRA_REVISION_A03p, 39 TEGRA_REVISION_A04, 40 TEGRA_REVISION_MAX, 41 }; 42 43 struct tegra_sku_info { 44 int sku_id; 45 int cpu_process_id; 46 int cpu_speedo_id; 47 int cpu_speedo_value; 48 int cpu_iddq_value; 49 int core_process_id; 50 int soc_speedo_id; 51 int gpu_speedo_id; 52 int gpu_process_id; 53 int gpu_speedo_value; 54 enum tegra_revision revision; 55 }; 56 57 u32 tegra_read_straps(void); 58 u32 tegra_read_chipid(void); 59 int tegra_fuse_readl(unsigned long offset, u32 *value); 60 61 extern struct tegra_sku_info tegra_sku_info; 62 63 #endif /* __ASSEMBLY__ */ 64 65 #endif /* __SOC_TEGRA_FUSE_H__ */ 66