1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #ifndef __SOC_TEGRA_FUSE_H__ 7 #define __SOC_TEGRA_FUSE_H__ 8 9 #define TEGRA20 0x20 10 #define TEGRA30 0x30 11 #define TEGRA114 0x35 12 #define TEGRA124 0x40 13 #define TEGRA132 0x13 14 #define TEGRA210 0x21 15 16 #define TEGRA_FUSE_SKU_CALIB_0 0xf0 17 #define TEGRA30_FUSE_SATA_CALIB 0x124 18 #define TEGRA_FUSE_USB_CALIB_EXT_0 0x250 19 20 #ifndef __ASSEMBLY__ 21 22 u32 tegra_read_chipid(void); 23 u8 tegra_get_chip_id(void); 24 25 enum tegra_revision { 26 TEGRA_REVISION_UNKNOWN = 0, 27 TEGRA_REVISION_A01, 28 TEGRA_REVISION_A02, 29 TEGRA_REVISION_A03, 30 TEGRA_REVISION_A03p, 31 TEGRA_REVISION_A04, 32 TEGRA_REVISION_MAX, 33 }; 34 35 struct tegra_sku_info { 36 int sku_id; 37 int cpu_process_id; 38 int cpu_speedo_id; 39 int cpu_speedo_value; 40 int cpu_iddq_value; 41 int soc_process_id; 42 int soc_speedo_id; 43 int soc_speedo_value; 44 int gpu_process_id; 45 int gpu_speedo_id; 46 int gpu_speedo_value; 47 enum tegra_revision revision; 48 }; 49 50 u32 tegra_read_straps(void); 51 u32 tegra_read_ram_code(void); 52 int tegra_fuse_readl(unsigned long offset, u32 *value); 53 54 extern struct tegra_sku_info tegra_sku_info; 55 56 struct device *tegra_soc_device_register(void); 57 58 #endif /* __ASSEMBLY__ */ 59 60 #endif /* __SOC_TEGRA_FUSE_H__ */ 61