1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #ifndef __SOC_TEGRA_FUSE_H__ 7 #define __SOC_TEGRA_FUSE_H__ 8 9 #include <linux/types.h> 10 11 #define TEGRA20 0x20 12 #define TEGRA30 0x30 13 #define TEGRA114 0x35 14 #define TEGRA124 0x40 15 #define TEGRA132 0x13 16 #define TEGRA210 0x21 17 #define TEGRA186 0x18 18 #define TEGRA194 0x19 19 #define TEGRA234 0x23 20 21 #define TEGRA_FUSE_SKU_CALIB_0 0xf0 22 #define TEGRA30_FUSE_SATA_CALIB 0x124 23 #define TEGRA_FUSE_USB_CALIB_EXT_0 0x250 24 25 #ifndef __ASSEMBLY__ 26 27 enum tegra_revision { 28 TEGRA_REVISION_UNKNOWN = 0, 29 TEGRA_REVISION_A01, 30 TEGRA_REVISION_A02, 31 TEGRA_REVISION_A03, 32 TEGRA_REVISION_A03p, 33 TEGRA_REVISION_A04, 34 TEGRA_REVISION_MAX, 35 }; 36 37 enum tegra_platform { 38 TEGRA_PLATFORM_SILICON = 0, 39 TEGRA_PLATFORM_QT, 40 TEGRA_PLATFORM_SYSTEM_FPGA, 41 TEGRA_PLATFORM_UNIT_FPGA, 42 TEGRA_PLATFORM_ASIM_QT, 43 TEGRA_PLATFORM_ASIM_LINSIM, 44 TEGRA_PLATFORM_DSIM_ASIM_LINSIM, 45 TEGRA_PLATFORM_VERIFICATION_SIMULATION, 46 TEGRA_PLATFORM_VDK, 47 TEGRA_PLATFORM_VSP, 48 TEGRA_PLATFORM_MAX, 49 }; 50 51 struct tegra_sku_info { 52 int sku_id; 53 int cpu_process_id; 54 int cpu_speedo_id; 55 int cpu_speedo_value; 56 int cpu_iddq_value; 57 int soc_process_id; 58 int soc_speedo_id; 59 int soc_speedo_value; 60 int gpu_process_id; 61 int gpu_speedo_id; 62 int gpu_speedo_value; 63 enum tegra_revision revision; 64 enum tegra_platform platform; 65 }; 66 67 #ifdef CONFIG_ARCH_TEGRA 68 extern struct tegra_sku_info tegra_sku_info; 69 u32 tegra_read_straps(void); 70 u32 tegra_read_ram_code(void); 71 int tegra_fuse_readl(unsigned long offset, u32 *value); 72 u32 tegra_read_chipid(void); 73 u8 tegra_get_chip_id(void); 74 u8 tegra_get_platform(void); 75 bool tegra_is_silicon(void); 76 int tegra194_miscreg_mask_serror(void); 77 #else 78 static struct tegra_sku_info tegra_sku_info __maybe_unused; 79 80 static inline u32 tegra_read_straps(void) 81 { 82 return 0; 83 } 84 85 static inline u32 tegra_read_ram_code(void) 86 { 87 return 0; 88 } 89 90 static inline int tegra_fuse_readl(unsigned long offset, u32 *value) 91 { 92 return -ENODEV; 93 } 94 95 static inline u32 tegra_read_chipid(void) 96 { 97 return 0; 98 } 99 100 static inline u8 tegra_get_chip_id(void) 101 { 102 return 0; 103 } 104 105 static inline u8 tegra_get_platform(void) 106 { 107 return 0; 108 } 109 110 static inline bool tegra_is_silicon(void) 111 { 112 return false; 113 } 114 115 static inline int tegra194_miscreg_mask_serror(void) 116 { 117 return false; 118 } 119 #endif 120 121 struct device *tegra_soc_device_register(void); 122 123 #endif /* __ASSEMBLY__ */ 124 125 #endif /* __SOC_TEGRA_FUSE_H__ */ 126