12025cf9eSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 297dd8268SLin Huang /* 397dd8268SLin Huang * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd 497dd8268SLin Huang * Author: Lin Huang <hl@rock-chips.com> 597dd8268SLin Huang */ 697dd8268SLin Huang #ifndef __SOC_ROCKCHIP_SIP_H 797dd8268SLin Huang #define __SOC_ROCKCHIP_SIP_H 897dd8268SLin Huang 997dd8268SLin Huang #define ROCKCHIP_SIP_DRAM_FREQ 0x82000008 1097dd8268SLin Huang #define ROCKCHIP_SIP_CONFIG_DRAM_INIT 0x00 1197dd8268SLin Huang #define ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE 0x01 1297dd8268SLin Huang #define ROCKCHIP_SIP_CONFIG_DRAM_ROUND_RATE 0x02 1397dd8268SLin Huang #define ROCKCHIP_SIP_CONFIG_DRAM_SET_AT_SR 0x03 1497dd8268SLin Huang #define ROCKCHIP_SIP_CONFIG_DRAM_GET_BW 0x04 1597dd8268SLin Huang #define ROCKCHIP_SIP_CONFIG_DRAM_GET_RATE 0x05 1697dd8268SLin Huang #define ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ 0x06 1797dd8268SLin Huang #define ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM 0x07 189173c5ceSEnric Balletbo i Serra #define ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD 0x08 1997dd8268SLin Huang 2097dd8268SLin Huang #endif 21